Changeset 96333 in vbox

Timestamp:

Aug 19, 2022 11:37:07 AM (2 years ago)

Author:

vboxsync

Message:

VMM/IEM: Implement divps/divpd instructions, bugref:9898

Location:

trunk/src/VBox/VMM

Files:

• VMMAll/IEMAllAImpl.asm (modified) (1 diff)
• VMMAll/IEMAllAImplC.cpp (modified) (4 diffs)
• VMMAll/IEMAllInstructionsTwoByte0f.cpp.h (modified) (1 diff)
• include/IEMInternal.h (modified) (3 diffs)
• testcase/tstIEMCheckMc.cpp (modified) (1 diff)

trunk/src/VBox/VMM/VMMAll/IEMAllAImpl.asm

@@ -4593 +4593 @@
 IEMIMPL_FP_F2 minps
 IEMIMPL_FP_F2 minpd
+IEMIMPL_FP_F2 divps
+IEMIMPL_FP_F2 divpd

trunk/src/VBox/VMM/VMMAll/IEMAllAImplC.cpp

@@ -453 +453 @@
 extern const RTFLOAT80U  g_ar80One[];
 extern const RTFLOAT80U  g_r80Indefinite;
+extern const RTFLOAT32U  g_ar32Infinity[];
+extern const RTFLOAT64U  g_ar64Infinity[];
 extern const RTFLOAT80U  g_ar80Infinity[];
 extern const RTFLOAT128U g_r128Ln2;
@@ -458 +460 @@
 extern const RTUINT128U  g_u128Ln2MantissaIntel;
 extern const RTFLOAT128U g_ar128F2xm1HornerConsts[];
+extern const RTFLOAT32U  g_ar32QNaN[];
+extern const RTFLOAT64U  g_ar64QNaN[];
 
 /** Zero values (indexed by fSign). */
@@ -472 +476 @@
 
 /** Infinities (indexed by fSign). */
+RTFLOAT32U const g_ar32Infinity[] = { RTFLOAT32U_INIT_INF(0), RTFLOAT32U_INIT_INF(1) };
+RTFLOAT64U const g_ar64Infinity[] = { RTFLOAT64U_INIT_INF(0), RTFLOAT64U_INIT_INF(1) };
 RTFLOAT80U const g_ar80Infinity[] = { RTFLOAT80U_INIT_INF(0), RTFLOAT80U_INIT_INF(1) };
+
+/** Default QNaNs (indexed by fSign). */
+RTFLOAT32U const g_ar32QNaN[] = { RTFLOAT32U_INIT_QNAN(0), RTFLOAT32U_INIT_QNAN(1) };
+RTFLOAT64U const g_ar64QNaN[] = { RTFLOAT64U_INIT_QNAN(0), RTFLOAT64U_INIT_QNAN(1) };
+
 
 #if 0
@@ -14384 +14395 @@
 }
 #endif
+
+
+/**
+ * DIVPS
+ */
+#ifdef IEM_WITHOUT_ASSEMBLY
+static uint32_t iemAImpl_divps_u128_worker(PRTFLOAT32U pr32Res, uint32_t fMxcsr, PCRTFLOAT32U pr32Val1, PCRTFLOAT32U pr32Val2)
+{
+    if (iemSseBinaryValIsNaNR32(pr32Res, pr32Val1, pr32Val2, &fMxcsr))
+        return fMxcsr;
+
+    RTFLOAT32U r32Src1, r32Src2;
+    iemSsePrepareValueR32(&r32Src1, fMxcsr, pr32Val1);
+    iemSsePrepareValueR32(&r32Src2, fMxcsr, pr32Val2);
+
+    if (RTFLOAT32U_IS_ZERO(&r32Src2))
+    {
+        if (   RTFLOAT32U_IS_ZERO(&r32Src1)
+            || RTFLOAT32U_IS_QUIET_NAN(&r32Src1))
+        {
+            *pr32Res = g_ar32QNaN[1];
+            return fMxcsr | X86_MXCSR_IE;
+        }
+        else if (RTFLOAT32U_IS_INF(&r32Src1))
+        {
+            *pr32Res = g_ar32Infinity[r32Src1.s.fSign != r32Src2.s.fSign];
+            return fMxcsr;
+        }
+        else
+        {
+            *pr32Res = g_ar32Infinity[r32Src1.s.fSign != r32Src2.s.fSign];
+            return fMxcsr | X86_MXCSR_ZE;
+        }
+    }
+
+    softfloat_state_t SoftState = IEM_SOFTFLOAT_STATE_INITIALIZER_FROM_MXCSR(fMxcsr);
+    float32_t r32Result = f32_div(iemFpSoftF32FromIprt(&r32Src1), iemFpSoftF32FromIprt(&r32Src2), &SoftState);
+    return iemSseSoftStateAndR32ToMxcsrAndIprtResult(&SoftState, r32Result, pr32Res, fMxcsr, &r32Src1, &r32Src2);
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_divps_u128,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))
+{
+    pResult->MXCSR |= iemAImpl_divps_u128_worker(&pResult->uResult.ar32[0], pFpuState->MXCSR, &puSrc1->ar32[0], &puSrc2->ar32[0]);
+    pResult->MXCSR |= iemAImpl_divps_u128_worker(&pResult->uResult.ar32[1], pFpuState->MXCSR, &puSrc1->ar32[1], &puSrc2->ar32[1]);
+    pResult->MXCSR |= iemAImpl_divps_u128_worker(&pResult->uResult.ar32[2], pFpuState->MXCSR, &puSrc1->ar32[2], &puSrc2->ar32[2]);
+    pResult->MXCSR |= iemAImpl_divps_u128_worker(&pResult->uResult.ar32[3], pFpuState->MXCSR, &puSrc1->ar32[3], &puSrc2->ar32[3]);
+}
+#endif
+
+
+/**
+ * DIVPD
+ */
+#ifdef IEM_WITHOUT_ASSEMBLY
+static uint32_t iemAImpl_divpd_u128_worker(PRTFLOAT64U pr64Res, uint32_t fMxcsr, PCRTFLOAT64U pr64Val1, PCRTFLOAT64U pr64Val2)
+{
+    if (iemSseBinaryValIsNaNR64(pr64Res, pr64Val1, pr64Val2, &fMxcsr))
+        return fMxcsr;
+
+    RTFLOAT64U r64Src1, r64Src2;
+    iemSsePrepareValueR64(&r64Src1, fMxcsr, pr64Val1);
+    iemSsePrepareValueR64(&r64Src2, fMxcsr, pr64Val2);
+
+    if (RTFLOAT64U_IS_ZERO(&r64Src2))
+    {
+        if (   RTFLOAT64U_IS_ZERO(&r64Src1)
+            || RTFLOAT64U_IS_QUIET_NAN(&r64Src1))
+        {
+            *pr64Res = g_ar64QNaN[1];
+            return fMxcsr | X86_MXCSR_IE;
+        }
+        else if (RTFLOAT64U_IS_INF(&r64Src1))
+        {
+            *pr64Res = g_ar64Infinity[r64Src1.s.fSign != r64Src2.s.fSign];
+            return fMxcsr;
+        }
+        else
+        {
+            *pr64Res = g_ar64Infinity[r64Src1.s.fSign != r64Src2.s.fSign];
+            return fMxcsr | X86_MXCSR_ZE;
+        }
+    }
+
+    softfloat_state_t SoftState = IEM_SOFTFLOAT_STATE_INITIALIZER_FROM_MXCSR(fMxcsr);
+    float64_t r64Result = f64_div(iemFpSoftF64FromIprt(&r64Src1), iemFpSoftF64FromIprt(&r64Src2), &SoftState);
+    return iemSseSoftStateAndR64ToMxcsrAndIprtResult(&SoftState, r64Result, pr64Res, fMxcsr, &r64Src1, &r64Src2);
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_divpd_u128,(PX86FXSTATE pFpuState, PIEMSSERESULT pResult, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2))
+{
+    pResult->MXCSR |= iemAImpl_divpd_u128_worker(&pResult->uResult.ar64[0], pFpuState->MXCSR, &puSrc1->ar64[0], &puSrc2->ar64[0]);
+    pResult->MXCSR |= iemAImpl_divpd_u128_worker(&pResult->uResult.ar64[1], pFpuState->MXCSR, &puSrc1->ar64[1], &puSrc2->ar64[1]);
+}
+#endif

trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsTwoByte0f.cpp.h

@@ -4027 +4027 @@
 FNIEMOP_STUB(iemOp_minsd_Vsd_Wsd);
 
+
 /** Opcode      0x0f 0x5e - divps Vps, Wps */
-FNIEMOP_STUB(iemOp_divps_Vps_Wps);
+FNIEMOP_DEF(iemOp_divps_Vps_Wps)
+{
+    IEMOP_MNEMONIC2(RM, DIVPS, divps, Vps, Wps, DISOPTYPE_HARMLESS, 0);
+    return FNIEMOP_CALL_1(iemOpCommonSseFp_FullFull_To_Full, iemAImpl_divps_u128);
+}
+
+
 /** Opcode 0x66 0x0f 0x5e - divpd Vpd, Wpd */
-FNIEMOP_STUB(iemOp_divpd_Vpd_Wpd);
+FNIEMOP_DEF(iemOp_divpd_Vpd_Wpd)
+{
+    IEMOP_MNEMONIC2(RM, DIVPD, divpd, Vpd, Wpd, DISOPTYPE_HARMLESS, 0);
+    return FNIEMOP_CALL_1(iemOpCommonSse2Fp_FullFull_To_Full, iemAImpl_divpd_u128);
+}
+
+
 /** Opcode 0xf3 0x0f 0x5e - divss Vss, Wss */
 FNIEMOP_STUB(iemOp_divss_Vss_Wss);

trunk/src/VBox/VMM/include/IEMInternal.h

@@ -2424 +2424 @@
 FNIEMAIMPLFPSSEF2U128 iemAImpl_minps_u128;
 FNIEMAIMPLFPSSEF2U128 iemAImpl_minpd_u128;
+FNIEMAIMPLFPSSEF2U128 iemAImpl_divps_u128;
+FNIEMAIMPLFPSSEF2U128 iemAImpl_divpd_u128;
 
 FNIEMAIMPLFPAVXF3U128 iemAImpl_vaddps_u128, iemAImpl_vaddps_u128_fallback;
@@ -2433 +2435 @@
 FNIEMAIMPLFPAVXF3U128 iemAImpl_vminps_u128, iemAImpl_vminps_u128_fallback;
 FNIEMAIMPLFPAVXF3U128 iemAImpl_vminpd_u128, iemAImpl_vminpd_u128_fallback;
+FNIEMAIMPLFPAVXF3U128 iemAImpl_vdivps_u128, iemAImpl_vdivps_u128_fallback;
+FNIEMAIMPLFPAVXF3U128 iemAImpl_vdivpd_u128, iemAImpl_vdivpd_u128_fallback;
 
 FNIEMAIMPLFPAVXF3U256 iemAImpl_vaddps_u256, iemAImpl_vaddps_u256_fallback;
@@ -2442 +2446 @@
 FNIEMAIMPLFPAVXF3U256 iemAImpl_vminps_u256, iemAImpl_vminps_u256_fallback;
 FNIEMAIMPLFPAVXF3U256 iemAImpl_vminpd_u256, iemAImpl_vminpd_u256_fallback;
+FNIEMAIMPLFPAVXF3U256 iemAImpl_vdivps_u256, iemAImpl_vdivps_u256_fallback;
+FNIEMAIMPLFPAVXF3U256 iemAImpl_vdivpd_u256, iemAImpl_vdivpd_u256_fallback;
 /** @} */
 

trunk/src/VBox/VMM/testcase/tstIEMCheckMc.cpp

@@ -470 +470 @@
 #define iemAImpl_minps_u128             NULL
 #define iemAImpl_minpd_u128             NULL
+#define iemAImpl_divps_u128             NULL
+#define iemAImpl_divpd_u128             NULL
 
 /** @}  */