Changeset 96435 in vbox

Timestamp:

Aug 23, 2022 10:40:19 AM (2 years ago)

Author:

vboxsync

Message:

VMM/IEM: Implement [v]lddqu instructions, bugref:9898

Location:

trunk

Files:

• include/VBox/vmm/vm.h (modified) (2 diffs)
• include/VBox/vmm/vm.mac (modified) (1 diff)
• src/VBox/VMM/VMMAll/IEMAllInstructionsTwoByte0f.cpp.h (modified) (1 diff)
• src/VBox/VMM/VMMAll/IEMAllInstructionsVexMap1.cpp.h (modified) (1 diff)

trunk/include/VBox/vmm/vm.h

@@ -146 +146 @@
         struct IEMCPU       s;
 #endif
-        uint8_t             padding[28736];     /* multiple of 64 */
+        uint8_t             padding[32832];     /* multiple of 64 */
     } iem;
 
@@ -327 +327 @@
     } em;
 
-    /** Align the structure size on 16384 boundrary for arm64 purposes. */
-    uint8_t                 abStructPadding[4096];
 } VMCPU;
 
 
 #ifndef VBOX_FOR_DTRACE_LIB
+/* Make sure the structure size is aligned on a 16384 boundary for arm64 purposes. */
 AssertCompileSizeAlignment(VMCPU, 16384);
 

trunk/include/VBox/vmm/vm.mac

@@ -58 +58 @@
 
     alignb 64
-    .iem                    resb 28736
+    .iem                    resb 32832
 
     alignb 64

trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsTwoByte0f.cpp.h

@@ -11316 +11316 @@
 /*  Opcode      0x0f 0xf0 - invalid */
 /*  Opcode 0x66 0x0f 0xf0 - invalid */
+
+
 /** Opcode 0xf2 0x0f 0xf0 - lddqu Vx, Mx */
-FNIEMOP_STUB(iemOp_lddqu_Vx_Mx);
+FNIEMOP_DEF(iemOp_lddqu_Vx_Mx)
+{
+    IEMOP_MNEMONIC2(RM_MEM, LDDQU, lddqu, Vdq_WO, Mx, DISOPTYPE_HARMLESS | DISOPTYPE_SSE, IEMOPHINT_IGNORES_OP_SIZES);
+    uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
+    if (IEM_IS_MODRM_REG_MODE(bRm))
+    {
+        /*
+         * Register, register - (not implemented, assuming it raises \#UD).
+         */
+        return IEMOP_RAISE_INVALID_OPCODE();
+    }
+    else
+    {
+        /*
+         * Register, memory.
+         */
+        IEM_MC_BEGIN(0, 2);
+        IEM_MC_LOCAL(RTUINT128U, u128Tmp);
+        IEM_MC_LOCAL(RTGCPTR,    GCPtrEffSrc);
+
+        IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
+        IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
+        IEM_MC_MAYBE_RAISE_SSE3_RELATED_XCPT();
+        IEM_MC_ACTUALIZE_SSE_STATE_FOR_CHANGE();
+        IEM_MC_FETCH_MEM_U128(u128Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
+        IEM_MC_STORE_XREG_U128(IEM_GET_MODRM_REG(pVCpu, bRm), u128Tmp);
+
+        IEM_MC_ADVANCE_RIP();
+        IEM_MC_END();
+    }
+    return VINF_SUCCESS;
+}
 
 

trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsVexMap1.cpp.h

@@ -4615 +4615 @@
 /*  Opcode VEX.0F 0xf0 - invalid */
 /*  Opcode VEX.66.0F 0xf0 - invalid */
+
+
 /** Opcode VEX.F2.0F 0xf0 - vlddqu Vx, Mx */
-FNIEMOP_STUB(iemOp_vlddqu_Vx_Mx);
+FNIEMOP_DEF(iemOp_vlddqu_Vx_Mx)
+{
+    IEMOP_MNEMONIC2(VEX_RM_MEM, VLDDQU, vlddqu, Vx_WO, Mx, DISOPTYPE_HARMLESS | DISOPTYPE_AVX, IEMOPHINT_IGNORES_OP_SIZES);
+    Assert(pVCpu->iem.s.uVexLength <= 1);
+    uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
+    if (IEM_IS_MODRM_REG_MODE(bRm))
+    {
+        /*
+         * Register, register - (not implemented, assuming it raises \#UD).
+         */
+        return IEMOP_RAISE_INVALID_OPCODE();
+    }
+    else if (pVCpu->iem.s.uVexLength == 0)
+    {
+        /*
+         * Register, memory128.
+         */
+        IEM_MC_BEGIN(0, 2);
+        IEM_MC_LOCAL(RTUINT128U, u128Tmp);
+        IEM_MC_LOCAL(RTGCPTR,    GCPtrEffSrc);
+
+        IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
+        IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
+        IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
+        IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
+
+        IEM_MC_FETCH_MEM_U128(u128Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
+        IEM_MC_STORE_YREG_U128_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), u128Tmp);
+
+        IEM_MC_ADVANCE_RIP();
+        IEM_MC_END();
+    }
+    else
+    {
+        /*
+         * Register, memory256.
+         */
+        IEM_MC_BEGIN(0, 2);
+        IEM_MC_LOCAL(RTUINT256U, u256Tmp);
+        IEM_MC_LOCAL(RTGCPTR,    GCPtrEffSrc);
+
+        IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
+        IEMOP_HLP_DONE_VEX_DECODING_NO_VVVV();
+        IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT();
+        IEM_MC_ACTUALIZE_AVX_STATE_FOR_CHANGE();
+
+        IEM_MC_FETCH_MEM_U256(u256Tmp, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
+        IEM_MC_STORE_YREG_U256_ZX_VLMAX(IEM_GET_MODRM_REG(pVCpu, bRm), u256Tmp);
+
+        IEM_MC_ADVANCE_RIP();
+        IEM_MC_END();
+    }
+    return VINF_SUCCESS;
+}
+
 
 /*  Opcode VEX.0F 0xf1 - invalid */