Changeset 96436 in vbox

Timestamp:

Aug 23, 2022 10:40:44 AM (3 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

153266

Message:

ValidationKit/bs3-cpu-instr-3: Add simple [v]lddqu instructions testcases, ​bugref:9898

Location:

trunk/src/VBox/ValidationKit/bootsectors

Files:

• bs3-cpu-instr-3-template.mac (modified) (1 diff)
• bs3-cpu-instr-3.c32 (modified) (2 diffs)

trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3-template.mac

@@ -2573 +2573 @@
  %endif
 
+;
+; [V]LDDQU
+;
+EMIT_INSTR_PLUS_ICEBP lddqu,  XMM1, FSxBX
+EMIT_INSTR_PLUS_ICEBP vlddqu, XMM1, FSxBX
+EMIT_INSTR_PLUS_ICEBP vlddqu, YMM1, FSxBX
+ %if TMPL_BITS == 64
+EMIT_INSTR_PLUS_ICEBP lddqu,  XMM10, FSxBX
+EMIT_INSTR_PLUS_ICEBP vlddqu, XMM11, FSxBX
+EMIT_INSTR_PLUS_ICEBP vlddqu, YMM12, FSxBX
+ %endif
 
 %endif ; BS3_INSTANTIATING_CMN

trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3.c32

@@ -9611 +9611 @@
     return bs3CpuInstr3_WorkerTestType3(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
                                         g_aXcptConfig5, RT_ELEMENTS(g_aXcptConfig5), X86_EFL_STATUS_BITS);
+}
+
+
+/*
+ * [V]LDDQU - Load unaligned integer from memory.
+ */
+BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_lddqu_XMM1_FSxBX_icebp);
+extern FNBS3FAR             bs3CpuInstr3_lddqu_XMM10_FSxBX_icebp_c64;
+BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vlddqu_XMM1_FSxBX_icebp);
+extern FNBS3FAR             bs3CpuInstr3_vlddqu_XMM11_FSxBX_icebp_c64;
+BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vlddqu_YMM1_FSxBX_icebp);
+extern FNBS3FAR             bs3CpuInstr3_vlddqu_YMM12_FSxBX_icebp_c64;
+
+BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_lddqu(uint8_t bMode)
+{
+    static BS3CPUINSTR3_TEST3_T const s_aTests16[] =
+    {
+        {  bs3CpuInstr3_lddqu_XMM1_FSxBX_icebp_c16,       X86_XCPT_DB, RM_MEM, T_SSE3,      1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
+
+        {  bs3CpuInstr3_vlddqu_XMM1_FSxBX_icebp_c16,      X86_XCPT_DB, RM_MEM, T_AVX_128,   1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
+        {  bs3CpuInstr3_vlddqu_YMM1_FSxBX_icebp_c16,      X86_XCPT_DB, RM_MEM, T_AVX_256,   1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
+    };
+    static BS3CPUINSTR3_TEST3_T const s_aTests32[] =
+    {
+        {  bs3CpuInstr3_lddqu_XMM1_FSxBX_icebp_c32,       X86_XCPT_DB, RM_MEM, T_SSE3,      1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
+
+        {  bs3CpuInstr3_vlddqu_XMM1_FSxBX_icebp_c32,      X86_XCPT_DB, RM_MEM, T_AVX_128,   1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
+
+        {  bs3CpuInstr3_vlddqu_YMM1_FSxBX_icebp_c32,      X86_XCPT_DB, RM_MEM, T_AVX_256,   1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
+    };
+    static BS3CPUINSTR3_TEST3_T const s_aTests64[] =
+    {
+        {  bs3CpuInstr3_lddqu_XMM1_FSxBX_icebp_c64,       X86_XCPT_DB, RM_MEM, T_SSE3,      1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
+        {  bs3CpuInstr3_lddqu_XMM10_FSxBX_icebp_c64,      X86_XCPT_DB, RM_MEM, T_SSE3,     10, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
+
+        {  bs3CpuInstr3_vlddqu_XMM1_FSxBX_icebp_c64,      X86_XCPT_DB, RM_MEM, T_AVX_128,   1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
+        {  bs3CpuInstr3_vlddqu_XMM11_FSxBX_icebp_c64,     X86_XCPT_DB, RM_MEM, T_AVX_128,  11, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
+
+        {  bs3CpuInstr3_vlddqu_YMM1_FSxBX_icebp_c64,      X86_XCPT_DB, RM_MEM, T_AVX_256,   1, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
+        {  bs3CpuInstr3_vlddqu_YMM12_FSxBX_icebp_c64,     X86_XCPT_DB, RM_MEM, T_AVX_256,  12, 255, RT_ELEMENTS(g_aMoveValues3), g_aMoveValues3 },
+    };
+    static BS3CPUINSTR3_TEST3_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST3_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
+    unsigned const                         iTest       = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
+    return bs3CpuInstr3_WorkerTestType3(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
+                                        g_aXcptConfig4Unaligned, RT_ELEMENTS(g_aXcptConfig4Unaligned), 0 /*cbMaxAlign*/);
 }
 
@@ -10070 +10115 @@
                                                             bs3CpuInstr3_v_pmovzxbw_pmovzxbd_pmovzxbq_pmovzxwd_pmovzxwq_pmovzxdq, 0 },
 #endif
-#if define(ALL_TESTS)
+#if defined(ALL_TESTS)
         { "[v]shufps",                                      bs3CpuInstr3_v_shufps, 0 },
         { "[v]shufpd",                                      bs3CpuInstr3_v_shufpd, 0 },
+#endif
+#if defined(ALL_TESTS)
+        { "[v]lddqu",                                       bs3CpuInstr3_v_lddqu, 0 },
 #endif
     };