Changeset 96455 in vbox
- Timestamp:
- Aug 24, 2022 12:54:22 PM (2 years ago)
- Location:
- trunk/src/VBox/ValidationKit/bootsectors
- Files:
-
- 2 edited
-
bs3-cpu-instr-3-template.mac (modified) (1 diff)
-
bs3-cpu-instr-3.c32 (modified) (2 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3-template.mac
r96439 r96455 2599 2599 %endif 2600 2600 2601 ; 2602 ; [V]PBLENDVB 2603 ; 2604 EMIT_INSTR_PLUS_ICEBP pblendvb, XMM1, XMM2 2605 EMIT_INSTR_PLUS_ICEBP pblendvb, XMM1, FSxBX 2606 EMIT_INSTR_PLUS_ICEBP vpblendvb, XMM1, XMM2, XMM3, XMM4 2607 EMIT_INSTR_PLUS_ICEBP vpblendvb, XMM1, XMM2, FSxBX, XMM4 2608 %if TMPL_BITS == 64 2609 EMIT_INSTR_PLUS_ICEBP pblendvb, XMM8, XMM9 2610 EMIT_INSTR_PLUS_ICEBP pblendvb, XMM8, FSxBX 2611 EMIT_INSTR_PLUS_ICEBP vpblendvb, XMM8, XMM9, XMM10, XMM11 2612 EMIT_INSTR_PLUS_ICEBP vpblendvb, XMM8, XMM9, FSxBX, XMM11 2613 %endif 2614 2615 EMIT_INSTR_PLUS_ICEBP vpblendvb, YMM1, YMM2, YMM3, YMM4 2616 EMIT_INSTR_PLUS_ICEBP vpblendvb, YMM1, YMM2, FSxBX, YMM4 2617 %if TMPL_BITS == 64 2618 EMIT_INSTR_PLUS_ICEBP vpblendvb, YMM8, YMM9, YMM10, YMM11 2619 EMIT_INSTR_PLUS_ICEBP vpblendvb, YMM8, YMM9, FSxBX, YMM11 2620 %endif 2621 2622 ; 2623 ; [V]BLENDVPS 2624 ; 2625 EMIT_INSTR_PLUS_ICEBP blendvps, XMM1, XMM2 2626 EMIT_INSTR_PLUS_ICEBP blendvps, XMM1, FSxBX 2627 EMIT_INSTR_PLUS_ICEBP vblendvps, XMM1, XMM2, XMM3, XMM4 2628 EMIT_INSTR_PLUS_ICEBP vblendvps, XMM1, XMM2, FSxBX, XMM4 2629 %if TMPL_BITS == 64 2630 EMIT_INSTR_PLUS_ICEBP blendvps, XMM8, XMM9 2631 EMIT_INSTR_PLUS_ICEBP blendvps, XMM8, FSxBX 2632 EMIT_INSTR_PLUS_ICEBP vblendvps, XMM8, XMM9, XMM10, XMM11 2633 EMIT_INSTR_PLUS_ICEBP vblendvps, XMM8, XMM9, FSxBX, XMM11 2634 %endif 2635 2636 EMIT_INSTR_PLUS_ICEBP vblendvps, YMM1, YMM2, YMM3, YMM4 2637 EMIT_INSTR_PLUS_ICEBP vblendvps, YMM1, YMM2, FSxBX, YMM4 2638 %if TMPL_BITS == 64 2639 EMIT_INSTR_PLUS_ICEBP vblendvps, YMM8, YMM9, YMM10, YMM11 2640 EMIT_INSTR_PLUS_ICEBP vblendvps, YMM8, YMM9, FSxBX, YMM11 2641 %endif 2642 2643 ; 2644 ; [V]BLENDVPD 2645 ; 2646 EMIT_INSTR_PLUS_ICEBP blendvpd, XMM1, XMM2 2647 EMIT_INSTR_PLUS_ICEBP blendvpd, XMM1, FSxBX 2648 EMIT_INSTR_PLUS_ICEBP vblendvpd, XMM1, XMM2, XMM3, XMM4 2649 EMIT_INSTR_PLUS_ICEBP vblendvpd, XMM1, XMM2, FSxBX, XMM4 2650 %if TMPL_BITS == 64 2651 EMIT_INSTR_PLUS_ICEBP blendvpd, XMM8, XMM9 2652 EMIT_INSTR_PLUS_ICEBP blendvpd, XMM8, FSxBX 2653 EMIT_INSTR_PLUS_ICEBP vblendvpd, XMM8, XMM9, XMM10, XMM11 2654 EMIT_INSTR_PLUS_ICEBP vblendvpd, XMM8, XMM9, FSxBX, XMM11 2655 %endif 2656 2657 EMIT_INSTR_PLUS_ICEBP vblendvpd, YMM1, YMM2, YMM3, YMM4 2658 EMIT_INSTR_PLUS_ICEBP vblendvpd, YMM1, YMM2, FSxBX, YMM4 2659 %if TMPL_BITS == 64 2660 EMIT_INSTR_PLUS_ICEBP vblendvpd, YMM8, YMM9, YMM10, YMM11 2661 EMIT_INSTR_PLUS_ICEBP vblendvpd, YMM8, YMM9, FSxBX, YMM11 2662 %endif 2663 2601 2664 %endif ; BS3_INSTANTIATING_CMN 2602 2665 -
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3.c32
r96439 r96455 10051 10051 return bs3CpuInstr3_WorkerTestType4(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, 10052 10052 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4), X86_EFL_STATUS_BITS); 10053 } 10054 10055 10056 /* 10057 * Test type #5 - three source MM/XMM/YMM operands. 10058 * 10059 * Probably only used by the [P]BLEND instruction. 10060 */ 10061 10062 typedef struct BS3CPUINSTR3_TEST5_VALUES_T 10063 { 10064 RTUINT256U uSrc3; 10065 RTUINT256U uSrc2; 10066 RTUINT256U uSrc1; 10067 RTUINT256U uDstOut; 10068 } BS3CPUINSTR3_TEST5_VALUES_T; 10069 10070 typedef struct BS3CPUINSTR3_TEST5_T 10071 { 10072 FPFNBS3FAR pfnWorker; 10073 uint8_t bAvxMisalignXcpt; 10074 uint8_t enmRm; 10075 uint8_t enmType; 10076 uint8_t iRegDst; 10077 uint8_t iRegSrc1; 10078 uint8_t iRegSrc2; 10079 uint8_t iRegSrc3; 10080 uint8_t cValues; 10081 BS3CPUINSTR3_TEST5_VALUES_T const BS3_FAR *paValues; 10082 } BS3CPUINSTR3_TEST5_T; 10083 10084 typedef struct BS3CPUINSTR3_TEST5_MODE_T 10085 { 10086 BS3CPUINSTR3_TEST5_T const BS3_FAR *paTests; 10087 unsigned cTests; 10088 } BS3CPUINSTR3_TEST5_MODE_T; 10089 10090 /** Initializer for a BS3CPUINSTR3_TEST5_MODE_T array (three entries). */ 10091 #define BS3CPUINSTR3_TEST5_MODES_INIT(a_aTests16, a_aTests32, a_aTests64) \ 10092 { { a_aTests16, RT_ELEMENTS(a_aTests16) }, { a_aTests32, RT_ELEMENTS(a_aTests32) }, { a_aTests64, RT_ELEMENTS(a_aTests64) } } 10093 10094 10095 /** 10096 * Test type #5 worker. 10097 */ 10098 static uint8_t bs3CpuInstr3_WorkerTestType5(uint8_t bMode, BS3CPUINSTR3_TEST5_T const BS3_FAR *paTests, unsigned cTests, 10099 PCBS3CPUINSTR3_CONFIG_T paConfigs, unsigned cConfigs) 10100 { 10101 BS3REGCTX Ctx; 10102 BS3TRAPFRAME TrapFrame; 10103 const char BS3_FAR * const pszMode = Bs3GetModeName(bMode); 10104 uint8_t bRing = BS3_MODE_IS_V86(bMode) ? 3 : 0; 10105 uint8_t BS3_FAR *pbBuf = g_pbBuf; 10106 uint32_t cbBuf = g_cbBuf; 10107 PBS3EXTCTX pExtCtxOut; 10108 PBS3EXTCTX pExtCtx = bs3CpuInstr3AllocExtCtxs(&pExtCtxOut); 10109 if (!pExtCtx) 10110 return 0; 10111 10112 /* Ensure the structures are allocated before we sample the stack pointer. */ 10113 Bs3MemSet(&Ctx, 0, sizeof(Ctx)); 10114 Bs3MemSet(&TrapFrame, 0, sizeof(TrapFrame)); 10115 10116 /* 10117 * Create test context. 10118 */ 10119 pbBuf = bs3CpuInstr3BufSetup(pbBuf, &cbBuf, bMode); 10120 Bs3RegCtxSaveForMode(&Ctx, bMode, 1024); 10121 bs3CpuInstr3SetupSseAndAvx(&Ctx, pExtCtx); 10122 //Bs3TestPrintf("FTW=%#x mm1/st1=%.16Rhxs\n", pExtCtx->Ctx.x87.FTW, &pExtCtx->Ctx.x87.aRegs[1]); 10123 10124 /* 10125 * Run the tests in all rings since alignment issues may behave 10126 * differently in ring-3 compared to ring-0. 10127 */ 10128 for (;;) 10129 { 10130 unsigned iCfg; 10131 for (iCfg = 0; iCfg < cConfigs; iCfg++) 10132 { 10133 unsigned iTest; 10134 BS3CPUINSTR3_CONFIG_SAVED_T SavedCfg; 10135 if (!bs3CpuInstr3ConfigReconfigure(&SavedCfg, &Ctx, pExtCtx, &paConfigs[iCfg], bMode)) 10136 continue; /* unsupported config */ 10137 10138 /* 10139 * Iterate the tests. 10140 */ 10141 for (iTest = 0; iTest < cTests; iTest++) 10142 { 10143 BS3CPUINSTR3_TEST5_VALUES_T const BS3_FAR *paValues = paTests[iTest].paValues; 10144 uint8_t const cbInstr = ((uint8_t const BS3_FAR *)(uintptr_t)paTests[iTest].pfnWorker)[-1]; 10145 unsigned const cValues = paTests[iTest].cValues; 10146 bool const fMmxInstr = paTests[iTest].enmType < T_SSE; 10147 bool const fSseInstr = paTests[iTest].enmType >= T_SSE && paTests[iTest].enmType < T_AVX_128; 10148 bool const fAvxInstr = paTests[iTest].enmType >= T_AVX_128; 10149 uint8_t const cbOperand = paTests[iTest].enmType < T_128BITS ? 64/8 10150 : paTests[iTest].enmType < T_256BITS ? 128/8 : 256/8; 10151 uint8_t const cbMemOp = bs3CpuInstr3MemOpSize(cbOperand, paTests[iTest].enmRm); 10152 uint8_t const cbAlign = cbMemOp; 10153 PRTUINT256U puMemOp = bs3CpuInstr3BufForOperand(pbBuf, cbBuf, cbMemOp, cbAlign, &paConfigs[iCfg]); 10154 uint8_t bXcptExpect = !g_afTypeSupports[paTests[iTest].enmType] ? X86_XCPT_UD 10155 : fMmxInstr ? paConfigs[iCfg].bXcptMmx 10156 : fSseInstr ? paConfigs[iCfg].bXcptSse 10157 : BS3_MODE_IS_RM_OR_V86(bMode) ? X86_XCPT_UD : paConfigs[iCfg].bXcptAvx; 10158 uint16_t idTestStep = bRing * 10000 + iCfg * 100 + iTest * 10; 10159 unsigned iVal; 10160 10161 /* If testing unaligned memory accesses, skip register-only tests. This allows 10162 setting bXcptMmx, bXcptSse and bXcptAvx to reflect the misaligned exceptions. */ 10163 if (paTests[iTest].enmRm == RM_REG && (!paConfigs[iCfg].fAligned || paConfigs[iCfg].fAlignCheck)) 10164 continue; 10165 10166 /* #AC is only raised in ring-3.: */ 10167 if (bXcptExpect == X86_XCPT_AC) 10168 { 10169 if (bRing != 3) 10170 bXcptExpect = X86_XCPT_DB; 10171 else if (fAvxInstr) 10172 bXcptExpect = paTests[iTest].bAvxMisalignXcpt; /* they generally don't raise #AC */ 10173 } 10174 10175 Bs3RegCtxSetRipCsFromCurPtr(&Ctx, paTests[iTest].pfnWorker); 10176 10177 /* 10178 * Iterate the test values and do the actual testing. 10179 */ 10180 for (iVal = 0; iVal < cValues; iVal++, idTestStep++) 10181 { 10182 uint16_t cErrors; 10183 uint16_t uSavedFtw = 0xff; 10184 RTUINT256U uMemOpExpect; 10185 10186 /* 10187 * Set up the context and some expectations. 10188 */ 10189 /* dest */ 10190 if (paTests[iTest].iRegDst == UINT8_MAX) 10191 { 10192 BS3_ASSERT(paTests[iTest].enmRm >= RM_MEM); 10193 Bs3MemSet(puMemOp, 0xcc, cbMemOp); 10194 if (bXcptExpect == X86_XCPT_DB) 10195 uMemOpExpect = paValues[iVal].uDstOut; 10196 else 10197 Bs3MemSet(&uMemOpExpect, 0xcc, sizeof(uMemOpExpect)); 10198 } 10199 else if (fMmxInstr) 10200 Bs3ExtCtxSetMm(pExtCtx, paTests[iTest].iRegSrc2, ~paValues[iVal].uDstOut.QWords.qw0, BS3EXTCTXTOPMM_ZERO); 10201 10202 /* source #1 (/ destination for MMX and SSE) */ 10203 if (paTests[iTest].iRegSrc1 == UINT8_MAX) 10204 { 10205 BS3_ASSERT(paTests[iTest].enmRm >= RM_MEM); 10206 Bs3MemCpy(puMemOp, &paValues[iVal].uSrc1, cbMemOp); 10207 if (paTests[iTest].iRegDst == UINT8_MAX) 10208 BS3_ASSERT(fSseInstr); 10209 else 10210 uMemOpExpect = paValues[iVal].uSrc1; 10211 } 10212 else if (fMmxInstr) 10213 Bs3ExtCtxSetMm(pExtCtx, paTests[iTest].iRegSrc1, paValues[iVal].uSrc1.QWords.qw0, BS3EXTCTXTOPMM_ZERO); 10214 else if (fSseInstr) 10215 Bs3ExtCtxSetXmm(pExtCtx, paTests[iTest].iRegSrc1, &paValues[iVal].uSrc1.DQWords.dqw0); 10216 else 10217 Bs3ExtCtxSetYmm(pExtCtx, paTests[iTest].iRegSrc1, &paValues[iVal].uSrc1, 32); 10218 10219 /* source #2 */ 10220 if (paTests[iTest].iRegSrc2 == UINT8_MAX) 10221 { 10222 BS3_ASSERT(paTests[iTest].enmRm >= RM_MEM); 10223 BS3_ASSERT(paTests[iTest].iRegDst != UINT8_MAX && paTests[iTest].iRegSrc1 != UINT8_MAX); 10224 Bs3MemCpy(puMemOp, &paValues[iVal].uSrc2, cbMemOp); 10225 uMemOpExpect = paValues[iVal].uSrc2; 10226 } 10227 else if (fMmxInstr) 10228 Bs3ExtCtxSetMm(pExtCtx, paTests[iTest].iRegSrc2, paValues[iVal].uSrc2.QWords.qw0, BS3EXTCTXTOPMM_ZERO); 10229 else if (fSseInstr) 10230 Bs3ExtCtxSetXmm(pExtCtx, paTests[iTest].iRegSrc2, &paValues[iVal].uSrc2.DQWords.dqw0); 10231 else 10232 Bs3ExtCtxSetYmm(pExtCtx, paTests[iTest].iRegSrc2, &paValues[iVal].uSrc2, 32); 10233 10234 /* source #3 */ 10235 if (paTests[iTest].iRegSrc3 == UINT8_MAX) 10236 { 10237 BS3_ASSERT(paTests[iTest].enmRm >= RM_MEM); 10238 BS3_ASSERT(paTests[iTest].iRegDst != UINT8_MAX && paTests[iTest].iRegSrc1 != UINT8_MAX); 10239 Bs3MemCpy(puMemOp, &paValues[iVal].uSrc3, cbMemOp); 10240 uMemOpExpect = paValues[iVal].uSrc3; 10241 } 10242 else if (fMmxInstr) 10243 Bs3ExtCtxSetMm(pExtCtx, paTests[iTest].iRegSrc3, paValues[iVal].uSrc3.QWords.qw0, BS3EXTCTXTOPMM_ZERO); 10244 else if (fSseInstr) 10245 Bs3ExtCtxSetXmm(pExtCtx, paTests[iTest].iRegSrc3, &paValues[iVal].uSrc3.DQWords.dqw0); 10246 else 10247 Bs3ExtCtxSetYmm(pExtCtx, paTests[iTest].iRegSrc3, &paValues[iVal].uSrc3, 32); 10248 10249 /* Memory pointer. */ 10250 if (paTests[iTest].enmRm >= RM_MEM) 10251 { 10252 BS3_ASSERT( paTests[iTest].iRegDst == UINT8_MAX 10253 || paTests[iTest].iRegSrc1 == UINT8_MAX 10254 || paTests[iTest].iRegSrc2 == UINT8_MAX 10255 || paTests[iTest].iRegSrc3 == UINT8_MAX); 10256 Bs3RegCtxSetGrpSegFromCurPtr(&Ctx, &Ctx.rbx, &Ctx.fs, puMemOp); 10257 } 10258 10259 /* 10260 * Execute. 10261 */ 10262 Bs3TrapSetJmpAndRestoreWithExtCtxAndRm(&Ctx, pExtCtx, &TrapFrame, pExtCtxOut); 10263 10264 /* 10265 * Check the result: 10266 */ 10267 cErrors = Bs3TestSubErrorCount(); 10268 10269 if (fMmxInstr && bXcptExpect == X86_XCPT_DB) 10270 { 10271 uSavedFtw = Bs3ExtCtxGetAbridgedFtw(pExtCtx); 10272 Bs3ExtCtxSetAbridgedFtw(pExtCtx, 0xff); /* Observed on 10980xe after pxor mm1, mm2. */ 10273 } 10274 if (bXcptExpect == X86_XCPT_DB && paTests[iTest].iRegDst != UINT8_MAX) 10275 { 10276 if (fMmxInstr) 10277 Bs3ExtCtxSetMm(pExtCtx, paTests[iTest].iRegDst, paValues[iVal].uDstOut.QWords.qw0, BS3EXTCTXTOPMM_SET); 10278 else if (fSseInstr) 10279 Bs3ExtCtxSetXmm(pExtCtx, paTests[iTest].iRegDst, &paValues[iVal].uDstOut.DQWords.dqw0); 10280 else 10281 Bs3ExtCtxSetYmm(pExtCtx, paTests[iTest].iRegDst, &paValues[iVal].uDstOut, cbOperand); 10282 } 10283 Bs3TestCheckExtCtx(pExtCtxOut, pExtCtx, 0 /*fFlags*/, pszMode, idTestStep); 10284 10285 if (TrapFrame.bXcpt != bXcptExpect) 10286 Bs3TestFailedF("Expected bXcpt = %#x, got %#x", bXcptExpect, TrapFrame.bXcpt); 10287 10288 /* Kludge! Looks like EFLAGS.AC is cleared when raising #GP in real mode on the 10980XE. WEIRD! */ 10289 if (bMode == BS3_MODE_RM && (Ctx.rflags.u32 & X86_EFL_AC)) 10290 { 10291 if (TrapFrame.Ctx.rflags.u32 & X86_EFL_AC) 10292 Bs3TestFailedF("Expected EFLAGS.AC to be cleared (bXcpt=%d)", TrapFrame.bXcpt); 10293 TrapFrame.Ctx.rflags.u32 |= X86_EFL_AC; 10294 } 10295 Bs3TestCheckRegCtxEx(&TrapFrame.Ctx, &Ctx, bXcptExpect == X86_XCPT_DB ? cbInstr + 1 : 0, 0, 10296 bXcptExpect == X86_XCPT_DB || BS3_MODE_IS_16BIT_SYS(bMode) ? 0 : X86_EFL_RF, 10297 pszMode, idTestStep); 10298 10299 if ( paTests[iTest].enmRm >= RM_MEM 10300 && Bs3MemCmp(puMemOp, &uMemOpExpect, cbMemOp) != 0) 10301 Bs3TestFailedF("Expected uMemOp %.*Rhxs, got %.*Rhxs", cbMemOp, &uMemOpExpect, cbMemOp, puMemOp); 10302 10303 if (cErrors != Bs3TestSubErrorCount()) 10304 { 10305 if (paConfigs[iCfg].fAligned) 10306 Bs3TestFailedF("ring-%d/cfg#%u/test#%u/value#%u failed (bXcptExpect=%#x)", 10307 bRing, iCfg, iTest, iVal, bXcptExpect); 10308 else 10309 Bs3TestFailedF("ring-%d/cfg#%u/test#%u/value#%u failed (bXcptExpect=%#x, puMemOp=%p, EFLAGS=%#RX32, CR0=%#RX32)", 10310 bRing, iCfg, iTest, iVal, bXcptExpect, puMemOp, TrapFrame.Ctx.rflags.u32, TrapFrame.Ctx.cr0); 10311 Bs3TestPrintf("\n"); 10312 } 10313 10314 if (uSavedFtw != 0xff) 10315 Bs3ExtCtxSetAbridgedFtw(pExtCtx, uSavedFtw); 10316 } 10317 } 10318 10319 bs3CpuInstr3ConfigRestore(&SavedCfg, &Ctx, pExtCtx); 10320 } 10321 10322 /* 10323 * Next ring. 10324 */ 10325 bRing++; 10326 if (bRing > 3 || bMode == BS3_MODE_RM) 10327 break; 10328 Bs3RegCtxConvertToRingX(&Ctx, bRing); 10329 } 10330 10331 /* 10332 * Cleanup. 10333 */ 10334 bs3CpuInstr3BufCleanup(pbBuf, cbBuf, bMode); 10335 bs3CpuInstr3FreeExtCtxs(pExtCtx, pExtCtxOut); 10336 return 0; 10337 } 10338 10339 10340 /* 10341 * PBLENDVB 10342 */ 10343 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pblendvb_XMM1_XMM2_icebp); 10344 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pblendvb_XMM1_FSxBX_icebp); 10345 extern FNBS3FAR bs3CpuInstr3_pblendvb_XMM8_XMM9_icebp_c64; 10346 extern FNBS3FAR bs3CpuInstr3_pblendvb_XMM8_FSxBX_icebp_c64; 10347 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpblendvb_XMM1_XMM2_XMM3_XMM4_icebp); 10348 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpblendvb_XMM1_XMM2_FSxBX_XMM4_icebp); 10349 extern FNBS3FAR bs3CpuInstr3_vpblendvb_XMM8_XMM9_XMM10_XMM11_icebp_c64; 10350 extern FNBS3FAR bs3CpuInstr3_vpblendvb_XMM8_XMM9_FSxBX_XMM11_icebp_c64; 10351 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpblendvb_YMM1_YMM2_YMM3_YMM4_icebp); 10352 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpblendvb_YMM1_YMM2_FSxBX_YMM4_icebp); 10353 extern FNBS3FAR bs3CpuInstr3_vpblendvb_YMM8_YMM9_YMM10_YMM11_icebp_c64; 10354 extern FNBS3FAR bs3CpuInstr3_vpblendvb_YMM8_YMM9_FSxBX_YMM11_icebp_c64; 10355 10356 BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_pblendvb(uint8_t bMode) 10357 { 10358 static BS3CPUINSTR3_TEST5_VALUES_T const s_aValues[] = 10359 { 10360 { /*mask*/ RTUINT256_INIT_C(0, 0, 0, 0), 10361 /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), 10362 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), 10363 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, 10364 { /*mask*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), 10365 /*src2*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), 10366 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), 10367 /* => */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff) }, 10368 { /*mask*/ RTUINT256_INIT_C(0x0000008000000000, 0x0000091000007f00, 0, 0x8080808080808080), 10369 /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), 10370 /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), 10371 /* => */ RTUINT256_INIT_C(0xb1b2b3f4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0xc1c2c3c4c5c6c7c8) }, 10372 { /*mask*/ RTUINT256_INIT_C(0x8080808080808080, 0x8080808080808080, 0x8080808080808080, 0x8080808080808080), 10373 /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), 10374 /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), 10375 /* => */ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8) }, 10376 { /*mask*/ RTUINT256_INIT_C(0x1234567890abcdef, 0xfedcba0987654321, 0xfedcba0987654321, 0x1234567890abcdef), 10377 /*src2*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), 10378 /*src1*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), 10379 /* => */ RTUINT256_INIT_C(0xddddeeee77778888, 0x111122aa33bbcccc, 0x111122aa33bbcccc, 0xddddeeee77778888) }, 10380 }; 10381 10382 static BS3CPUINSTR3_TEST5_T const s_aTests16[] = 10383 { 10384 { bs3CpuInstr3_pblendvb_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 1, 2, 0, RT_ELEMENTS(s_aValues), s_aValues }, 10385 { bs3CpuInstr3_pblendvb_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE4_1, 1, 1, 255, 0, RT_ELEMENTS(s_aValues), s_aValues }, 10386 10387 { bs3CpuInstr3_vpblendvb_XMM1_XMM2_XMM3_XMM4_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, 4, RT_ELEMENTS(s_aValues), s_aValues }, 10388 { bs3CpuInstr3_vpblendvb_XMM1_XMM2_FSxBX_XMM4_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, 4, RT_ELEMENTS(s_aValues), s_aValues }, 10389 { bs3CpuInstr3_vpblendvb_YMM1_YMM2_YMM3_YMM4_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, 3, 4, RT_ELEMENTS(s_aValues), s_aValues }, 10390 { bs3CpuInstr3_vpblendvb_YMM1_YMM2_FSxBX_YMM4_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 2, 255, 4, RT_ELEMENTS(s_aValues), s_aValues }, 10391 }; 10392 static BS3CPUINSTR3_TEST5_T const s_aTests32[] = 10393 { 10394 { bs3CpuInstr3_pblendvb_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 1, 2, 0, RT_ELEMENTS(s_aValues), s_aValues }, 10395 { bs3CpuInstr3_pblendvb_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE4_1, 1, 1, 255, 0, RT_ELEMENTS(s_aValues), s_aValues }, 10396 10397 { bs3CpuInstr3_vpblendvb_XMM1_XMM2_XMM3_XMM4_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, 4, RT_ELEMENTS(s_aValues), s_aValues }, 10398 { bs3CpuInstr3_vpblendvb_XMM1_XMM2_FSxBX_XMM4_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, 4, RT_ELEMENTS(s_aValues), s_aValues }, 10399 { bs3CpuInstr3_vpblendvb_YMM1_YMM2_YMM3_YMM4_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, 3, 4, RT_ELEMENTS(s_aValues), s_aValues }, 10400 { bs3CpuInstr3_vpblendvb_YMM1_YMM2_FSxBX_YMM4_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 2, 255, 4, RT_ELEMENTS(s_aValues), s_aValues }, 10401 }; 10402 static BS3CPUINSTR3_TEST5_T const s_aTests64[] = 10403 { 10404 { bs3CpuInstr3_pblendvb_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 1, 2, 0, RT_ELEMENTS(s_aValues), s_aValues }, 10405 { bs3CpuInstr3_pblendvb_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 1, 1, 255, 0, RT_ELEMENTS(s_aValues), s_aValues }, 10406 { bs3CpuInstr3_pblendvb_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE4_1, 8, 8, 9, 0, RT_ELEMENTS(s_aValues), s_aValues }, 10407 { bs3CpuInstr3_pblendvb_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 8, 8, 255, 0, RT_ELEMENTS(s_aValues), s_aValues }, 10408 10409 { bs3CpuInstr3_vpblendvb_XMM1_XMM2_XMM3_XMM4_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, 4, RT_ELEMENTS(s_aValues), s_aValues }, 10410 { bs3CpuInstr3_vpblendvb_XMM1_XMM2_FSxBX_XMM4_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, 4, RT_ELEMENTS(s_aValues), s_aValues }, 10411 { bs3CpuInstr3_vpblendvb_XMM8_XMM9_XMM10_XMM11_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, 11, RT_ELEMENTS(s_aValues), s_aValues }, 10412 { bs3CpuInstr3_vpblendvb_XMM8_XMM9_FSxBX_XMM11_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, 11, RT_ELEMENTS(s_aValues), s_aValues }, 10413 10414 { bs3CpuInstr3_vpblendvb_YMM1_YMM2_YMM3_YMM4_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, 3, 4, RT_ELEMENTS(s_aValues), s_aValues }, 10415 { bs3CpuInstr3_vpblendvb_YMM1_YMM2_FSxBX_YMM4_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 2, 255, 4, RT_ELEMENTS(s_aValues), s_aValues }, 10416 { bs3CpuInstr3_vpblendvb_YMM8_YMM9_YMM10_YMM11_icebp_c64, 255, RM_REG, T_AVX_256, 8, 9, 10, 11, RT_ELEMENTS(s_aValues), s_aValues }, 10417 { bs3CpuInstr3_vpblendvb_YMM8_YMM9_FSxBX_YMM11_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 8, 9, 255, 11, RT_ELEMENTS(s_aValues), s_aValues }, 10418 }; 10419 static BS3CPUINSTR3_TEST5_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST5_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); 10420 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); 10421 return bs3CpuInstr3_WorkerTestType5(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, 10422 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); 10423 } 10424 10425 10426 /* 10427 * BLENDPS 10428 */ 10429 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_blendvps_XMM1_XMM2_icebp); 10430 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_blendvps_XMM1_FSxBX_icebp); 10431 extern FNBS3FAR bs3CpuInstr3_blendvps_XMM8_XMM9_icebp_c64; 10432 extern FNBS3FAR bs3CpuInstr3_blendvps_XMM8_FSxBX_icebp_c64; 10433 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vblendvps_XMM1_XMM2_XMM3_XMM4_icebp); 10434 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vblendvps_XMM1_XMM2_FSxBX_XMM4_icebp); 10435 extern FNBS3FAR bs3CpuInstr3_vblendvps_XMM8_XMM9_XMM10_XMM11_icebp_c64; 10436 extern FNBS3FAR bs3CpuInstr3_vblendvps_XMM8_XMM9_FSxBX_XMM11_icebp_c64; 10437 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vblendvps_YMM1_YMM2_YMM3_YMM4_icebp); 10438 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vblendvps_YMM1_YMM2_FSxBX_YMM4_icebp); 10439 extern FNBS3FAR bs3CpuInstr3_vblendvps_YMM8_YMM9_YMM10_YMM11_icebp_c64; 10440 extern FNBS3FAR bs3CpuInstr3_vblendvps_YMM8_YMM9_FSxBX_YMM11_icebp_c64; 10441 10442 BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_blendvps(uint8_t bMode) 10443 { 10444 static BS3CPUINSTR3_TEST5_VALUES_T const s_aValues[] = 10445 { 10446 { /*mask*/ RTUINT256_INIT_C(0, 0, 0, 0), 10447 /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), 10448 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), 10449 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, 10450 { /*mask*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), 10451 /*src2*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), 10452 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), 10453 /* => */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff) }, 10454 { /*mask*/ RTUINT256_INIT_C(0x0000008000000000, 0x0000091000007f00, 0, 0x8080808080808080), 10455 /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), 10456 /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), 10457 /* => */ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0xc1c2c3c4c5c6c7c8) }, 10458 { /*mask*/ RTUINT256_INIT_C(0x8080808080808080, 0x8080808080808080, 0x8080808080808080, 0x8080808080808080), 10459 /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), 10460 /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), 10461 /* => */ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8) }, 10462 { /*mask*/ RTUINT256_INIT_C(0x1234567890abcdef, 0xfedcba0987654321, 0xfedcba0987654321, 0x1234567890abcdef), 10463 /*src2*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), 10464 /*src1*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), 10465 /* => */ RTUINT256_INIT_C(0xddddeeee77778888, 0x1111222233334444, 0x1111222233334444, 0xddddeeee77778888) }, 10466 }; 10467 10468 static BS3CPUINSTR3_TEST5_T const s_aTests16[] = 10469 { 10470 { bs3CpuInstr3_blendvps_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 1, 2, 0, RT_ELEMENTS(s_aValues), s_aValues }, 10471 { bs3CpuInstr3_blendvps_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE4_1, 1, 1, 255, 0, RT_ELEMENTS(s_aValues), s_aValues }, 10472 10473 { bs3CpuInstr3_vblendvps_XMM1_XMM2_XMM3_XMM4_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, 4, RT_ELEMENTS(s_aValues), s_aValues }, 10474 { bs3CpuInstr3_vblendvps_XMM1_XMM2_FSxBX_XMM4_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, 4, RT_ELEMENTS(s_aValues), s_aValues }, 10475 { bs3CpuInstr3_vblendvps_YMM1_YMM2_YMM3_YMM4_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, 3, 4, RT_ELEMENTS(s_aValues), s_aValues }, 10476 { bs3CpuInstr3_vblendvps_YMM1_YMM2_FSxBX_YMM4_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 2, 255, 4, RT_ELEMENTS(s_aValues), s_aValues }, 10477 }; 10478 static BS3CPUINSTR3_TEST5_T const s_aTests32[] = 10479 { 10480 { bs3CpuInstr3_blendvps_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 1, 2, 0, RT_ELEMENTS(s_aValues), s_aValues }, 10481 { bs3CpuInstr3_blendvps_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE4_1, 1, 1, 255, 0, RT_ELEMENTS(s_aValues), s_aValues }, 10482 10483 { bs3CpuInstr3_vblendvps_XMM1_XMM2_XMM3_XMM4_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, 4, RT_ELEMENTS(s_aValues), s_aValues }, 10484 { bs3CpuInstr3_vblendvps_XMM1_XMM2_FSxBX_XMM4_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, 4, RT_ELEMENTS(s_aValues), s_aValues }, 10485 { bs3CpuInstr3_vblendvps_YMM1_YMM2_YMM3_YMM4_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, 3, 4, RT_ELEMENTS(s_aValues), s_aValues }, 10486 { bs3CpuInstr3_vblendvps_YMM1_YMM2_FSxBX_YMM4_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 2, 255, 4, RT_ELEMENTS(s_aValues), s_aValues }, 10487 }; 10488 static BS3CPUINSTR3_TEST5_T const s_aTests64[] = 10489 { 10490 { bs3CpuInstr3_blendvps_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 1, 2, 0, RT_ELEMENTS(s_aValues), s_aValues }, 10491 { bs3CpuInstr3_blendvps_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 1, 1, 255, 0, RT_ELEMENTS(s_aValues), s_aValues }, 10492 { bs3CpuInstr3_blendvps_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE4_1, 8, 8, 9, 0, RT_ELEMENTS(s_aValues), s_aValues }, 10493 { bs3CpuInstr3_blendvps_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 8, 8, 255, 0, RT_ELEMENTS(s_aValues), s_aValues }, 10494 10495 { bs3CpuInstr3_vblendvps_XMM1_XMM2_XMM3_XMM4_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, 4, RT_ELEMENTS(s_aValues), s_aValues }, 10496 { bs3CpuInstr3_vblendvps_XMM1_XMM2_FSxBX_XMM4_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, 4, RT_ELEMENTS(s_aValues), s_aValues }, 10497 { bs3CpuInstr3_vblendvps_XMM8_XMM9_XMM10_XMM11_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, 11, RT_ELEMENTS(s_aValues), s_aValues }, 10498 { bs3CpuInstr3_vblendvps_XMM8_XMM9_FSxBX_XMM11_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, 11, RT_ELEMENTS(s_aValues), s_aValues }, 10499 10500 { bs3CpuInstr3_vblendvps_YMM1_YMM2_YMM3_YMM4_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, 3, 4, RT_ELEMENTS(s_aValues), s_aValues }, 10501 { bs3CpuInstr3_vblendvps_YMM1_YMM2_FSxBX_YMM4_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 2, 255, 4, RT_ELEMENTS(s_aValues), s_aValues }, 10502 { bs3CpuInstr3_vblendvps_YMM8_YMM9_YMM10_YMM11_icebp_c64, 255, RM_REG, T_AVX_256, 8, 9, 10, 11, RT_ELEMENTS(s_aValues), s_aValues }, 10503 { bs3CpuInstr3_vblendvps_YMM8_YMM9_FSxBX_YMM11_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 8, 9, 255, 11, RT_ELEMENTS(s_aValues), s_aValues }, 10504 }; 10505 static BS3CPUINSTR3_TEST5_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST5_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); 10506 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); 10507 return bs3CpuInstr3_WorkerTestType5(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, 10508 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); 10509 } 10510 10511 10512 /* 10513 * BLENDPD 10514 */ 10515 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_blendvpd_XMM1_XMM2_icebp); 10516 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_blendvpd_XMM1_FSxBX_icebp); 10517 extern FNBS3FAR bs3CpuInstr3_blendvpd_XMM8_XMM9_icebp_c64; 10518 extern FNBS3FAR bs3CpuInstr3_blendvpd_XMM8_FSxBX_icebp_c64; 10519 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vblendvpd_XMM1_XMM2_XMM3_XMM4_icebp); 10520 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vblendvpd_XMM1_XMM2_FSxBX_XMM4_icebp); 10521 extern FNBS3FAR bs3CpuInstr3_vblendvpd_XMM8_XMM9_XMM10_XMM11_icebp_c64; 10522 extern FNBS3FAR bs3CpuInstr3_vblendvpd_XMM8_XMM9_FSxBX_XMM11_icebp_c64; 10523 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vblendvpd_YMM1_YMM2_YMM3_YMM4_icebp); 10524 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vblendvpd_YMM1_YMM2_FSxBX_YMM4_icebp); 10525 extern FNBS3FAR bs3CpuInstr3_vblendvpd_YMM8_YMM9_YMM10_YMM11_icebp_c64; 10526 extern FNBS3FAR bs3CpuInstr3_vblendvpd_YMM8_YMM9_FSxBX_YMM11_icebp_c64; 10527 10528 BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_blendvpd(uint8_t bMode) 10529 { 10530 static BS3CPUINSTR3_TEST5_VALUES_T const s_aValues[] = 10531 { 10532 { /*mask*/ RTUINT256_INIT_C(0, 0, 0, 0), 10533 /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), 10534 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), 10535 /* => */ RTUINT256_INIT_C(0, 0, 0, 0) }, 10536 { /*mask*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), 10537 /*src2*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), 10538 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), 10539 /* => */ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff) }, 10540 { /*mask*/ RTUINT256_INIT_C(0x0000008000000000, 0x0000091000007f00, 0, 0x8080808080808080), 10541 /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), 10542 /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), 10543 /* => */ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0xc1c2c3c4c5c6c7c8) }, 10544 { /*mask*/ RTUINT256_INIT_C(0x8080808080808080, 0x8080808080808080, 0x8080808080808080, 0x8080808080808080), 10545 /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), 10546 /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), 10547 /* => */ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8) }, 10548 { /*mask*/ RTUINT256_INIT_C(0x1234567890abcdef, 0xfedcba0987654321, 0xfedcba0987654321, 0x1234567890abcdef), 10549 /*src2*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), 10550 /*src1*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), 10551 /* => */ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x1111222233334444, 0x1111222233334444, 0xddddeeeeffff0000) }, 10552 }; 10553 10554 static BS3CPUINSTR3_TEST5_T const s_aTests16[] = 10555 { 10556 { bs3CpuInstr3_blendvpd_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SSE4_1, 1, 1, 2, 0, RT_ELEMENTS(s_aValues), s_aValues }, 10557 { bs3CpuInstr3_blendvpd_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SSE4_1, 1, 1, 255, 0, RT_ELEMENTS(s_aValues), s_aValues }, 10558 10559 { bs3CpuInstr3_vblendvpd_XMM1_XMM2_XMM3_XMM4_icebp_c16, 255, RM_REG, T_AVX_128, 1, 2, 3, 4, RT_ELEMENTS(s_aValues), s_aValues }, 10560 { bs3CpuInstr3_vblendvpd_XMM1_XMM2_FSxBX_XMM4_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, 4, RT_ELEMENTS(s_aValues), s_aValues }, 10561 { bs3CpuInstr3_vblendvpd_YMM1_YMM2_YMM3_YMM4_icebp_c16, 255, RM_REG, T_AVX_256, 1, 2, 3, 4, RT_ELEMENTS(s_aValues), s_aValues }, 10562 { bs3CpuInstr3_vblendvpd_YMM1_YMM2_FSxBX_YMM4_icebp_c16, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 2, 255, 4, RT_ELEMENTS(s_aValues), s_aValues }, 10563 }; 10564 static BS3CPUINSTR3_TEST5_T const s_aTests32[] = 10565 { 10566 { bs3CpuInstr3_blendvpd_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SSE4_1, 1, 1, 2, 0, RT_ELEMENTS(s_aValues), s_aValues }, 10567 { bs3CpuInstr3_blendvpd_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SSE4_1, 1, 1, 255, 0, RT_ELEMENTS(s_aValues), s_aValues }, 10568 10569 { bs3CpuInstr3_vblendvpd_XMM1_XMM2_XMM3_XMM4_icebp_c32, 255, RM_REG, T_AVX_128, 1, 2, 3, 4, RT_ELEMENTS(s_aValues), s_aValues }, 10570 { bs3CpuInstr3_vblendvpd_XMM1_XMM2_FSxBX_XMM4_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, 4, RT_ELEMENTS(s_aValues), s_aValues }, 10571 { bs3CpuInstr3_vblendvpd_YMM1_YMM2_YMM3_YMM4_icebp_c32, 255, RM_REG, T_AVX_256, 1, 2, 3, 4, RT_ELEMENTS(s_aValues), s_aValues }, 10572 { bs3CpuInstr3_vblendvpd_YMM1_YMM2_FSxBX_YMM4_icebp_c32, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 2, 255, 4, RT_ELEMENTS(s_aValues), s_aValues }, 10573 }; 10574 static BS3CPUINSTR3_TEST5_T const s_aTests64[] = 10575 { 10576 { bs3CpuInstr3_blendvpd_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SSE4_1, 1, 1, 2, 0, RT_ELEMENTS(s_aValues), s_aValues }, 10577 { bs3CpuInstr3_blendvpd_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 1, 1, 255, 0, RT_ELEMENTS(s_aValues), s_aValues }, 10578 { bs3CpuInstr3_blendvpd_XMM8_XMM9_icebp_c64, 255, RM_REG, T_SSE4_1, 8, 8, 9, 0, RT_ELEMENTS(s_aValues), s_aValues }, 10579 { bs3CpuInstr3_blendvpd_XMM8_FSxBX_icebp_c64, 255, RM_MEM, T_SSE4_1, 8, 8, 255, 0, RT_ELEMENTS(s_aValues), s_aValues }, 10580 10581 { bs3CpuInstr3_vblendvpd_XMM1_XMM2_XMM3_XMM4_icebp_c64, 255, RM_REG, T_AVX_128, 1, 2, 3, 4, RT_ELEMENTS(s_aValues), s_aValues }, 10582 { bs3CpuInstr3_vblendvpd_XMM1_XMM2_FSxBX_XMM4_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 1, 2, 255, 4, RT_ELEMENTS(s_aValues), s_aValues }, 10583 { bs3CpuInstr3_vblendvpd_XMM8_XMM9_XMM10_XMM11_icebp_c64, 255, RM_REG, T_AVX_128, 8, 9, 10, 11, RT_ELEMENTS(s_aValues), s_aValues }, 10584 { bs3CpuInstr3_vblendvpd_XMM8_XMM9_FSxBX_XMM11_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_128, 8, 9, 255, 11, RT_ELEMENTS(s_aValues), s_aValues }, 10585 10586 { bs3CpuInstr3_vblendvpd_YMM1_YMM2_YMM3_YMM4_icebp_c64, 255, RM_REG, T_AVX_256, 1, 2, 3, 4, RT_ELEMENTS(s_aValues), s_aValues }, 10587 { bs3CpuInstr3_vblendvpd_YMM1_YMM2_FSxBX_YMM4_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 1, 2, 255, 4, RT_ELEMENTS(s_aValues), s_aValues }, 10588 { bs3CpuInstr3_vblendvpd_YMM8_YMM9_YMM10_YMM11_icebp_c64, 255, RM_REG, T_AVX_256, 8, 9, 10, 11, RT_ELEMENTS(s_aValues), s_aValues }, 10589 { bs3CpuInstr3_vblendvpd_YMM8_YMM9_FSxBX_YMM11_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 8, 9, 255, 11, RT_ELEMENTS(s_aValues), s_aValues }, 10590 }; 10591 static BS3CPUINSTR3_TEST5_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST5_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); 10592 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); 10593 return bs3CpuInstr3_WorkerTestType5(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, 10594 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); 10053 10595 } 10054 10596 … … 10183 10725 { "[v]phminposuw", bs3CpuInstr3_v_phminposuw, 0 }, 10184 10726 #endif 10727 #if defined(ALL_TESTS) 10728 { "[v]pblendvb", bs3CpuInstr3_v_pblendvb, 0 }, 10729 { "[v]blendvps", bs3CpuInstr3_v_blendvps, 0 }, 10730 { "[v]blendvpd", bs3CpuInstr3_v_blendvpd, 0 }, 10731 #endif 10185 10732 }; 10186 10733 Bs3TestInit("bs3-cpu-instr-3");
Note:
See TracChangeset
for help on using the changeset viewer.
