Changeset 96702 in vbox for trunk/src/VBox/ValidationKit/bootsectors
- Timestamp:
- Sep 12, 2022 2:47:35 PM (3 years ago)
- svn:sync-xref-src-repo-rev:
- 153586
- Location:
- trunk/src/VBox/ValidationKit/bootsectors
- Files:
-
- 2 edited
-
bs3-cpu-instr-3-template.mac (modified) (1 diff)
-
bs3-cpu-instr-3.c32 (modified) (2 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3-template.mac
r96653 r96702 2860 2860 %endif 2861 2861 2862 ; 2863 ; [V]PINSRW 2864 ; 2865 EMIT_INSTR_PLUS_ICEBP pinsrw, MM1, EDX, 0FFh 2866 EMIT_INSTR_PLUS_ICEBP pinsrw, MM1, FSxBX, 0FFh 2867 EMIT_INSTR_PLUS_ICEBP pinsrw, MM1, EDX, 000h 2868 EMIT_INSTR_PLUS_ICEBP pinsrw, MM1, FSxBX, 000h 2869 2870 EMIT_INSTR_PLUS_ICEBP pinsrw, XMM1, EDX, 0FFh 2871 EMIT_INSTR_PLUS_ICEBP pinsrw, XMM1, FSxBX, 0FFh 2872 EMIT_INSTR_PLUS_ICEBP pinsrw, XMM1, EDX, 000h 2873 EMIT_INSTR_PLUS_ICEBP pinsrw, XMM1, FSxBX, 000h 2874 2875 EMIT_INSTR_PLUS_ICEBP vpinsrw, XMM1, XMM2, EDX, 0FFh 2876 EMIT_INSTR_PLUS_ICEBP vpinsrw, XMM1, XMM2, FSxBX, 0FFh 2877 EMIT_INSTR_PLUS_ICEBP vpinsrw, XMM1, XMM2, EDX, 000h 2878 EMIT_INSTR_PLUS_ICEBP vpinsrw, XMM1, XMM2, FSxBX, 000h 2879 2880 %if TMPL_BITS == 64 2881 EMIT_INSTR_PLUS_ICEBP pinsrw, MM1, R9D, 0FFh 2882 EMIT_INSTR_PLUS_ICEBP pinsrw, MM1, R9D, 000h 2883 2884 EMIT_INSTR_PLUS_ICEBP pinsrw, XMM8, R9D, 0FFh 2885 EMIT_INSTR_PLUS_ICEBP pinsrw, XMM8, FSxBX, 0FFh 2886 EMIT_INSTR_PLUS_ICEBP pinsrw, XMM8, R9D, 000h 2887 EMIT_INSTR_PLUS_ICEBP pinsrw, XMM8, FSxBX, 000h 2888 2889 EMIT_INSTR_PLUS_ICEBP vpinsrw, XMM8, XMM9, R9D, 0FFh 2890 EMIT_INSTR_PLUS_ICEBP vpinsrw, XMM8, XMM9, FSxBX, 0FFh 2891 EMIT_INSTR_PLUS_ICEBP vpinsrw, XMM8, XMM9, R9D, 000h 2892 EMIT_INSTR_PLUS_ICEBP vpinsrw, XMM8, XMM9, FSxBX, 000h 2893 %endif 2894 2862 2895 2863 2896 %endif ; BS3_INSTANTIATING_CMN -
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3.c32
r96653 r96702 11397 11397 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); 11398 11398 } 11399 11400 11401 /* 11402 * Test type #6 - MM/XMM/YMM <- GPR, no VVVV. 11403 * 11404 * Used probably only by the PINSRW testcases 11405 */ 11406 11407 typedef struct BS3CPUINSTR3_TEST6_VALUES_T 11408 { 11409 RTUINT256U uMediaSrc; 11410 uint64_t uGpr; 11411 RTUINT256U uMediaDst; 11412 } BS3CPUINSTR3_TEST6_VALUES_T; 11413 11414 typedef struct BS3CPUINSTR3_TEST6_T 11415 { 11416 FPFNBS3FAR pfnWorker; 11417 uint8_t bAvxMisalignXcpt; 11418 uint8_t enmRm; 11419 uint8_t enmType; 11420 uint8_t cbGpr; 11421 uint8_t cBitsGprValMask; 11422 uint8_t iGprReg; 11423 uint8_t iMediaRegSrc; 11424 uint8_t iMediaRegDst; 11425 uint8_t cValues; 11426 BS3CPUINSTR3_TEST6_VALUES_T const BS3_FAR *paValues; 11427 } BS3CPUINSTR3_TEST6_T; 11428 11429 typedef struct BS3CPUINSTR3_TEST6_MODE_T 11430 { 11431 BS3CPUINSTR3_TEST6_T const BS3_FAR *paTests; 11432 unsigned cTests; 11433 } BS3CPUINSTR3_TEST6_MODE_T; 11434 11435 /** Initializer for a BS3CPUINSTR3_TEST6_MODE_T array (three entries). */ 11436 #define BS3CPUINSTR3_TEST6_MODES_INIT(a_aTests16, a_aTests32, a_aTests64) \ 11437 { { a_aTests16, RT_ELEMENTS(a_aTests16) }, { a_aTests32, RT_ELEMENTS(a_aTests32) }, { a_aTests64, RT_ELEMENTS(a_aTests64) } } 11438 11439 11440 /** 11441 * Test type #6 worker. 11442 */ 11443 static uint8_t bs3CpuInstr3_WorkerTestType6(uint8_t bMode, BS3CPUINSTR3_TEST6_T const BS3_FAR *paTests, unsigned cTests, 11444 PCBS3CPUINSTR3_CONFIG_T paConfigs, unsigned cConfigs) 11445 { 11446 BS3REGCTX Ctx; 11447 BS3TRAPFRAME TrapFrame; 11448 const char BS3_FAR * const pszMode = Bs3GetModeName(bMode); 11449 uint8_t BS3_FAR *pbBuf = g_pbBuf; 11450 uint32_t cbBuf = g_cbBuf; 11451 uint8_t bRing = BS3_MODE_IS_V86(bMode) ? 3 : 0; 11452 PBS3EXTCTX pExtCtxOut; 11453 PBS3EXTCTX pExtCtx = bs3CpuInstr3AllocExtCtxs(&pExtCtxOut); 11454 if (!pExtCtx) 11455 return 0; 11456 11457 /* Ensure the structures are allocated before we sample the stack pointer. */ 11458 Bs3MemSet(&Ctx, 0, sizeof(Ctx)); 11459 Bs3MemSet(&TrapFrame, 0, sizeof(TrapFrame)); 11460 11461 /* 11462 * Create test context. 11463 */ 11464 pbBuf = bs3CpuInstr3BufSetup(pbBuf, &cbBuf, bMode); 11465 Bs3RegCtxSaveForMode(&Ctx, bMode, 1024); 11466 bs3CpuInstr3SetupSseAndAvx(&Ctx, pExtCtx); 11467 11468 /* 11469 * Run the tests in all rings since alignment issues may behave 11470 * differently in ring-3 compared to ring-0. 11471 */ 11472 for (;;) 11473 { 11474 unsigned iCfg; 11475 for (iCfg = 0; iCfg < cConfigs; iCfg++) 11476 { 11477 unsigned iTest; 11478 BS3CPUINSTR3_CONFIG_SAVED_T SavedCfg; 11479 if (!bs3CpuInstr3ConfigReconfigure(&SavedCfg, &Ctx, pExtCtx, &paConfigs[iCfg], bMode)) 11480 continue; /* unsupported config */ 11481 11482 /* 11483 * Iterate the tests. 11484 */ 11485 for (iTest = 0; iTest < cTests; iTest++) 11486 { 11487 BS3CPUINSTR3_TEST6_VALUES_T const BS3_FAR *paValues = paTests[iTest].paValues; 11488 uint8_t const cbInstr = ((uint8_t const BS3_FAR *)(uintptr_t)paTests[iTest].pfnWorker)[-1]; 11489 unsigned const cValues = paTests[iTest].cValues; 11490 bool const fMmxInstr = paTests[iTest].enmType < T_SSE; 11491 bool const fSseInstr = paTests[iTest].enmType >= T_SSE && paTests[iTest].enmType < T_AVX_128; 11492 bool const fAvxInstr = paTests[iTest].enmType >= T_AVX_128; 11493 uint8_t const cbOperand = paTests[iTest].enmType < T_128BITS ? 64/8 11494 : paTests[iTest].enmType < T_256BITS ? 128/8 : 256/8; 11495 uint8_t const cbMemOp = bs3CpuInstr3MemOpSize(cbOperand, paTests[iTest].enmRm); 11496 uint8_t const cbAlign = RT_MIN(cbOperand, 16); 11497 PRTUINT256U puMemOp = bs3CpuInstr3BufForOperand(pbBuf, cbBuf, cbMemOp, cbAlign, &paConfigs[iCfg]); 11498 uint8_t bXcptExpect = !g_afTypeSupports[paTests[iTest].enmType] ? X86_XCPT_UD 11499 : fMmxInstr ? paConfigs[iCfg].bXcptMmx 11500 : fSseInstr ? paConfigs[iCfg].bXcptSse 11501 : BS3_MODE_IS_RM_OR_V86(bMode) ? X86_XCPT_UD : paConfigs[iCfg].bXcptAvx; 11502 uint64_t const fGprValMask = paTests[iTest].cBitsGprValMask == 64 ? UINT64_MAX 11503 : RT_BIT_64(paTests[iTest].cBitsGprValMask) - 1; 11504 uint16_t idTestStep = bRing * 10000 + iCfg * 100 + iTest * 10; 11505 unsigned iVal; 11506 11507 /* If testing unaligned memory accesses, skip register-only tests. This allows 11508 setting bXcptMmx, bXcptSse and bXcptAvx to reflect the misaligned exceptions. */ 11509 if (paTests[iTest].enmRm == RM_REG && (!paConfigs[iCfg].fAligned || paConfigs[iCfg].fAlignCheck)) 11510 continue; 11511 11512 /* #AC is only raised in ring-3.: */ 11513 if (bXcptExpect == X86_XCPT_AC) 11514 { 11515 if (bRing != 3) 11516 bXcptExpect = X86_XCPT_DB; 11517 else if (fAvxInstr) 11518 bXcptExpect = paTests[iTest].bAvxMisalignXcpt; /* they generally don't raise #AC */ 11519 } 11520 11521 Bs3RegCtxSetRipCsFromCurPtr(&Ctx, paTests[iTest].pfnWorker); 11522 11523 /* 11524 * Iterate the test values and do the actual testing. 11525 */ 11526 for (iVal = 0; iVal < cValues; iVal++, idTestStep++) 11527 { 11528 uint16_t cErrors; 11529 uint16_t uSavedFtw = 0xff; 11530 RTUINT256U uMemOpExpect; 11531 11532 /* 11533 * Set up the context and some expectations. 11534 */ 11535 /* source - media */ 11536 BS3_ASSERT(paTests[iTest].iMediaRegSrc != UINT8_MAX); 11537 if (fMmxInstr) 11538 Bs3ExtCtxSetMm(pExtCtx, paTests[iTest].iMediaRegSrc, paValues[iVal].uMediaSrc.QWords.qw0, BS3EXTCTXTOPMM_ZERO); 11539 else if (fSseInstr) 11540 Bs3ExtCtxSetXmm(pExtCtx, paTests[iTest].iMediaRegSrc, &paValues[iVal].uMediaSrc.DQWords.dqw0); 11541 else 11542 Bs3ExtCtxSetYmm(pExtCtx, paTests[iTest].iMediaRegSrc, &paValues[iVal].uMediaSrc, 32); 11543 11544 /* source - gpr/mem */ 11545 if (paTests[iTest].iGprReg == UINT8_MAX) 11546 { 11547 BS3_ASSERT(paTests[iTest].enmRm >= RM_MEM); 11548 Bs3MemSet(&uMemOpExpect, 0xcc, sizeof(uMemOpExpect)); 11549 if (bXcptExpect == X86_XCPT_DB) 11550 switch (paTests[iTest].cbGpr) 11551 { 11552 case 1: uMemOpExpect.au8[0] = (uint8_t) (paValues[iVal].uGpr & fGprValMask); break; 11553 case 2: uMemOpExpect.au16[0] = (uint16_t)(paValues[iVal].uGpr & fGprValMask); break; 11554 case 4: uMemOpExpect.au32[0] = (uint32_t)(paValues[iVal].uGpr & fGprValMask); break; 11555 case 8: uMemOpExpect.au64[0] = (paValues[iVal].uGpr & fGprValMask); break; 11556 default: BS3_ASSERT(0); 11557 } 11558 Bs3MemCpy(puMemOp, &uMemOpExpect, cbMemOp); 11559 } 11560 else 11561 Bs3RegCtxSetGpr(&Ctx, paTests[iTest].iGprReg, paValues[iVal].uGpr & fGprValMask, paTests[iTest].cbGpr); 11562 11563 /* Memory pointer. */ 11564 if (paTests[iTest].enmRm >= RM_MEM) 11565 { 11566 BS3_ASSERT(paTests[iTest].iGprReg == UINT8_MAX || paTests[iTest].iMediaRegSrc == UINT8_MAX); 11567 Bs3RegCtxSetGrpSegFromCurPtr(&Ctx, &Ctx.rbx, &Ctx.fs, puMemOp); 11568 } 11569 11570 /* 11571 * Execute. 11572 */ 11573 Bs3TrapSetJmpAndRestoreWithExtCtxAndRm(&Ctx, pExtCtx, &TrapFrame, pExtCtxOut); 11574 11575 /* 11576 * Check the result: 11577 */ 11578 cErrors = Bs3TestSubErrorCount(); 11579 11580 if (fMmxInstr && bXcptExpect == X86_XCPT_DB) 11581 { 11582 uSavedFtw = Bs3ExtCtxGetAbridgedFtw(pExtCtx); 11583 Bs3ExtCtxSetAbridgedFtw(pExtCtx, 0xff); 11584 } 11585 11586 if (bXcptExpect == X86_XCPT_DB) 11587 { 11588 if (fMmxInstr) 11589 Bs3ExtCtxSetMm(pExtCtx, paTests[iTest].iMediaRegDst, paValues[iVal].uMediaDst.QWords.qw0, BS3EXTCTXTOPMM_SET); 11590 else if (fSseInstr) 11591 Bs3ExtCtxSetXmm(pExtCtx, paTests[iTest].iMediaRegDst, &paValues[iVal].uMediaDst.DQWords.dqw0); 11592 else 11593 Bs3ExtCtxSetYmm(pExtCtx, paTests[iTest].iMediaRegDst, &paValues[iVal].uMediaDst, 32); 11594 } 11595 11596 Bs3TestCheckExtCtx(pExtCtxOut, pExtCtx, 0 /*fFlags*/, pszMode, idTestStep); 11597 11598 if (TrapFrame.bXcpt != bXcptExpect) 11599 Bs3TestFailedF("Expected bXcpt = %#x, got %#x", bXcptExpect, TrapFrame.bXcpt); 11600 11601 /* Kludge! Looks like EFLAGS.AC is cleared when raising #GP in real mode on the 10980XE. WEIRD! */ 11602 if (bMode == BS3_MODE_RM && (Ctx.rflags.u32 & X86_EFL_AC)) 11603 { 11604 if (TrapFrame.Ctx.rflags.u32 & X86_EFL_AC) 11605 Bs3TestFailedF("Expected EFLAGS.AC to be cleared (bXcpt=%d)", TrapFrame.bXcpt); 11606 TrapFrame.Ctx.rflags.u32 |= X86_EFL_AC; 11607 } 11608 Bs3TestCheckRegCtxEx(&TrapFrame.Ctx, &Ctx, bXcptExpect == X86_XCPT_DB ? cbInstr + 1 : 0, 0, 11609 bXcptExpect == X86_XCPT_DB || BS3_MODE_IS_16BIT_SYS(bMode) ? 0 : X86_EFL_RF, 11610 pszMode, idTestStep); 11611 11612 if ( paTests[iTest].enmRm >= RM_MEM 11613 && Bs3MemCmp(puMemOp, &uMemOpExpect, cbMemOp) != 0) 11614 Bs3TestFailedF("Expected uMemOp %.*Rhxs, got %.*Rhxs", cbMemOp, &uMemOpExpect, cbMemOp, puMemOp); 11615 11616 if (cErrors != Bs3TestSubErrorCount()) 11617 { 11618 if (paConfigs[iCfg].fAligned) 11619 Bs3TestFailedF("ring-%d/cfg#%u/test#%u/value#%u failed (bXcptExpect=%#x)", 11620 bRing, iCfg, iTest, iVal, bXcptExpect); 11621 else 11622 Bs3TestFailedF("ring-%d/cfg#%u/test#%u/value#%u failed (bXcptExpect=%#x, puMemOp=%p, EFLAGS=%#RX32, CR0=%#RX32)", 11623 bRing, iCfg, iTest, iVal, bXcptExpect, puMemOp, TrapFrame.Ctx.rflags.u32, TrapFrame.Ctx.cr0); 11624 Bs3TestPrintf("\n"); 11625 } 11626 11627 if (uSavedFtw != 0xff) 11628 Bs3ExtCtxSetAbridgedFtw(pExtCtx, uSavedFtw); 11629 } 11630 } 11631 11632 bs3CpuInstr3ConfigRestore(&SavedCfg, &Ctx, pExtCtx); 11633 } 11634 11635 /* 11636 * Next ring. 11637 */ 11638 bRing++; 11639 if (bRing > 3 || bMode == BS3_MODE_RM) 11640 break; 11641 Bs3RegCtxConvertToRingX(&Ctx, bRing); 11642 } 11643 11644 /* 11645 * Cleanup. 11646 */ 11647 bs3CpuInstr3BufCleanup(pbBuf, cbBuf, bMode); 11648 bs3CpuInstr3FreeExtCtxs(pExtCtx, pExtCtxOut); 11649 return 0; 11650 } 11651 11652 11653 /* 11654 * [V]PINSRW. 11655 */ 11656 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pinsrw_MM1_EDX_000h_icebp); 11657 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pinsrw_MM1_FSxBX_000h_icebp); 11658 extern FNBS3FAR bs3CpuInstr3_pinsrw_MM1_R9D_000h_icebp_c64; 11659 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pinsrw_MM1_EDX_0FFh_icebp); 11660 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pinsrw_MM1_FSxBX_0FFh_icebp); 11661 extern FNBS3FAR bs3CpuInstr3_pinsrw_MM1_R9D_0FFh_icebp_c64; 11662 11663 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pinsrw_XMM1_EDX_000h_icebp); 11664 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pinsrw_XMM1_FSxBX_000h_icebp); 11665 extern FNBS3FAR bs3CpuInstr3_pinsrw_XMM8_R9D_000h_icebp_c64; 11666 extern FNBS3FAR bs3CpuInstr3_pinsrw_XMM8_FSxBX_000h_icebp_c64; 11667 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pinsrw_XMM1_EDX_0FFh_icebp); 11668 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pinsrw_XMM1_FSxBX_0FFh_icebp); 11669 extern FNBS3FAR bs3CpuInstr3_pinsrw_XMM8_R9D_0FFh_icebp_c64; 11670 extern FNBS3FAR bs3CpuInstr3_pinsrw_XMM8_FSxBX_0FFh_icebp_c64; 11671 11672 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpinsrw_XMM1_XMM2_EDX_000h_icebp); 11673 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpinsrw_XMM1_XMM2_FSxBX_000h_icebp); 11674 extern FNBS3FAR bs3CpuInstr3_vpinsrw_XMM8_XMM9_R9D_000h_icebp_c64; 11675 extern FNBS3FAR bs3CpuInstr3_vpinsrw_XMM8_XMM9_FSxBX_000h_icebp_c64; 11676 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpinsrw_XMM1_XMM2_EDX_0FFh_icebp); 11677 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpinsrw_XMM1_XMM2_FSxBX_0FFh_icebp); 11678 extern FNBS3FAR bs3CpuInstr3_vpinsrw_XMM8_XMM9_R9D_0FFh_icebp_c64; 11679 extern FNBS3FAR bs3CpuInstr3_vpinsrw_XMM8_XMM9_FSxBX_0FFh_icebp_c64; 11680 11681 BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_pinsrw(uint8_t bMode) 11682 { 11683 static BS3CPUINSTR3_TEST6_VALUES_T const s_aValues00[] = 11684 { 11685 /* Media source GPR word Media dest. */ 11686 { RTUINT256_INIT_C(0, 0, 0, 0), UINT64_C(0x1234), RTUINT256_INIT_C(0, 0, 0, 0x0000000000001234) }, 11687 }; 11688 static BS3CPUINSTR3_TEST6_VALUES_T const s_aValuesFF_64[] = 11689 { 11690 /* Media source GPR word Media dest. */ 11691 { RTUINT256_INIT_C(0, 0, 0, 0), UINT64_C(0x1234), RTUINT256_INIT_C(0, 0, 0, 0x1234000000000000) }, 11692 }; 11693 static BS3CPUINSTR3_TEST6_VALUES_T const s_aValuesFF[] = 11694 { 11695 /* Media source GPR word Media dest. */ 11696 { RTUINT256_INIT_C(0, 0, 0, 0), UINT64_C(0x1234), RTUINT256_INIT_C(0, 0, 0x1234000000000000, 0) }, 11697 }; 11698 11699 static BS3CPUINSTR3_TEST6_T const s_aTests16[] = 11700 { 11701 { bs3CpuInstr3_pinsrw_MM1_EDX_000h_icebp_c16, 255, RM_REG, T_MMX_SSE, 4, 32, 2, 1, 1, RT_ELEMENTS(s_aValues00), s_aValues00 }, 11702 { bs3CpuInstr3_pinsrw_MM1_FSxBX_000h_icebp_c16, 255, RM_MEM32, T_MMX_SSE, 4, 32, 255, 1, 1, RT_ELEMENTS(s_aValues00), s_aValues00 }, 11703 { bs3CpuInstr3_pinsrw_MM1_EDX_0FFh_icebp_c16, 255, RM_REG, T_MMX_SSE, 4, 32, 2, 1, 1, RT_ELEMENTS(s_aValuesFF_64), s_aValuesFF_64 }, 11704 { bs3CpuInstr3_pinsrw_MM1_FSxBX_0FFh_icebp_c16, 255, RM_MEM32, T_MMX_SSE, 4, 32, 255, 1, 1, RT_ELEMENTS(s_aValuesFF_64), s_aValuesFF_64 }, 11705 11706 { bs3CpuInstr3_pinsrw_XMM1_EDX_000h_icebp_c16, 255, RM_REG, T_SSE, 4, 32, 2, 1, 1, RT_ELEMENTS(s_aValues00), s_aValues00 }, 11707 { bs3CpuInstr3_pinsrw_XMM1_FSxBX_000h_icebp_c16, 255, RM_MEM32, T_SSE, 4, 32, 255, 1, 1, RT_ELEMENTS(s_aValues00), s_aValues00 }, 11708 { bs3CpuInstr3_pinsrw_XMM1_EDX_0FFh_icebp_c16, 255, RM_REG, T_SSE, 4, 32, 2, 1, 1, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 11709 { bs3CpuInstr3_pinsrw_XMM1_FSxBX_0FFh_icebp_c16, 255, RM_MEM32, T_SSE, 4, 32, 255, 1, 1, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 11710 11711 { bs3CpuInstr3_vpinsrw_XMM1_XMM2_EDX_000h_icebp_c16, 255, RM_REG, T_AVX_128, 4, 32, 2, 2, 1, RT_ELEMENTS(s_aValues00), s_aValues00 }, 11712 { bs3CpuInstr3_vpinsrw_XMM1_XMM2_FSxBX_000h_icebp_c16, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, 255, 2, 1, RT_ELEMENTS(s_aValues00), s_aValues00 }, 11713 { bs3CpuInstr3_vpinsrw_XMM1_XMM2_EDX_0FFh_icebp_c16, 255, RM_REG, T_AVX_128, 4, 32, 2, 2, 1, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 11714 { bs3CpuInstr3_vpinsrw_XMM1_XMM2_FSxBX_0FFh_icebp_c16, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, 255, 2, 1, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 11715 }; 11716 static BS3CPUINSTR3_TEST6_T const s_aTests32[] = 11717 { 11718 { bs3CpuInstr3_pinsrw_MM1_EDX_000h_icebp_c32, 255, RM_REG, T_MMX_SSE, 4, 32, 2, 1, 1, RT_ELEMENTS(s_aValues00), s_aValues00 }, 11719 { bs3CpuInstr3_pinsrw_MM1_FSxBX_000h_icebp_c32, 255, RM_MEM32, T_MMX_SSE, 4, 32, 255, 1, 1, RT_ELEMENTS(s_aValues00), s_aValues00 }, 11720 { bs3CpuInstr3_pinsrw_MM1_EDX_0FFh_icebp_c32, 255, RM_REG, T_MMX_SSE, 4, 32, 2, 1, 1, RT_ELEMENTS(s_aValuesFF_64), s_aValuesFF_64 }, 11721 { bs3CpuInstr3_pinsrw_MM1_FSxBX_0FFh_icebp_c32, 255, RM_MEM32, T_MMX_SSE, 4, 32, 255, 1, 1, RT_ELEMENTS(s_aValuesFF_64), s_aValuesFF_64 }, 11722 11723 { bs3CpuInstr3_pinsrw_XMM1_EDX_000h_icebp_c32, 255, RM_REG, T_SSE, 4, 32, 2, 1, 1, RT_ELEMENTS(s_aValues00), s_aValues00 }, 11724 { bs3CpuInstr3_pinsrw_XMM1_FSxBX_000h_icebp_c32, 255, RM_MEM32, T_SSE, 4, 32, 255, 1, 1, RT_ELEMENTS(s_aValues00), s_aValues00 }, 11725 { bs3CpuInstr3_pinsrw_XMM1_EDX_0FFh_icebp_c32, 255, RM_REG, T_SSE, 4, 32, 2, 1, 1, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 11726 { bs3CpuInstr3_pinsrw_XMM1_FSxBX_0FFh_icebp_c32, 255, RM_MEM32, T_SSE, 4, 32, 255, 1, 1, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 11727 11728 { bs3CpuInstr3_vpinsrw_XMM1_XMM2_EDX_000h_icebp_c32, 255, RM_REG, T_AVX_128, 4, 32, 2, 2, 1, RT_ELEMENTS(s_aValues00), s_aValues00 }, 11729 { bs3CpuInstr3_vpinsrw_XMM1_XMM2_FSxBX_000h_icebp_c32, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, 255, 2, 1, RT_ELEMENTS(s_aValues00), s_aValues00 }, 11730 { bs3CpuInstr3_vpinsrw_XMM1_XMM2_EDX_0FFh_icebp_c32, 255, RM_REG, T_AVX_128, 4, 32, 2, 2, 1, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 11731 { bs3CpuInstr3_vpinsrw_XMM1_XMM2_FSxBX_0FFh_icebp_c32, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, 255, 2, 1, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 11732 }; 11733 static BS3CPUINSTR3_TEST6_T const s_aTests64[] = 11734 { 11735 { bs3CpuInstr3_pinsrw_MM1_EDX_000h_icebp_c64, 255, RM_REG, T_MMX_SSE, 4, 32, 2, 1, 1, RT_ELEMENTS(s_aValues00), s_aValues00 }, 11736 { bs3CpuInstr3_pinsrw_MM1_R9D_000h_icebp_c64, 255, RM_REG, T_MMX_SSE, 4, 32, 9, 1, 1, RT_ELEMENTS(s_aValues00), s_aValues00 }, 11737 { bs3CpuInstr3_pinsrw_MM1_FSxBX_000h_icebp_c64, 255, RM_MEM32, T_MMX_SSE, 4, 32, 255, 1, 1, RT_ELEMENTS(s_aValues00), s_aValues00 }, 11738 { bs3CpuInstr3_pinsrw_MM1_EDX_0FFh_icebp_c64, 255, RM_REG, T_MMX_SSE, 4, 32, 2, 1, 1, RT_ELEMENTS(s_aValuesFF_64), s_aValuesFF_64 }, 11739 { bs3CpuInstr3_pinsrw_MM1_R9D_0FFh_icebp_c64, 255, RM_REG, T_MMX_SSE, 4, 32, 9, 1, 1, RT_ELEMENTS(s_aValuesFF_64), s_aValuesFF_64 }, 11740 { bs3CpuInstr3_pinsrw_MM1_FSxBX_0FFh_icebp_c64, 255, RM_MEM32, T_MMX_SSE, 4, 32, 255, 1, 1, RT_ELEMENTS(s_aValuesFF_64), s_aValuesFF_64 }, 11741 11742 { bs3CpuInstr3_pinsrw_XMM1_EDX_000h_icebp_c64, 255, RM_REG, T_SSE, 4, 32, 2, 1, 1, RT_ELEMENTS(s_aValues00), s_aValues00 }, 11743 { bs3CpuInstr3_pinsrw_XMM1_FSxBX_000h_icebp_c64, 255, RM_MEM32, T_SSE, 4, 32, 255, 1, 1, RT_ELEMENTS(s_aValues00), s_aValues00 }, 11744 { bs3CpuInstr3_pinsrw_XMM1_EDX_0FFh_icebp_c64, 255, RM_REG, T_SSE, 4, 32, 2, 1, 1, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 11745 { bs3CpuInstr3_pinsrw_XMM1_FSxBX_0FFh_icebp_c64, 255, RM_MEM32, T_SSE, 4, 32, 255, 1, 1, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 11746 11747 { bs3CpuInstr3_pinsrw_XMM8_R9D_000h_icebp_c64, 255, RM_REG, T_SSE, 4, 32, 9, 8, 8, RT_ELEMENTS(s_aValues00), s_aValues00 }, 11748 { bs3CpuInstr3_pinsrw_XMM8_FSxBX_000h_icebp_c64, 255, RM_MEM32, T_SSE, 4, 32, 255, 8, 8, RT_ELEMENTS(s_aValues00), s_aValues00 }, 11749 { bs3CpuInstr3_pinsrw_XMM8_R9D_0FFh_icebp_c64, 255, RM_REG, T_SSE, 4, 32, 9, 8, 8, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 11750 { bs3CpuInstr3_pinsrw_XMM8_FSxBX_0FFh_icebp_c64, 255, RM_MEM32, T_SSE, 4, 32, 255, 8, 8, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 11751 11752 { bs3CpuInstr3_vpinsrw_XMM1_XMM2_EDX_000h_icebp_c64, 255, RM_REG, T_AVX_128, 4, 32, 2, 2, 1, RT_ELEMENTS(s_aValues00), s_aValues00 }, 11753 { bs3CpuInstr3_vpinsrw_XMM1_XMM2_FSxBX_000h_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, 255, 2, 1, RT_ELEMENTS(s_aValues00), s_aValues00 }, 11754 { bs3CpuInstr3_vpinsrw_XMM1_XMM2_EDX_0FFh_icebp_c64, 255, RM_REG, T_AVX_128, 4, 32, 2, 2, 1, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 11755 { bs3CpuInstr3_vpinsrw_XMM1_XMM2_FSxBX_0FFh_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, 255, 2, 1, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 11756 11757 { bs3CpuInstr3_vpinsrw_XMM8_XMM9_R9D_000h_icebp_c64, 255, RM_REG, T_AVX_128, 4, 32, 9, 9, 8, RT_ELEMENTS(s_aValues00), s_aValues00 }, 11758 { bs3CpuInstr3_vpinsrw_XMM8_XMM9_FSxBX_000h_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, 255, 9, 8, RT_ELEMENTS(s_aValues00), s_aValues00 }, 11759 { bs3CpuInstr3_vpinsrw_XMM8_XMM9_R9D_0FFh_icebp_c64, 255, RM_REG, T_AVX_128, 4, 32, 9, 9, 8, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 11760 { bs3CpuInstr3_vpinsrw_XMM8_XMM9_FSxBX_0FFh_icebp_c64, X86_XCPT_AC, RM_MEM32, T_AVX_128, 4, 32, 255, 9, 8, RT_ELEMENTS(s_aValuesFF), s_aValuesFF }, 11761 }; 11762 static BS3CPUINSTR3_TEST6_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST6_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); 11763 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); 11764 return bs3CpuInstr3_WorkerTestType6(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, 11765 g_aXcptConfig5, RT_ELEMENTS(g_aXcptConfig5)); 11766 } 11767 11768 11399 11769 11400 11770 … … 11543 11913 #if defined(ALL_TESTS) 11544 11914 { "[v]pclmulqdq", bs3CpuInstr3_v_pclmulqdq, 0 }, 11915 { "[v]pinsrw", bs3CpuInstr3_v_pinsrw, 0 }, 11545 11916 #endif 11546 11917 };
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