VirtualBox

Changeset 96708 in vbox for trunk


Ignore:
Timestamp:
Sep 12, 2022 4:57:27 PM (2 years ago)
Author:
vboxsync
Message:

ValidationKit/bs3-cpu-instr-3: Add simple [v]pextrw instructions testcases, ​​bugref:9898

Location:
trunk/src/VBox/ValidationKit/bootsectors
Files:
2 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3-template.mac

    r96702 r96708  
    28932893 %endif
    28942894
     2895;
     2896; [V]PEXTRW
     2897;
     2898EMIT_INSTR_PLUS_ICEBP   pextrw,  EDX, MM1, 0FFh
     2899EMIT_INSTR_PLUS_ICEBP   pextrw,  EDX, MM1, 000h
     2900
     2901EMIT_INSTR_PLUS_ICEBP   pextrw,  EDX, XMM1, 0FFh
     2902EMIT_INSTR_PLUS_ICEBP   pextrw,  EDX, XMM1, 000h
     2903
     2904EMIT_INSTR_PLUS_ICEBP   vpextrw, EDX, XMM1, 0FFh
     2905EMIT_INSTR_PLUS_ICEBP   vpextrw, EDX, XMM1, 000h
     2906
     2907 %if TMPL_BITS == 64
     2908EMIT_INSTR_PLUS_ICEBP   pextrw,  R9D, MM1, 0FFh
     2909EMIT_INSTR_PLUS_ICEBP   pextrw,  R9D, MM1, 000h
     2910
     2911; @todo Emits the SSE4.1 0f3a variant EMIT_INSTR_PLUS_ICEBP   pextrw,  RDX, XMM1, 0FFh
     2912; @todo Emits the SSE4.1 0f3a variant EMIT_INSTR_PLUS_ICEBP   pextrw,  RDX, XMM1, 000h
     2913
     2914EMIT_INSTR_PLUS_ICEBP   pextrw,  R9D, XMM8, 0FFh
     2915EMIT_INSTR_PLUS_ICEBP   pextrw,  R9D, XMM8, 000h
     2916
     2917EMIT_INSTR_PLUS_ICEBP   vpextrw, R9D, XMM8, 0FFh
     2918EMIT_INSTR_PLUS_ICEBP   vpextrw, R9D, XMM8, 000h
     2919
     2920EMIT_INSTR_PLUS_ICEBP   vpextrw, RDX, XMM1, 0FFh
     2921EMIT_INSTR_PLUS_ICEBP   vpextrw, RDX, XMM1, 000h
     2922 %endif
     2923
    28952924
    28962925%endif ; BS3_INSTANTIATING_CMN

  • trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3.c32

    r96702 r96708  
    80768076
    80778077
     8078/*
     8079 * [V]PEXTRW.
     8080 */
     8081BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pextrw_EDX_MM1_000h_icebp);
     8082BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pextrw_EDX_XMM1_000h_icebp);
     8083extern FNBS3FAR             bs3CpuInstr3_pextrw_RDX_XMM1_000h_icebp_c64;
     8084extern FNBS3FAR             bs3CpuInstr3_pextrw_R9D_MM1_000h_icebp_c64;
     8085extern FNBS3FAR             bs3CpuInstr3_pextrw_R9D_XMM8_000h_icebp_c64;
     8086
     8087BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pextrw_EDX_MM1_0FFh_icebp);
     8088BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_pextrw_EDX_XMM1_0FFh_icebp);
     8089extern FNBS3FAR             bs3CpuInstr3_pextrw_RDX_XMM1_0FFh_icebp_c64;
     8090extern FNBS3FAR             bs3CpuInstr3_pextrw_R9D_MM1_0FFh_icebp_c64;
     8091extern FNBS3FAR             bs3CpuInstr3_pextrw_R9D_XMM8_0FFh_icebp_c64;
     8092
     8093BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpextrw_EDX_XMM1_000h_icebp);
     8094extern FNBS3FAR             bs3CpuInstr3_vpextrw_RDX_XMM1_000h_icebp_c64;
     8095extern FNBS3FAR             bs3CpuInstr3_vpextrw_EDX_XMM8_000h_icebp_c64;
     8096extern FNBS3FAR             bs3CpuInstr3_vpextrw_R9D_XMM8_000h_icebp_c64;
     8097
     8098BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vpextrw_EDX_XMM1_0FFh_icebp);
     8099extern FNBS3FAR             bs3CpuInstr3_vpextrw_RDX_XMM1_0FFh_icebp_c64;
     8100extern FNBS3FAR             bs3CpuInstr3_vpextrw_EDX_XMM8_0FFh_icebp_c64;
     8101extern FNBS3FAR             bs3CpuInstr3_vpextrw_R9D_XMM8_0FFh_icebp_c64;
     8102
     8103BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_pextrw(uint8_t bMode)
     8104{
     8105    static BS3CPUINSTR3_TEST2_VALUES_T const s_aValues00[] =
     8106    {
     8107        { RTUINT256_INIT_C(0,  0, 0, 0x1234),                       /*->*/ UINT64_C(0x1234) },
     8108        { RTUINT256_INIT_C(1,  2, 0xffffffffffffffff, 0xffffffffffffffff), UINT64_C(0xffff) },
     8109        { RTUINT256_INIT_C(3,  4, 0x7f7f7f7f7f7f7f7f, 0x7f7f7f7f7f7f7f7f), UINT64_C(0x7f7f) },
     8110        { RTUINT256_INIT_C(5,  6, 0x8080808080808080, 0x8080808080808080), UINT64_C(0x8080) },
     8111        { RTUINT256_INIT_C(7,  8, 0x1111222233334444, 0x5555666677778888), UINT64_C(0x8888) },
     8112        { RTUINT256_INIT_C(9, 10, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), UINT64_C(0x96bb) },
     8113    };
     8114
     8115    static BS3CPUINSTR3_TEST2_VALUES_T const s_aValuesFF[] =
     8116    {
     8117        { RTUINT256_INIT_C(0,  0, 0x1234000000000000,                  0), UINT64_C(0x1234) },
     8118        { RTUINT256_INIT_C(1,  2, 0xffffffffffffffff, 0xffffffffffffffff), UINT64_C(0xffff) },
     8119        { RTUINT256_INIT_C(3,  4, 0x7f7f7f7f7f7f7f7f, 0x7f7f7f7f7f7f7f7f), UINT64_C(0x7f7f) },
     8120        { RTUINT256_INIT_C(5,  6, 0x8080808080808080, 0x8080808080808080), UINT64_C(0x8080) },
     8121        { RTUINT256_INIT_C(7,  8, 0x1111222233334444, 0x5555666677778888), UINT64_C(0x1111) },
     8122        { RTUINT256_INIT_C(9, 10, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), UINT64_C(0xb421) },
     8123    };
     8124
     8125    static BS3CPUINSTR3_TEST2_VALUES_T const s_aValuesFF_64[] =
     8126    {
     8127        { RTUINT256_INIT_C(0,  0,                  0, 0x1234000000000000), UINT64_C(0x1234) },
     8128        { RTUINT256_INIT_C(1,  2, 0xffffffffffffffff, 0xffffffffffffffff), UINT64_C(0xffff) },
     8129        { RTUINT256_INIT_C(3,  4, 0x7f7f7f7f7f7f7f7f, 0x7f7f7f7f7f7f7f7f), UINT64_C(0x7f7f) },
     8130        { RTUINT256_INIT_C(5,  6, 0x8080808080808080, 0x8080808080808080), UINT64_C(0x8080) },
     8131        { RTUINT256_INIT_C(7,  8, 0x1111222233334444, 0x5555666677778888), UINT64_C(0x5555) },
     8132        { RTUINT256_INIT_C(9, 10, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), UINT64_C(0x9c5c) },
     8133    };
     8134
     8135    static BS3CPUINSTR3_TEST2_T const s_aTests16[] =
     8136    {
     8137        {  bs3CpuInstr3_pextrw_EDX_MM1_000h_icebp_c16,           255, RM_REG, T_MMX_SSE,      4, 32, false, true, 2,   1, RT_ELEMENTS(s_aValues00),    s_aValues00 },
     8138        {  bs3CpuInstr3_pextrw_EDX_XMM1_000h_icebp_c16,          255, RM_REG, T_SSE2,         4, 32, false, true, 2,   1, RT_ELEMENTS(s_aValues00),    s_aValues00 },
     8139        {  bs3CpuInstr3_vpextrw_EDX_XMM1_000h_icebp_c16,         255, RM_REG, T_AVX_128,      4, 32, false, true, 2,   1, RT_ELEMENTS(s_aValues00),    s_aValues00 },
     8140
     8141        {  bs3CpuInstr3_pextrw_EDX_MM1_0FFh_icebp_c16,           255, RM_REG, T_MMX_SSE,      4, 32, false, true, 2,   1, RT_ELEMENTS(s_aValuesFF_64), s_aValuesFF_64 },
     8142        {  bs3CpuInstr3_pextrw_EDX_XMM1_0FFh_icebp_c16,          255, RM_REG, T_SSE2,         4, 32, false, true, 2,   1, RT_ELEMENTS(s_aValuesFF),    s_aValuesFF },
     8143        {  bs3CpuInstr3_vpextrw_EDX_XMM1_0FFh_icebp_c16,         255, RM_REG, T_AVX_128,      4, 32, false, true, 2,   1, RT_ELEMENTS(s_aValuesFF),    s_aValuesFF },
     8144    };
     8145    static BS3CPUINSTR3_TEST2_T const s_aTests32[] =
     8146    {
     8147        {  bs3CpuInstr3_pextrw_EDX_MM1_000h_icebp_c32,           255, RM_REG, T_MMX_SSE,      4, 32, false, true, 2,   1, RT_ELEMENTS(s_aValues00),    s_aValues00 },
     8148        {  bs3CpuInstr3_pextrw_EDX_XMM1_000h_icebp_c32,          255, RM_REG, T_SSE2,         4, 32, false, true, 2,   1, RT_ELEMENTS(s_aValues00),    s_aValues00 },
     8149        {  bs3CpuInstr3_vpextrw_EDX_XMM1_000h_icebp_c32,         255, RM_REG, T_AVX_128,      4, 32, false, true, 2,   1, RT_ELEMENTS(s_aValues00),    s_aValues00 },
     8150
     8151        {  bs3CpuInstr3_pextrw_EDX_MM1_0FFh_icebp_c32,           255, RM_REG, T_MMX_SSE,      4, 32, false, true, 2,   1, RT_ELEMENTS(s_aValuesFF_64), s_aValuesFF_64 },
     8152        {  bs3CpuInstr3_pextrw_EDX_XMM1_0FFh_icebp_c32,          255, RM_REG, T_SSE2,         4, 32, false, true, 2,   1, RT_ELEMENTS(s_aValuesFF),    s_aValuesFF },
     8153        {  bs3CpuInstr3_vpextrw_EDX_XMM1_0FFh_icebp_c32,         255, RM_REG, T_AVX_128,      4, 32, false, true, 2,   1, RT_ELEMENTS(s_aValuesFF),    s_aValuesFF },
     8154    };
     8155    static BS3CPUINSTR3_TEST2_T const s_aTests64[] =
     8156    {
     8157        {  bs3CpuInstr3_pextrw_EDX_MM1_000h_icebp_c64,           255, RM_REG, T_MMX_SSE,      4, 32, false, true, 2,   1, RT_ELEMENTS(s_aValues00),    s_aValues00 },
     8158        {  bs3CpuInstr3_pextrw_R9D_MM1_000h_icebp_c64,           255, RM_REG, T_MMX_SSE,      4, 32, false, true, 9,   1, RT_ELEMENTS(s_aValues00),    s_aValues00 },
     8159        {  bs3CpuInstr3_pextrw_EDX_XMM1_000h_icebp_c64,          255, RM_REG, T_SSE2,         4, 32, false, true, 2,   1, RT_ELEMENTS(s_aValues00),    s_aValues00 },
     8160        // @todo Emits the SSE4.1 0f3a variant {  bs3CpuInstr3_pextrw_RDX_XMM1_000h_icebp_c64,          255, RM_REG, T_SSE2,         8, 64, false, true, 2,   1, RT_ELEMENTS(s_aValues00),    s_aValues00 },
     8161        {  bs3CpuInstr3_pextrw_R9D_XMM8_000h_icebp_c64,          255, RM_REG, T_SSE2,         4, 32, false, true, 9,   8, RT_ELEMENTS(s_aValues00),    s_aValues00 },
     8162        {  bs3CpuInstr3_vpextrw_EDX_XMM1_000h_icebp_c64,         255, RM_REG, T_AVX_128,      4, 32, false, true, 2,   1, RT_ELEMENTS(s_aValues00),    s_aValues00 },
     8163        {  bs3CpuInstr3_vpextrw_RDX_XMM1_000h_icebp_c64,         255, RM_REG, T_AVX_128,      8, 64, false, true, 2,   1, RT_ELEMENTS(s_aValues00),    s_aValues00 },
     8164        {  bs3CpuInstr3_vpextrw_R9D_XMM8_000h_icebp_c64,         255, RM_REG, T_AVX_128,      4, 32, false, true, 9,   8, RT_ELEMENTS(s_aValues00),    s_aValues00 },
     8165
     8166        {  bs3CpuInstr3_pextrw_EDX_MM1_0FFh_icebp_c64,           255, RM_REG, T_MMX_SSE,      4, 32, false, true, 2,   1, RT_ELEMENTS(s_aValuesFF_64), s_aValuesFF_64 },
     8167        {  bs3CpuInstr3_pextrw_R9D_MM1_0FFh_icebp_c64,           255, RM_REG, T_MMX_SSE,      4, 32, false, true, 9,   1, RT_ELEMENTS(s_aValuesFF_64), s_aValuesFF_64 },
     8168        {  bs3CpuInstr3_pextrw_EDX_XMM1_0FFh_icebp_c64,          255, RM_REG, T_SSE2,         4, 32, false, true, 2,   1, RT_ELEMENTS(s_aValuesFF),    s_aValuesFF },
     8169        // @todo Emits the SSE4.1 0f3a variant {  bs3CpuInstr3_pextrw_RDX_XMM1_0FFh_icebp_c64,          255, RM_REG, T_SSE2,         8, 64, false, true, 2,   1, RT_ELEMENTS(s_aValuesFF),    s_aValuesFF },
     8170        {  bs3CpuInstr3_pextrw_R9D_XMM8_0FFh_icebp_c64,          255, RM_REG, T_SSE2,         4, 32, false, true, 9,   8, RT_ELEMENTS(s_aValuesFF),    s_aValuesFF },
     8171        {  bs3CpuInstr3_vpextrw_EDX_XMM1_0FFh_icebp_c64,         255, RM_REG, T_AVX_128,      4, 32, false, true, 2,   1, RT_ELEMENTS(s_aValuesFF),    s_aValuesFF },
     8172        {  bs3CpuInstr3_vpextrw_RDX_XMM1_0FFh_icebp_c64,         255, RM_REG, T_AVX_128,      8, 64, false, true, 2,   1, RT_ELEMENTS(s_aValuesFF),    s_aValuesFF },
     8173        {  bs3CpuInstr3_vpextrw_R9D_XMM8_0FFh_icebp_c64,         255, RM_REG, T_AVX_128,      4, 32, false, true, 9,   8, RT_ELEMENTS(s_aValuesFF),    s_aValuesFF },
     8174    };
     8175    static BS3CPUINSTR3_TEST2_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST2_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
     8176    unsigned const                         iTest       = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
     8177    return bs3CpuInstr3_WorkerTestType2(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
     8178                                        g_aXcptConfig5, RT_ELEMENTS(g_aXcptConfig5));
     8179}
     8180
     8181
    80788182
    80798183
    … …  
    1178511889    {
    1178611890#if 1 /*ndef DEBUG_bird*/
    11787 # define ALL_TESTS
     11891//# define ALL_TESTS
    1178811892#endif
    1178911893#if defined(ALL_TESTS)
    … …  
    1191112015        { "[v]blendpd",                                     bs3CpuInstr3_v_blendpd,  0 },
    1191212016#endif
    11913 #if defined(ALL_TESTS)
    11914         { "[v]pclmulqdq",                                   bs3CpuInstr3_v_pclmulqdq, 0 },
    11915         { "[v]pinsrw",                                      bs3CpuInstr3_v_pinsrw,    0 },
     12017#if 1 //defined(ALL_TESTS)
     12018        //{ "[v]pclmulqdq",                                   bs3CpuInstr3_v_pclmulqdq, 0 },
     12019        //{ "[v]pinsrw",                                      bs3CpuInstr3_v_pinsrw,    0 },
     12020        { "[v]pextrw",                                      bs3CpuInstr3_v_pextrw,    0 },
     12021
    1191612022#endif
    1191712023    };
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