Changeset 96714 in vbox for trunk/src/VBox/ValidationKit/bootsectors
- Timestamp:
- Sep 13, 2022 9:10:10 AM (3 years ago)
- svn:sync-xref-src-repo-rev:
- 153599
- Location:
- trunk/src/VBox/ValidationKit/bootsectors
- Files:
-
- 2 edited
-
bs3-cpu-instr-3-template.mac (modified) (1 diff)
-
bs3-cpu-instr-3.c32 (modified) (3 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3-template.mac
r96708 r96714 2922 2922 %endif 2923 2923 2924 ; 2925 ; [V]MOVMSKPS 2926 ; 2927 EMIT_INSTR_PLUS_ICEBP movmskps, EDX, XMM1 2928 EMIT_INSTR_PLUS_ICEBP vmovmskps, EDX, XMM1 2929 EMIT_INSTR_PLUS_ICEBP vmovmskps, EDX, YMM1 2930 2931 %if TMPL_BITS == 64 2932 EMIT_INSTR_PLUS_ICEBP movmskps, R9D, XMM8 2933 EMIT_INSTR_PLUS_ICEBP movmskps, RDX, XMM1 2934 2935 EMIT_INSTR_PLUS_ICEBP vmovmskps, R9D, XMM8 2936 EMIT_INSTR_PLUS_ICEBP vmovmskps, RDX, XMM1 2937 2938 EMIT_INSTR_PLUS_ICEBP vmovmskps, R9D, YMM8 2939 EMIT_INSTR_PLUS_ICEBP vmovmskps, RDX, YMM1 2940 %endif 2941 2942 ; 2943 ; [V]MOVMSKPD 2944 ; 2945 EMIT_INSTR_PLUS_ICEBP movmskpd, EDX, XMM1 2946 EMIT_INSTR_PLUS_ICEBP vmovmskpd, EDX, XMM1 2947 EMIT_INSTR_PLUS_ICEBP vmovmskpd, EDX, YMM1 2948 2949 %if TMPL_BITS == 64 2950 EMIT_INSTR_PLUS_ICEBP movmskpd, R9D, XMM8 2951 EMIT_INSTR_PLUS_ICEBP movmskpd, RDX, XMM1 2952 2953 EMIT_INSTR_PLUS_ICEBP vmovmskpd, R9D, XMM8 2954 EMIT_INSTR_PLUS_ICEBP vmovmskpd, RDX, XMM1 2955 2956 EMIT_INSTR_PLUS_ICEBP vmovmskpd, R9D, YMM8 2957 EMIT_INSTR_PLUS_ICEBP vmovmskpd, RDX, YMM1 2958 %endif 2959 2924 2960 2925 2961 %endif ; BS3_INSTANTIATING_CMN -
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3.c32
r96709 r96714 8180 8180 8181 8181 8182 /* 8183 * [V]MOVMSKPS / [V]MOVMSKPD. 8184 */ 8185 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movmskps_EDX_XMM1_icebp); 8186 extern FNBS3FAR bs3CpuInstr3_movmskps_RDX_XMM1_icebp_c64; 8187 extern FNBS3FAR bs3CpuInstr3_movmskps_R9D_XMM8_icebp_c64; 8188 extern FNBS3FAR bs3CpuInstr3_movmskps_RDX_XMM8_icebp_c64; 8189 8190 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovmskps_EDX_XMM1_icebp); 8191 extern FNBS3FAR bs3CpuInstr3_vmovmskps_RDX_XMM1_icebp_c64; 8192 extern FNBS3FAR bs3CpuInstr3_vmovmskps_EDX_XMM8_icebp_c64; 8193 extern FNBS3FAR bs3CpuInstr3_vmovmskps_R9D_XMM8_icebp_c64; 8194 8195 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovmskps_EDX_YMM1_icebp); 8196 extern FNBS3FAR bs3CpuInstr3_vmovmskps_RDX_YMM1_icebp_c64; 8197 extern FNBS3FAR bs3CpuInstr3_vmovmskps_EDX_YMM8_icebp_c64; 8198 extern FNBS3FAR bs3CpuInstr3_vmovmskps_R9D_YMM8_icebp_c64; 8199 8200 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_movmskpd_EDX_XMM1_icebp); 8201 extern FNBS3FAR bs3CpuInstr3_movmskpd_RDX_XMM1_icebp_c64; 8202 extern FNBS3FAR bs3CpuInstr3_movmskpd_R9D_XMM8_icebp_c64; 8203 extern FNBS3FAR bs3CpuInstr3_movmskpd_RDX_XMM8_icebp_c64; 8204 8205 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovmskpd_EDX_XMM1_icebp); 8206 extern FNBS3FAR bs3CpuInstr3_vmovmskpd_RDX_XMM1_icebp_c64; 8207 extern FNBS3FAR bs3CpuInstr3_vmovmskpd_EDX_XMM8_icebp_c64; 8208 extern FNBS3FAR bs3CpuInstr3_vmovmskpd_R9D_XMM8_icebp_c64; 8209 8210 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_vmovmskpd_EDX_YMM1_icebp); 8211 extern FNBS3FAR bs3CpuInstr3_vmovmskpd_RDX_YMM1_icebp_c64; 8212 extern FNBS3FAR bs3CpuInstr3_vmovmskpd_EDX_YMM8_icebp_c64; 8213 extern FNBS3FAR bs3CpuInstr3_vmovmskpd_R9D_YMM8_icebp_c64; 8214 8215 BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_movmskps_movmskpd(uint8_t bMode) 8216 { 8217 static BS3CPUINSTR3_TEST2_VALUES_T const s_aValuesR32_128[] = 8218 { 8219 { RTUINT256_INIT_C(0, 0, 0, 0), /*->*/ UINT64_C(0x0) }, 8220 { RTUINT256_INIT_C(1, 2, 0xffffffffffffffff, 0xffffffffffffffff), UINT64_C(0xf) }, 8221 { RTUINT256_INIT_C(3, 4, 0x7f7f7f7f7f7f7f7f, 0x7f7f7f7f7f7f7f7f), UINT64_C(0x0) }, 8222 { RTUINT256_INIT_C(5, 6, 0x8080808080808080, 0x8080808080808080), UINT64_C(0xf) }, 8223 { RTUINT256_INIT_C(7, 8, 0x1111222233334444, 0x5555666677778888), UINT64_C(0x0) }, 8224 { RTUINT256_INIT_C(9, 10, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), UINT64_C(0xb) }, 8225 }; 8226 8227 static BS3CPUINSTR3_TEST2_VALUES_T const s_aValuesR32_256[] = 8228 { 8229 { RTUINT256_INIT_C(0, 0, 0, 0), /*->*/ UINT64_C(0x00) }, 8230 { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), UINT64_C(0xff) }, 8231 { RTUINT256_INIT_C(0x7f7f7f7f7f7f7f7f, 0x7f7f7f7f7f7f7f7f, 0x7f7f7f7f7f7f7f7f, 0x7f7f7f7f7f7f7f7f), UINT64_C(0x00) }, 8232 { RTUINT256_INIT_C(0x8080808080808080, 0x8080808080808080, 0x8080808080808080, 0x8080808080808080), UINT64_C(0xff) }, 8233 { RTUINT256_INIT_C(0x9999aaaabbbbcccc, 0xddddeeeeffff0000, 0x1111222233334444, 0x5555666677778888), UINT64_C(0xf0) }, 8234 { RTUINT256_INIT_C(0x9c5ce073930996bb, 0xb4212fa8564c9ba2, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), UINT64_C(0xeb) }, 8235 }; 8236 8237 static BS3CPUINSTR3_TEST2_VALUES_T const s_aValuesR64_128[] = 8238 { 8239 { RTUINT256_INIT_C(0, 0, 0, 0), UINT64_C(0x0) }, 8240 { RTUINT256_INIT_C(1, 2, 0xffffffffffffffff, 0xffffffffffffffff), UINT64_C(0x3) }, 8241 { RTUINT256_INIT_C(3, 4, 0x7f7f7f7f7f7f7f7f, 0x7f7f7f7f7f7f7f7f), UINT64_C(0x0) }, 8242 { RTUINT256_INIT_C(5, 6, 0x8080808080808080, 0x8080808080808080), UINT64_C(0x3) }, 8243 { RTUINT256_INIT_C(7, 8, 0x1111222233334444, 0x5555666677778888), UINT64_C(0x0) }, 8244 { RTUINT256_INIT_C(9, 10, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), UINT64_C(0x3) }, 8245 }; 8246 8247 static BS3CPUINSTR3_TEST2_VALUES_T const s_aValuesR64_256[] = 8248 { 8249 { RTUINT256_INIT_C(0, 0, 0, 0), UINT64_C(0x0) }, 8250 { RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), UINT64_C(0xf) }, 8251 { RTUINT256_INIT_C(0x7f7f7f7f7f7f7f7f, 0x7f7f7f7f7f7f7f7f, 0x7f7f7f7f7f7f7f7f, 0x7f7f7f7f7f7f7f7f), UINT64_C(0x0) }, 8252 { RTUINT256_INIT_C(0x8080808080808080, 0x8080808080808080, 0x8080808080808080, 0x8080808080808080), UINT64_C(0xf) }, 8253 { RTUINT256_INIT_C(0x9999aaaabbbbcccc, 0xddddeeeeffff0000, 0x1111222233334444, 0x5555666677778888), UINT64_C(0xc) }, 8254 { RTUINT256_INIT_C(0x9c5ce073930996bb, 0xb4212fa8564c9ba2, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), UINT64_C(0xf) }, 8255 }; 8256 8257 static BS3CPUINSTR3_TEST2_T const s_aTests16[] = 8258 { 8259 { bs3CpuInstr3_movmskps_EDX_XMM1_icebp_c16, 255, RM_REG, T_SSE, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesR32_128), s_aValuesR32_128 }, 8260 { bs3CpuInstr3_vmovmskps_EDX_XMM1_icebp_c16, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesR32_128), s_aValuesR32_128 }, 8261 { bs3CpuInstr3_vmovmskps_EDX_YMM1_icebp_c16, 255, RM_REG, T_AVX_256, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesR32_256), s_aValuesR32_256 }, 8262 8263 { bs3CpuInstr3_movmskpd_EDX_XMM1_icebp_c16, 255, RM_REG, T_SSE2, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesR64_128), s_aValuesR64_128 }, 8264 { bs3CpuInstr3_vmovmskpd_EDX_XMM1_icebp_c16, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesR64_128), s_aValuesR64_128 }, 8265 { bs3CpuInstr3_vmovmskpd_EDX_YMM1_icebp_c16, 255, RM_REG, T_AVX_256, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesR64_256), s_aValuesR64_256 }, 8266 }; 8267 static BS3CPUINSTR3_TEST2_T const s_aTests32[] = 8268 { 8269 { bs3CpuInstr3_movmskps_EDX_XMM1_icebp_c32, 255, RM_REG, T_SSE, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesR32_128), s_aValuesR32_128 }, 8270 { bs3CpuInstr3_vmovmskps_EDX_XMM1_icebp_c32, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesR32_128), s_aValuesR32_128 }, 8271 { bs3CpuInstr3_vmovmskps_EDX_YMM1_icebp_c32, 255, RM_REG, T_AVX_256, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesR32_256), s_aValuesR32_256 }, 8272 8273 { bs3CpuInstr3_movmskpd_EDX_XMM1_icebp_c32, 255, RM_REG, T_SSE2, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesR64_128), s_aValuesR64_128 }, 8274 { bs3CpuInstr3_vmovmskpd_EDX_XMM1_icebp_c32, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesR64_128), s_aValuesR64_128 }, 8275 { bs3CpuInstr3_vmovmskpd_EDX_YMM1_icebp_c32, 255, RM_REG, T_AVX_256, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesR64_256), s_aValuesR64_256 }, 8276 }; 8277 static BS3CPUINSTR3_TEST2_T const s_aTests64[] = 8278 { 8279 { bs3CpuInstr3_movmskps_EDX_XMM1_icebp_c64, 255, RM_REG, T_SSE, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesR32_128), s_aValuesR32_128 }, 8280 { bs3CpuInstr3_movmskps_R9D_XMM8_icebp_c64, 255, RM_REG, T_SSE, 4, 32, false, true, 9, 8, RT_ELEMENTS(s_aValuesR32_128), s_aValuesR32_128 }, 8281 { bs3CpuInstr3_movmskps_RDX_XMM1_icebp_c64, 255, RM_REG, T_SSE, 8, 64, false, true, 2, 1, RT_ELEMENTS(s_aValuesR32_128), s_aValuesR32_128 }, 8282 { bs3CpuInstr3_vmovmskps_EDX_XMM1_icebp_c64, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesR32_128), s_aValuesR32_128 }, 8283 { bs3CpuInstr3_vmovmskps_RDX_XMM1_icebp_c64, 255, RM_REG, T_AVX_128, 8, 64, false, true, 2, 1, RT_ELEMENTS(s_aValuesR32_128), s_aValuesR32_128 }, 8284 { bs3CpuInstr3_vmovmskps_R9D_XMM8_icebp_c64, 255, RM_REG, T_AVX_128, 4, 32, false, true, 9, 8, RT_ELEMENTS(s_aValuesR32_128), s_aValuesR32_128 }, 8285 8286 { bs3CpuInstr3_vmovmskps_EDX_YMM1_icebp_c64, 255, RM_REG, T_AVX_256, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesR32_256), s_aValuesR32_256 }, 8287 { bs3CpuInstr3_vmovmskps_RDX_YMM1_icebp_c64, 255, RM_REG, T_AVX_256, 8, 64, false, true, 2, 1, RT_ELEMENTS(s_aValuesR32_256), s_aValuesR32_256 }, 8288 { bs3CpuInstr3_vmovmskps_R9D_YMM8_icebp_c64, 255, RM_REG, T_AVX_256, 4, 32, false, true, 9, 8, RT_ELEMENTS(s_aValuesR32_256), s_aValuesR32_256 }, 8289 8290 { bs3CpuInstr3_movmskpd_EDX_XMM1_icebp_c64, 255, RM_REG, T_SSE2, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesR64_128), s_aValuesR64_128 }, 8291 { bs3CpuInstr3_movmskpd_R9D_XMM8_icebp_c64, 255, RM_REG, T_SSE2, 4, 32, false, true, 9, 8, RT_ELEMENTS(s_aValuesR64_128), s_aValuesR64_128 }, 8292 { bs3CpuInstr3_movmskpd_RDX_XMM1_icebp_c64, 255, RM_REG, T_SSE2, 8, 64, false, true, 2, 1, RT_ELEMENTS(s_aValuesR64_128), s_aValuesR64_128 }, 8293 { bs3CpuInstr3_vmovmskpd_EDX_XMM1_icebp_c64, 255, RM_REG, T_AVX_128, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesR64_128), s_aValuesR64_128 }, 8294 { bs3CpuInstr3_vmovmskpd_RDX_XMM1_icebp_c64, 255, RM_REG, T_AVX_128, 8, 64, false, true, 2, 1, RT_ELEMENTS(s_aValuesR64_128), s_aValuesR64_128 }, 8295 { bs3CpuInstr3_vmovmskpd_R9D_XMM8_icebp_c64, 255, RM_REG, T_AVX_128, 4, 32, false, true, 9, 8, RT_ELEMENTS(s_aValuesR64_128), s_aValuesR64_128 }, 8296 8297 { bs3CpuInstr3_vmovmskpd_EDX_YMM1_icebp_c64, 255, RM_REG, T_AVX_256, 4, 32, false, true, 2, 1, RT_ELEMENTS(s_aValuesR64_256), s_aValuesR64_256 }, 8298 { bs3CpuInstr3_vmovmskpd_RDX_YMM1_icebp_c64, 255, RM_REG, T_AVX_256, 8, 64, false, true, 2, 1, RT_ELEMENTS(s_aValuesR64_256), s_aValuesR64_256 }, 8299 { bs3CpuInstr3_vmovmskpd_R9D_YMM8_icebp_c64, 255, RM_REG, T_AVX_256, 4, 32, false, true, 9, 8, RT_ELEMENTS(s_aValuesR64_256), s_aValuesR64_256 }, 8300 }; 8301 static BS3CPUINSTR3_TEST2_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST2_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); 8302 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); 8303 return bs3CpuInstr3_WorkerTestType2(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, 8304 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); 8305 } 8306 8307 8182 8308 8183 8309 … … 11889 12015 { 11890 12016 #if 1 /*ndef DEBUG_bird*/ 11891 //# define ALL_TESTS12017 # define ALL_TESTS 11892 12018 #endif 11893 12019 #if defined(ALL_TESTS) … … 12015 12141 { "[v]blendpd", bs3CpuInstr3_v_blendpd, 0 }, 12016 12142 #endif 12017 #if 1 //defined(ALL_TESTS)12018 //{ "[v]pclmulqdq", bs3CpuInstr3_v_pclmulqdq, 0 },12019 //{ "[v]pinsrw", bs3CpuInstr3_v_pinsrw, 0 },12143 #if defined(ALL_TESTS) 12144 { "[v]pclmulqdq", bs3CpuInstr3_v_pclmulqdq, 0 }, 12145 { "[v]pinsrw", bs3CpuInstr3_v_pinsrw, 0 }, 12020 12146 { "[v]pextrw", bs3CpuInstr3_v_pextrw, 0 }, 12147 { "[v]movmskps/[v]movmskpd", bs3CpuInstr3_v_movmskps_movmskpd, 0 }, 12021 12148 12022 12149 #endif
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