Changeset 96726 in vbox for trunk/src/VBox

Timestamp:

Sep 14, 2022 7:53:21 AM (2 years ago)

Author:

vboxsync

Message:

VMM/IEM: Implement cvtsd2si instruction, bugref:9898

Location:

trunk/src/VBox/VMM

Files:

• VMMAll/IEMAllAImpl.asm (modified) (1 diff)
• VMMAll/IEMAllAImplC.cpp (modified) (1 diff)
• VMMAll/IEMAllInstructionsTwoByte0f.cpp.h (modified) (1 diff)
• include/IEMInternal.h (modified) (1 diff)

trunk/src/VBox/VMM/VMMAll/IEMAllAImpl.asm

@@ -5546 +5546 @@
         EPILOGUE_4_ARGS
 ENDPROC iemAImpl_cvttsd2si_i64_r64
+
+
+;;
+; cvtsd2si instruction - 32-bit variant.
+;
+; @param    A0      FPU context (FXSTATE or XSAVEAREA).
+; @param    A1      Where to return the MXCSR value.
+; @param    A2      Pointer to the result operand (output).
+; @param    A3      Pointer to the second operand (input).
+;
+BEGINPROC_FASTCALL iemAImpl_cvtsd2si_i32_r64, 16
+        PROLOGUE_4_ARGS
+        IEMIMPL_SSE_PROLOGUE
+        SSE_LD_FXSTATE_MXCSR A0
+
+        cvtsd2si  T0_32, [A3]
+        mov       dword [A2], T0_32
+
+        SSE_ST_FXSTATE_MXCSR_ONLY A1, A0
+        IEMIMPL_SSE_PROLOGUE
+        EPILOGUE_4_ARGS
+ENDPROC iemAImpl_cvtsd2si_i32_r64
+
+;;
+; cvtsd2si instruction - 64-bit variant.
+;
+; @param    A0      FPU context (FXSTATE or XSAVEAREA).
+; @param    A1      Where to return the MXCSR value.
+; @param    A2      Pointer to the result operand (output).
+; @param    A3      Pointer to the second operand (input).
+;
+BEGINPROC_FASTCALL iemAImpl_cvtsd2si_i64_r64, 16
+        PROLOGUE_4_ARGS
+        IEMIMPL_SSE_PROLOGUE
+        SSE_LD_FXSTATE_MXCSR A0
+
+        cvtsd2si  T0, [A3]
+        mov       qword [A2], T0
+
+        SSE_ST_FXSTATE_MXCSR_ONLY A1, A0
+        IEMIMPL_SSE_PROLOGUE
+        EPILOGUE_4_ARGS
+ENDPROC iemAImpl_cvtsd2si_i64_r64

trunk/src/VBox/VMM/VMMAll/IEMAllAImplC.cpp

@@ -16030 +16030 @@
 }
 #endif
+
+
+/**
+ * CVTSD2SI
+ */
+#ifdef IEM_WITHOUT_ASSEMBLY
+IEM_DECL_IMPL_DEF(void, iemAImpl_cvtsd2si_i32_r64,(PCX86FXSTATE pFpuState, uint32_t *pfMxcsr, int32_t *pi32Dst, const uint64_t *pu64Src))
+{
+    RTFLOAT64U r64Src;
+
+    r64Src.u = *pu64Src;
+    iemSsePrepareValueR64(&r64Src, pFpuState->MXCSR, &r64Src); /* The de-normal flag is not set. */
+
+    softfloat_state_t SoftState = IEM_SOFTFLOAT_STATE_INITIALIZER_FROM_MXCSR(pFpuState->MXCSR);
+    *pi32Dst = f64_to_i32(iemFpSoftF64FromIprt(&r64Src), SoftState.roundingMode, true /*exact*/, &SoftState);
+    *pfMxcsr = pFpuState->MXCSR | (SoftState.exceptionFlags & X86_MXCSR_XCPT_FLAGS);
+}
+
+
+IEM_DECL_IMPL_DEF(void, iemAImpl_cvtsd2si_i64_r64,(PCX86FXSTATE pFpuState, uint32_t *pfMxcsr, int64_t *pi64Dst, const uint64_t *pu64Src))
+{
+    RTFLOAT64U r64Src;
+
+    r64Src.u = *pu64Src;
+    iemSsePrepareValueR64(&r64Src, pFpuState->MXCSR, &r64Src); /* The de-normal flag is not set. */
+
+    softfloat_state_t SoftState = IEM_SOFTFLOAT_STATE_INITIALIZER_FROM_MXCSR(pFpuState->MXCSR);
+    *pi64Dst = f64_to_i64(iemFpSoftF64FromIprt(&r64Src), SoftState.roundingMode, true /*exact*/, &SoftState);
+    *pfMxcsr = pFpuState->MXCSR | (SoftState.exceptionFlags & X86_MXCSR_XCPT_FLAGS);
+}
+#endif

trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsTwoByte0f.cpp.h

@@ -3812 +3812 @@
 /** Opcode 0xf3 0x0f 0x2d - cvtss2si Gy, Wss */
 FNIEMOP_STUB(iemOp_cvtss2si_Gy_Wss);
+
+
 /** Opcode 0xf2 0x0f 0x2d - cvtsd2si Gy, Wsd */
-FNIEMOP_STUB(iemOp_cvtsd2si_Gy_Wsd);
+FNIEMOP_DEF(iemOp_cvtsd2si_Gy_Wsd)
+{
+    IEMOP_MNEMONIC2(RM, CVTSD2SI, cvtsd2si, Gy, Wsd, DISOPTYPE_HARMLESS | DISOPTYPE_SSE, 0);
+
+    uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm);
+    if (pVCpu->iem.s.fPrefixes & IEM_OP_PRF_SIZE_REX_W)
+    {
+        if (IEM_IS_MODRM_REG_MODE(bRm))
+        {
+            /* greg64, XMM */
+            IEM_MC_BEGIN(3, 4);
+            IEM_MC_LOCAL(uint32_t,  fMxcsr);
+            IEM_MC_LOCAL(int64_t,   i64Dst);
+            IEM_MC_ARG_LOCAL_REF(uint32_t *, pfMxcsr, fMxcsr,     0);
+            IEM_MC_ARG_LOCAL_REF(int64_t *,  pi64Dst, i64Dst,     1);
+            IEM_MC_ARG(const uint64_t *,     pu64Src,             2);
+
+            IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
+            IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
+            IEM_MC_PREPARE_SSE_USAGE(); /** @todo: This is superfluous because IEM_MC_CALL_SSE_AIMPL_3() is calling this but the tstIEMCheckMc testcase depends on it. */
+
+            IEM_MC_REF_XREG_U64_CONST(pu64Src, IEM_GET_MODRM_RM(pVCpu, bRm));
+            IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_cvtsd2si_i64_r64, pfMxcsr, pi64Dst, pu64Src);
+            IEM_MC_SSE_UPDATE_MXCSR(fMxcsr);
+            IEM_MC_IF_MXCSR_XCPT_PENDING()
+                IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
+            IEM_MC_ELSE()
+                IEM_MC_STORE_GREG_I64(i64Dst, IEM_GET_MODRM_REG(pVCpu, bRm));
+            IEM_MC_ENDIF();
+
+            IEM_MC_ADVANCE_RIP();
+            IEM_MC_END();
+        }
+        else
+        {
+            /* greg64, [mem64] */
+            IEM_MC_BEGIN(3, 4);
+            IEM_MC_LOCAL(RTGCPTR,   GCPtrEffSrc);
+            IEM_MC_LOCAL(uint32_t,  fMxcsr);
+            IEM_MC_LOCAL(int64_t,   i64Dst);
+            IEM_MC_LOCAL(uint64_t,  u64Src);
+            IEM_MC_ARG_LOCAL_REF(uint32_t *,        pfMxcsr, fMxcsr,     0);
+            IEM_MC_ARG_LOCAL_REF(int64_t *,         pi64Dst, i64Dst,     1);
+            IEM_MC_ARG_LOCAL_REF(const uint64_t *,  pu64Src, u64Src,     2);
+
+            IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
+            IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
+            IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
+            IEM_MC_PREPARE_SSE_USAGE(); /** @todo: This is superfluous because IEM_MC_CALL_SSE_AIMPL_3() is calling this but the tstIEMCheckMc testcase depends on it. */
+
+            IEM_MC_FETCH_MEM_U64(u64Src, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
+            IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_cvtsd2si_i64_r64, pfMxcsr, pi64Dst, pu64Src);
+            IEM_MC_SSE_UPDATE_MXCSR(fMxcsr);
+            IEM_MC_IF_MXCSR_XCPT_PENDING()
+                IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
+            IEM_MC_ELSE()
+                IEM_MC_STORE_GREG_I64(i64Dst, IEM_GET_MODRM_REG(pVCpu, bRm));
+            IEM_MC_ENDIF();
+
+            IEM_MC_ADVANCE_RIP();
+            IEM_MC_END();
+        }
+    }
+    else
+    {
+        if (IEM_IS_MODRM_REG_MODE(bRm))
+        {
+            /* greg, XMM */
+            IEM_MC_BEGIN(3, 4);
+            IEM_MC_LOCAL(uint32_t,  fMxcsr);
+            IEM_MC_LOCAL(int32_t,   i32Dst);
+            IEM_MC_ARG_LOCAL_REF(uint32_t *, pfMxcsr, fMxcsr,     0);
+            IEM_MC_ARG_LOCAL_REF(int32_t *,  pi32Dst, i32Dst,     1);
+            IEM_MC_ARG(const uint64_t *,     pu64Src,             2);
+
+            IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
+            IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
+            IEM_MC_PREPARE_SSE_USAGE(); /** @todo: This is superfluous because IEM_MC_CALL_SSE_AIMPL_3() is calling this but the tstIEMCheckMc testcase depends on it. */
+
+            IEM_MC_REF_XREG_U64_CONST(pu64Src, IEM_GET_MODRM_RM(pVCpu, bRm));
+            IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_cvtsd2si_i32_r64, pfMxcsr, pi32Dst, pu64Src);
+            IEM_MC_SSE_UPDATE_MXCSR(fMxcsr);
+            IEM_MC_IF_MXCSR_XCPT_PENDING()
+                IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
+            IEM_MC_ELSE()
+                IEM_MC_STORE_GREG_I32(i32Dst, IEM_GET_MODRM_REG(pVCpu, bRm));
+            IEM_MC_ENDIF();
+
+            IEM_MC_ADVANCE_RIP();
+            IEM_MC_END();
+        }
+        else
+        {
+            /* greg, [mem] */
+            IEM_MC_BEGIN(3, 4);
+            IEM_MC_LOCAL(RTGCPTR,   GCPtrEffSrc);
+            IEM_MC_LOCAL(uint32_t,  fMxcsr);
+            IEM_MC_LOCAL(int32_t,   i32Dst);
+            IEM_MC_LOCAL(uint64_t,  u64Src);
+            IEM_MC_ARG_LOCAL_REF(uint32_t *,        pfMxcsr, fMxcsr,     0);
+            IEM_MC_ARG_LOCAL_REF(int32_t *,         pi32Dst, i32Dst,     1);
+            IEM_MC_ARG_LOCAL_REF(const uint64_t *,  pu64Src, u64Src,     2);
+
+            IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0);
+            IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
+            IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT();
+            IEM_MC_PREPARE_SSE_USAGE(); /** @todo: This is superfluous because IEM_MC_CALL_SSE_AIMPL_3() is calling this but the tstIEMCheckMc testcase depends on it. */
+
+            IEM_MC_FETCH_MEM_U64(u64Src, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
+            IEM_MC_CALL_SSE_AIMPL_3(iemAImpl_cvtsd2si_i32_r64, pfMxcsr, pi32Dst, pu64Src);
+            IEM_MC_SSE_UPDATE_MXCSR(fMxcsr);
+            IEM_MC_IF_MXCSR_XCPT_PENDING()
+                IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT();
+            IEM_MC_ELSE()
+                IEM_MC_STORE_GREG_I32(i32Dst, IEM_GET_MODRM_REG(pVCpu, bRm));
+            IEM_MC_ENDIF();
+
+            IEM_MC_ADVANCE_RIP();
+            IEM_MC_END();
+        }
+    }
+    return VINF_SUCCESS;
+}
 
 /** Opcode      0x0f 0x2e - ucomiss Vss, Wss */

trunk/src/VBox/VMM/include/IEMInternal.h

@@ -2300 +2300 @@
 
 FNIEMAIMPLSSEF2I32U64 iemAImpl_cvttsd2si_i32_r64;
+FNIEMAIMPLSSEF2I32U64 iemAImpl_cvtsd2si_i32_r64;
+
 FNIEMAIMPLSSEF2I64U64 iemAImpl_cvttsd2si_i64_r64;
+FNIEMAIMPLSSEF2I64U64 iemAImpl_cvtsd2si_i64_r64;
 
 /** @} */