Changeset 96736 in vbox

Timestamp:

Sep 14, 2022 11:57:13 AM (2 years ago)

Author:

vboxsync

Message:

VMM/PGM: Nested VMX: bugref:10092 Adjusted guest EPT masks and comments.

File:

• trunk/src/VBox/VMM/VMMR3/PGM.cpp (modified) (2 diffs)

trunk/src/VBox/VMM/VMMR3/PGM.cpp

@@ -1720 +1720 @@
         pVCpu->pgm.s.fGstEptMbzBigPdpteMask   = fMbzPageFrameMask | fGstEptMbzBigPdpteMask;
         pVCpu->pgm.s.fGstEptMbzPml4eMask      = fMbzPageFrameMask | EPT_PML4E_MBZ_MASK;
-        pVCpu->pgm.s.fGstEptPresentMask       = EPT_PRESENT_MASK;
-
-        /* If any of the features (in the assert below) are enabled, we would have to shadow the relevant bits. */
+
+        /* If any of the features in the assert below are enabled, additional bits would need to be shadowed. */
         Assert(   !pVM->cpum.ro.GuestFeatures.fVmxModeBasedExecuteEpt
                && !pVM->cpum.ro.GuestFeatures.fVmxSppEpt
@@ -1728 +1727 @@
                && !(fEptVpidCap & MSR_IA32_VMX_EPT_VPID_CAP_ACCESS_DIRTY));
         /* We need to shadow reserved bits as guest EPT tables can set them to trigger EPT misconfigs.  */
-        pVCpu->pgm.s.fGstEptShadowedPteMask   = GCPhysRsvdAddrMask | EPT_PRESENT_MASK | EPT_E_MEMTYPE_MASK;
-        pVCpu->pgm.s.fGstEptShadowedPdeMask   = GCPhysRsvdAddrMask | EPT_PRESENT_MASK | EPT_E_MEMTYPE_MASK | EPT_E_LEAF;
-        pVCpu->pgm.s.fGstEptShadowedPdpteMask = GCPhysRsvdAddrMask | EPT_PRESENT_MASK | EPT_E_MEMTYPE_MASK | EPT_E_LEAF;
+        pVCpu->pgm.s.fGstEptShadowedPteMask   = GCPhysRsvdAddrMask | EPT_PRESENT_MASK | EPT_E_MEMTYPE_MASK | EPT_E_IGNORE_PAT;
+        pVCpu->pgm.s.fGstEptShadowedPdeMask   = GCPhysRsvdAddrMask | EPT_PRESENT_MASK | EPT_E_MEMTYPE_MASK | EPT_E_IGNORE_PAT | EPT_E_LEAF;
+        pVCpu->pgm.s.fGstEptShadowedPdpteMask = GCPhysRsvdAddrMask | EPT_PRESENT_MASK | EPT_E_MEMTYPE_MASK | EPT_E_IGNORE_PAT | EPT_E_LEAF;
         pVCpu->pgm.s.fGstEptShadowedPml4eMask = GCPhysRsvdAddrMask | EPT_PRESENT_MASK | EPT_PML4E_MBZ_MASK;
+        /* If mode-based execute control for EPT is enabled, we would need to include bit 10 in the present mask. */
+        pVCpu->pgm.s.fGstEptPresentMask       = EPT_PRESENT_MASK;
 #endif
     }