Changeset 96748 in vbox for trunk/src/VBox/VMM/VMMAll
- Timestamp:
- Sep 15, 2022 5:32:44 PM (2 years ago)
- Location:
- trunk/src/VBox/VMM/VMMAll
- Files:
-
- 4 edited
-
IEMAllAImpl.asm (modified) (1 diff)
-
IEMAllAImplC.cpp (modified) (1 diff)
-
IEMAllInstructionsTwoByte0f.cpp.h (modified) (1 diff)
-
IEMAllInstructionsVexMap1.cpp.h (modified) (1 diff)
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/VMMAll/IEMAllAImpl.asm
r96741 r96748 5761 5761 EPILOGUE_4_ARGS 5762 5762 ENDPROC iemAImpl_cvtsi2sd_r64_i64 5763 5764 5765 ;; 5766 ; Initialize the SSE MXCSR register using the guest value partially to 5767 ; account for rounding mode. 5768 ; 5769 ; @uses 4 bytes of stack to save the original value, T0. 5770 ; @param 1 Expression giving the address of the MXCSR register of the guest. 5771 ; 5772 %macro SSE_LD_FXSTATE_MXCSR_ONLY 1 5773 sub xSP, 4 5774 5775 stmxcsr [xSP] 5776 mov T0_32, [%1] 5777 and T0_32, X86_MXCSR_FZ | X86_MXCSR_RC_MASK | X86_MXCSR_DAZ 5778 or T0_32, X86_MXCSR_XCPT_MASK 5779 sub xSP, 4 5780 mov [xSP], T0_32 5781 ldmxcsr [xSP] 5782 add xSP, 4 5783 %endmacro 5784 5785 5786 ;; 5787 ; Restores the SSE MXCSR register with the original value. 5788 ; 5789 ; @uses 4 bytes of stack to save the content of MXCSR value, T0, T1. 5790 ; @param 1 Expression giving the address where to return the MXCSR value - only the MXCSR is stored, no IEMSSERESULT is used. 5791 ; 5792 ; @note Restores the stack pointer. 5793 ; 5794 %macro SSE_ST_FXSTATE_MXCSR_ONLY_NO_FXSTATE 1 5795 sub xSP, 4 5796 stmxcsr [xSP] 5797 mov T0_32, [xSP] 5798 add xSP, 4 5799 ; Merge the status bits into the original MXCSR value. 5800 mov T1_32, [%1] 5801 and T0_32, X86_MXCSR_XCPT_FLAGS 5802 or T0_32, T1_32 5803 mov [%1], T0_32 5804 5805 ldmxcsr [xSP] 5806 add xSP, 4 5807 %endmacro 5808 5809 5810 ; 5811 ; UCOMISS (SSE) 5812 ; 5813 ; @param A0 Pointer to the MXCSR value (input/output). 5814 ; @param A1 Pointer to the EFLAGS value (input/output). 5815 ; @param A2 Pointer to the first source operand (aka readonly destination). 5816 ; @param A3 Pointer to the second source operand. 5817 ; 5818 BEGINPROC_FASTCALL iemAImpl_ucomiss_u128, 12 5819 PROLOGUE_3_ARGS 5820 IEMIMPL_SSE_PROLOGUE 5821 SSE_LD_FXSTATE_MXCSR_ONLY A0 5822 5823 movdqu xmm0, [A2] 5824 movdqu xmm1, [A3] 5825 ucomiss xmm0, xmm1 5826 IEM_SAVE_FLAGS A1, X86_EFL_STATUS_BITS, 0 5827 5828 SSE_ST_FXSTATE_MXCSR_ONLY_NO_FXSTATE A0 5829 IEMIMPL_SSE_EPILOGUE 5830 EPILOGUE_3_ARGS 5831 ENDPROC iemAImpl_ucomiss_u128 5832 5833 BEGINPROC_FASTCALL iemAImpl_vucomiss_u128, 12 5834 PROLOGUE_3_ARGS 5835 IEMIMPL_SSE_PROLOGUE 5836 SSE_LD_FXSTATE_MXCSR_ONLY A0 5837 5838 movdqu xmm0, [A2] 5839 movdqu xmm1, [A3] 5840 vucomiss xmm0, xmm1 5841 IEM_SAVE_FLAGS A1, X86_EFL_STATUS_BITS, 0 5842 5843 SSE_ST_FXSTATE_MXCSR_ONLY_NO_FXSTATE A0 5844 IEMIMPL_SSE_EPILOGUE 5845 EPILOGUE_3_ARGS 5846 ENDPROC iemAImpl_vucomiss_u128 5847 5848 5849 ; 5850 ; UCOMISD (SSE) 5851 ; 5852 ; @param A0 Pointer to the MXCSR value (input/output). 5853 ; @param A1 Pointer to the EFLAGS value (input/output). 5854 ; @param A2 Pointer to the first source operand (aka readonly destination). 5855 ; @param A3 Pointer to the second source operand. 5856 ; 5857 BEGINPROC_FASTCALL iemAImpl_ucomisd_u128, 12 5858 PROLOGUE_3_ARGS 5859 IEMIMPL_SSE_PROLOGUE 5860 SSE_LD_FXSTATE_MXCSR_ONLY A0 5861 5862 movdqu xmm0, [A2] 5863 movdqu xmm1, [A3] 5864 ucomisd xmm0, xmm1 5865 IEM_SAVE_FLAGS A1, X86_EFL_STATUS_BITS, 0 5866 5867 SSE_ST_FXSTATE_MXCSR_ONLY_NO_FXSTATE A0 5868 IEMIMPL_SSE_EPILOGUE 5869 EPILOGUE_3_ARGS 5870 ENDPROC iemAImpl_ucomisd_u128 5871 5872 BEGINPROC_FASTCALL iemAImpl_vucomisd_u128, 12 5873 PROLOGUE_3_ARGS 5874 IEMIMPL_SSE_PROLOGUE 5875 SSE_LD_FXSTATE_MXCSR_ONLY A0 5876 5877 movdqu xmm0, [A2] 5878 movdqu xmm1, [A3] 5879 vucomisd xmm0, xmm1 5880 IEM_SAVE_FLAGS A1, X86_EFL_STATUS_BITS, 0 5881 5882 SSE_ST_FXSTATE_MXCSR_ONLY_NO_FXSTATE A0 5883 IEMIMPL_SSE_EPILOGUE 5884 EPILOGUE_3_ARGS 5885 ENDPROC iemAImpl_vucomisd_u128 5886 5887 ; 5888 ; COMISS (SSE) 5889 ; 5890 ; @param A0 Pointer to the MXCSR value (input/output). 5891 ; @param A1 Pointer to the EFLAGS value (input/output). 5892 ; @param A2 Pointer to the first source operand (aka readonly destination). 5893 ; @param A3 Pointer to the second source operand. 5894 ; 5895 BEGINPROC_FASTCALL iemAImpl_comiss_u128, 12 5896 PROLOGUE_3_ARGS 5897 IEMIMPL_SSE_PROLOGUE 5898 SSE_LD_FXSTATE_MXCSR_ONLY A0 5899 5900 movdqu xmm0, [A2] 5901 movdqu xmm1, [A3] 5902 comiss xmm0, xmm1 5903 IEM_SAVE_FLAGS A1, X86_EFL_STATUS_BITS, 0 5904 5905 SSE_ST_FXSTATE_MXCSR_ONLY_NO_FXSTATE A0 5906 IEMIMPL_SSE_EPILOGUE 5907 EPILOGUE_3_ARGS 5908 ENDPROC iemAImpl_comiss_u128 5909 5910 BEGINPROC_FASTCALL iemAImpl_vcomiss_u128, 12 5911 PROLOGUE_3_ARGS 5912 IEMIMPL_SSE_PROLOGUE 5913 SSE_LD_FXSTATE_MXCSR_ONLY A0 5914 5915 movdqu xmm0, [A2] 5916 movdqu xmm1, [A3] 5917 vcomiss xmm0, xmm1 5918 IEM_SAVE_FLAGS A1, X86_EFL_STATUS_BITS, 0 5919 5920 SSE_ST_FXSTATE_MXCSR_ONLY_NO_FXSTATE A0 5921 IEMIMPL_SSE_EPILOGUE 5922 EPILOGUE_3_ARGS 5923 ENDPROC iemAImpl_vcomiss_u128 5924 5925 5926 ; 5927 ; COMISD (SSE) 5928 ; 5929 ; @param A0 Pointer to the MXCSR value (input/output). 5930 ; @param A1 Pointer to the EFLAGS value (input/output). 5931 ; @param A2 Pointer to the first source operand (aka readonly destination). 5932 ; @param A3 Pointer to the second source operand. 5933 ; 5934 BEGINPROC_FASTCALL iemAImpl_comisd_u128, 12 5935 PROLOGUE_3_ARGS 5936 IEMIMPL_SSE_PROLOGUE 5937 SSE_LD_FXSTATE_MXCSR_ONLY A0 5938 5939 movdqu xmm0, [A2] 5940 movdqu xmm1, [A3] 5941 comisd xmm0, xmm1 5942 IEM_SAVE_FLAGS A1, X86_EFL_STATUS_BITS, 0 5943 5944 SSE_ST_FXSTATE_MXCSR_ONLY_NO_FXSTATE A0 5945 IEMIMPL_SSE_EPILOGUE 5946 EPILOGUE_3_ARGS 5947 ENDPROC iemAImpl_comisd_u128 5948 5949 BEGINPROC_FASTCALL iemAImpl_vcomisd_u128, 12 5950 PROLOGUE_3_ARGS 5951 IEMIMPL_SSE_PROLOGUE 5952 SSE_LD_FXSTATE_MXCSR_ONLY A0 5953 5954 movdqu xmm0, [A2] 5955 movdqu xmm1, [A3] 5956 vcomisd xmm0, xmm1 5957 IEM_SAVE_FLAGS A1, X86_EFL_STATUS_BITS, 0 5958 5959 SSE_ST_FXSTATE_MXCSR_ONLY_NO_FXSTATE A0 5960 IEMIMPL_SSE_EPILOGUE 5961 EPILOGUE_3_ARGS 5962 ENDPROC iemAImpl_vcomisd_u128 -
trunk/src/VBox/VMM/VMMAll/IEMAllAImplC.cpp
r96741 r96748 16165 16165 } 16166 16166 #endif 16167 16168 16169 /** 16170 * [V]UCOMISS 16171 */ 16172 #ifdef IEM_WITHOUT_ASSEMBLY 16173 IEM_DECL_IMPL_DEF(void, iemAImpl_ucomiss_u128,(uint32_t *pfMxcsr, uint32_t *pfEFlags, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2)) 16174 { 16175 uint32_t fEFlagsNew = *pfEFlags & ~X86_EFL_STATUS_BITS; 16176 16177 if (RTFLOAT32U_IS_SIGNALLING_NAN(&puSrc1->ar32[0]) || RTFLOAT32U_IS_SIGNALLING_NAN(&puSrc2->ar32[0])) 16178 { 16179 *pfMxcsr |= X86_MXCSR_IE; 16180 fEFlagsNew |= X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF; /* UNORDERED 111 */ 16181 } 16182 else if (RTFLOAT32U_IS_QUIET_NAN(&puSrc1->ar32[0]) || RTFLOAT32U_IS_QUIET_NAN(&puSrc2->ar32[0])) 16183 { 16184 /* ucomiss doesn't raise \#IE for quiet NaNs. */ 16185 fEFlagsNew |= X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF; /* UNORDERED 111 */ 16186 } 16187 else 16188 { 16189 softfloat_state_t SoftState = IEM_SOFTFLOAT_STATE_INITIALIZER_FROM_MXCSR(*pfMxcsr); 16190 16191 RTFLOAT32U r32Src1, r32Src2; 16192 uint32_t fDe = iemSsePrepareValueR32(&r32Src1, *pfMxcsr, &puSrc1->ar32[0]); 16193 fDe |= iemSsePrepareValueR32(&r32Src2, *pfMxcsr, &puSrc2->ar32[0]); 16194 16195 float32_t f32Src1 = iemFpSoftF32FromIprt(&r32Src1); 16196 float32_t f32Src2 = iemFpSoftF32FromIprt(&r32Src2); 16197 if (f32_eq(f32Src1, f32Src2, &SoftState)) 16198 fEFlagsNew |= X86_EFL_ZF; /* EQUAL 100 */ 16199 else if (f32_lt(f32Src1, f32Src2, &SoftState)) 16200 fEFlagsNew |= X86_EFL_CF; /* LESS_THAN 001 */ 16201 /* else: GREATER_THAN 000 */ 16202 16203 *pfMxcsr |= fDe; 16204 } 16205 16206 *pfEFlags = fEFlagsNew; 16207 } 16208 #endif 16209 16210 IEM_DECL_IMPL_DEF(void, iemAImpl_vucomiss_u128_fallback,(uint32_t *pfMxcsr, uint32_t *pfEFlags, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2)) 16211 { 16212 iemAImpl_ucomiss_u128(pfMxcsr, pfEFlags, puSrc1, puSrc2); 16213 } 16214 16215 16216 /** 16217 * [V]UCOMISD 16218 */ 16219 #ifdef IEM_WITHOUT_ASSEMBLY 16220 IEM_DECL_IMPL_DEF(void, iemAImpl_ucomisd_u128,(uint32_t *pfMxcsr, uint32_t *pfEFlags, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2)) 16221 { 16222 uint32_t fEFlagsNew = *pfEFlags & ~X86_EFL_STATUS_BITS; 16223 16224 if (RTFLOAT64U_IS_SIGNALLING_NAN(&puSrc1->ar64[0]) || RTFLOAT64U_IS_SIGNALLING_NAN(&puSrc2->ar64[0])) 16225 { 16226 *pfMxcsr |= X86_MXCSR_IE; 16227 fEFlagsNew |= X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF; /* UNORDERED 111 */ 16228 } 16229 else if (RTFLOAT64U_IS_QUIET_NAN(&puSrc1->ar64[0]) || RTFLOAT64U_IS_QUIET_NAN(&puSrc2->ar64[0])) 16230 { 16231 /* ucomiss doesn't raise \#IE for quiet NaNs. */ 16232 fEFlagsNew |= X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF; /* UNORDERED 111 */ 16233 } 16234 else 16235 { 16236 softfloat_state_t SoftState = IEM_SOFTFLOAT_STATE_INITIALIZER_FROM_MXCSR(*pfMxcsr); 16237 16238 RTFLOAT64U r64Src1, r64Src2; 16239 uint32_t fDe = iemSsePrepareValueR64(&r64Src1, *pfMxcsr, &puSrc1->ar64[0]); 16240 fDe |= iemSsePrepareValueR64(&r64Src2, *pfMxcsr, &puSrc2->ar64[0]); 16241 16242 float64_t f64Src1 = iemFpSoftF64FromIprt(&r64Src1); 16243 float64_t f64Src2 = iemFpSoftF64FromIprt(&r64Src2); 16244 if (f64_eq(f64Src1, f64Src2, &SoftState)) 16245 fEFlagsNew |= X86_EFL_ZF; /* EQUAL 100 */ 16246 else if (f64_lt(f64Src1, f64Src2, &SoftState)) 16247 fEFlagsNew |= X86_EFL_CF; /* LESS_THAN 001 */ 16248 /* else: GREATER_THAN 000 */ 16249 16250 *pfMxcsr |= fDe; 16251 } 16252 16253 *pfEFlags = fEFlagsNew; 16254 } 16255 #endif 16256 16257 IEM_DECL_IMPL_DEF(void, iemAImpl_vucomisd_u128_fallback,(uint32_t *pfMxcsr, uint32_t *pfEFlags, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2)) 16258 { 16259 iemAImpl_ucomisd_u128(pfMxcsr, pfEFlags, puSrc1, puSrc2); 16260 } 16261 16262 16263 /** 16264 * [V]COMISS 16265 */ 16266 #ifdef IEM_WITHOUT_ASSEMBLY 16267 IEM_DECL_IMPL_DEF(void, iemAImpl_comiss_u128,(uint32_t *pfMxcsr, uint32_t *pfEFlags, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2)) 16268 { 16269 uint32_t fEFlagsNew = *pfEFlags & ~X86_EFL_STATUS_BITS; 16270 16271 if ( RTFLOAT32U_IS_SIGNALLING_NAN(&puSrc1->ar32[0]) || RTFLOAT32U_IS_SIGNALLING_NAN(&puSrc2->ar32[0]) 16272 || RTFLOAT32U_IS_QUIET_NAN(&puSrc1->ar32[0]) || RTFLOAT32U_IS_QUIET_NAN(&puSrc2->ar32[0])) 16273 { 16274 *pfMxcsr |= X86_MXCSR_IE; 16275 fEFlagsNew |= X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF; /* UNORDERED 111 */ 16276 } 16277 else 16278 { 16279 softfloat_state_t SoftState = IEM_SOFTFLOAT_STATE_INITIALIZER_FROM_MXCSR(*pfMxcsr); 16280 16281 RTFLOAT32U r32Src1, r32Src2; 16282 uint32_t fDe = iemSsePrepareValueR32(&r32Src1, *pfMxcsr, &puSrc1->ar32[0]); 16283 fDe |= iemSsePrepareValueR32(&r32Src2, *pfMxcsr, &puSrc2->ar32[0]); 16284 16285 float32_t f32Src1 = iemFpSoftF32FromIprt(&r32Src1); 16286 float32_t f32Src2 = iemFpSoftF32FromIprt(&r32Src2); 16287 if (f32_eq(f32Src1, f32Src2, &SoftState)) 16288 fEFlagsNew |= X86_EFL_ZF; /* EQUAL 100 */ 16289 else if (f32_lt(f32Src1, f32Src2, &SoftState)) 16290 fEFlagsNew |= X86_EFL_CF; /* LESS_THAN 001 */ 16291 /* else: GREATER_THAN 000 */ 16292 16293 *pfMxcsr |= fDe; 16294 } 16295 16296 *pfEFlags = fEFlagsNew; 16297 } 16298 #endif 16299 16300 16301 IEM_DECL_IMPL_DEF(void, iemAImpl_vcomiss_u128_fallback,(uint32_t *pfMxcsr, uint32_t *pfEFlags, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2)) 16302 { 16303 iemAImpl_comiss_u128(pfMxcsr, pfEFlags, puSrc1, puSrc2); 16304 } 16305 16306 16307 /** 16308 * [V]COMISD 16309 */ 16310 #ifdef IEM_WITHOUT_ASSEMBLY 16311 IEM_DECL_IMPL_DEF(void, iemAImpl_comisd_u128,(uint32_t *pfMxcsr, uint32_t *pfEFlags, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2)) 16312 { 16313 uint32_t fEFlagsNew = *pfEFlags & ~X86_EFL_STATUS_BITS; 16314 16315 if ( RTFLOAT64U_IS_SIGNALLING_NAN(&puSrc1->ar64[0]) || RTFLOAT64U_IS_SIGNALLING_NAN(&puSrc2->ar64[0]) 16316 || RTFLOAT64U_IS_QUIET_NAN(&puSrc1->ar64[0]) || RTFLOAT64U_IS_QUIET_NAN(&puSrc2->ar64[0])) 16317 { 16318 *pfMxcsr |= X86_MXCSR_IE; 16319 fEFlagsNew |= X86_EFL_ZF | X86_EFL_PF | X86_EFL_CF; /* UNORDERED 111 */ 16320 } 16321 else 16322 { 16323 softfloat_state_t SoftState = IEM_SOFTFLOAT_STATE_INITIALIZER_FROM_MXCSR(*pfMxcsr); 16324 16325 RTFLOAT64U r64Src1, r64Src2; 16326 uint32_t fDe = iemSsePrepareValueR64(&r64Src1, *pfMxcsr, &puSrc1->ar64[0]); 16327 fDe |= iemSsePrepareValueR64(&r64Src2, *pfMxcsr, &puSrc2->ar64[0]); 16328 16329 float64_t f64Src1 = iemFpSoftF64FromIprt(&r64Src1); 16330 float64_t f64Src2 = iemFpSoftF64FromIprt(&r64Src2); 16331 if (f64_eq(f64Src1, f64Src2, &SoftState)) 16332 fEFlagsNew |= X86_EFL_ZF; /* EQUAL 100 */ 16333 else if (f64_lt(f64Src1, f64Src2, &SoftState)) 16334 fEFlagsNew |= X86_EFL_CF; /* LESS_THAN 001 */ 16335 /* else: GREATER_THAN 000 */ 16336 16337 *pfMxcsr |= fDe; 16338 } 16339 16340 *pfEFlags = fEFlagsNew; 16341 } 16342 #endif 16343 16344 IEM_DECL_IMPL_DEF(void, iemAImpl_vcomisd_u128_fallback,(uint32_t *pfMxcsr, uint32_t *pfEFlags, PCX86XMMREG puSrc1, PCX86XMMREG puSrc2)) 16345 { 16346 iemAImpl_comisd_u128(pfMxcsr, pfEFlags, puSrc1, puSrc2); 16347 } -
trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsTwoByte0f.cpp.h
r96741 r96748 4435 4435 } 4436 4436 4437 4437 4438 /** Opcode 0x0f 0x2e - ucomiss Vss, Wss */ 4438 FNIEMOP_STUB(iemOp_ucomiss_Vss_Wss); // NEXT 4439 FNIEMOP_DEF(iemOp_ucomiss_Vss_Wss) 4440 { 4441 IEMOP_MNEMONIC2(RM, UCOMISS, ucomiss, Vss, Wss, DISOPTYPE_HARMLESS | DISOPTYPE_SSE, IEMOPHINT_IGNORES_OP_SIZES); 4442 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); 4443 if (IEM_IS_MODRM_REG_MODE(bRm)) 4444 { 4445 /* 4446 * Register, register. 4447 */ 4448 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 4449 IEM_MC_BEGIN(4, 1); 4450 IEM_MC_LOCAL(uint32_t, fEFlags); 4451 IEM_MC_ARG(uint32_t *, pfMxcsr, 0); 4452 IEM_MC_ARG_LOCAL_REF(uint32_t *, pEFlags, fEFlags, 1); 4453 IEM_MC_ARG(PCX86XMMREG, puSrc1, 2); 4454 IEM_MC_ARG(PCX86XMMREG, puSrc2, 3); 4455 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT(); 4456 IEM_MC_PREPARE_SSE_USAGE(); 4457 IEM_MC_FETCH_EFLAGS(fEFlags); 4458 IEM_MC_REF_MXCSR(pfMxcsr); 4459 IEM_MC_REF_XREG_XMM_CONST(puSrc1, IEM_GET_MODRM_REG(pVCpu, bRm)); 4460 IEM_MC_REF_XREG_XMM_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm)); 4461 IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_ucomiss_u128, pfMxcsr, pEFlags, puSrc1, puSrc2); 4462 IEM_MC_IF_MXCSR_XCPT_PENDING() 4463 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT(); 4464 IEM_MC_ELSE() 4465 IEM_MC_STORE_EFLAGS(fEFlags); 4466 IEM_MC_ENDIF(); 4467 4468 IEM_MC_ADVANCE_RIP(); 4469 IEM_MC_END(); 4470 } 4471 else 4472 { 4473 /* 4474 * Register, memory. 4475 */ 4476 IEM_MC_BEGIN(4, 3); 4477 IEM_MC_LOCAL(uint32_t, fEFlags); 4478 IEM_MC_ARG(uint32_t *, pfMxcsr, 0); 4479 IEM_MC_ARG_LOCAL_REF(uint32_t *, pEFlags, fEFlags, 1); 4480 IEM_MC_ARG(PCX86XMMREG, puSrc1, 2); 4481 IEM_MC_LOCAL(X86XMMREG, uSrc2); 4482 IEM_MC_ARG_LOCAL_REF(PCX86XMMREG, puSrc2, uSrc2, 3); 4483 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); 4484 4485 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); 4486 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 4487 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT(); 4488 IEM_MC_FETCH_MEM_XMM_U32(uSrc2, 0 /*a_DWord*/, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); 4489 4490 IEM_MC_PREPARE_SSE_USAGE(); 4491 IEM_MC_REF_MXCSR(pfMxcsr); 4492 IEM_MC_REF_XREG_XMM_CONST(puSrc1, IEM_GET_MODRM_REG(pVCpu, bRm)); 4493 IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_ucomiss_u128, pfMxcsr, pEFlags, puSrc1, puSrc2); 4494 IEM_MC_IF_MXCSR_XCPT_PENDING() 4495 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT(); 4496 IEM_MC_ELSE() 4497 IEM_MC_STORE_EFLAGS(fEFlags); 4498 IEM_MC_ENDIF(); 4499 4500 IEM_MC_ADVANCE_RIP(); 4501 IEM_MC_END(); 4502 } 4503 return VINF_SUCCESS; 4504 } 4505 4506 4439 4507 /** Opcode 0x66 0x0f 0x2e - ucomisd Vsd, Wsd */ 4440 FNIEMOP_STUB(iemOp_ucomisd_Vsd_Wsd); // NEXT 4508 FNIEMOP_DEF(iemOp_ucomisd_Vsd_Wsd) 4509 { 4510 IEMOP_MNEMONIC2(RM, UCOMISD, ucomisd, Vsd, Wsd, DISOPTYPE_HARMLESS | DISOPTYPE_SSE, IEMOPHINT_IGNORES_OP_SIZES); 4511 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); 4512 if (IEM_IS_MODRM_REG_MODE(bRm)) 4513 { 4514 /* 4515 * Register, register. 4516 */ 4517 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 4518 IEM_MC_BEGIN(4, 1); 4519 IEM_MC_LOCAL(uint32_t, fEFlags); 4520 IEM_MC_ARG(uint32_t *, pfMxcsr, 0); 4521 IEM_MC_ARG_LOCAL_REF(uint32_t *, pEFlags, fEFlags, 1); 4522 IEM_MC_ARG(PCX86XMMREG, puSrc1, 2); 4523 IEM_MC_ARG(PCX86XMMREG, puSrc2, 3); 4524 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT(); 4525 IEM_MC_PREPARE_SSE_USAGE(); 4526 IEM_MC_FETCH_EFLAGS(fEFlags); 4527 IEM_MC_REF_MXCSR(pfMxcsr); 4528 IEM_MC_REF_XREG_XMM_CONST(puSrc1, IEM_GET_MODRM_REG(pVCpu, bRm)); 4529 IEM_MC_REF_XREG_XMM_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm)); 4530 IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_ucomisd_u128, pfMxcsr, pEFlags, puSrc1, puSrc2); 4531 IEM_MC_IF_MXCSR_XCPT_PENDING() 4532 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT(); 4533 IEM_MC_ELSE() 4534 IEM_MC_STORE_EFLAGS(fEFlags); 4535 IEM_MC_ENDIF(); 4536 4537 IEM_MC_ADVANCE_RIP(); 4538 IEM_MC_END(); 4539 } 4540 else 4541 { 4542 /* 4543 * Register, memory. 4544 */ 4545 IEM_MC_BEGIN(4, 3); 4546 IEM_MC_LOCAL(uint32_t, fEFlags); 4547 IEM_MC_ARG(uint32_t *, pfMxcsr, 0); 4548 IEM_MC_ARG_LOCAL_REF(uint32_t *, pEFlags, fEFlags, 1); 4549 IEM_MC_ARG(PCX86XMMREG, puSrc1, 2); 4550 IEM_MC_LOCAL(X86XMMREG, uSrc2); 4551 IEM_MC_ARG_LOCAL_REF(PCX86XMMREG, puSrc2, uSrc2, 3); 4552 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); 4553 4554 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); 4555 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 4556 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT(); 4557 IEM_MC_FETCH_MEM_XMM_U64(uSrc2, 0 /*a_QWord*/, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); 4558 4559 IEM_MC_PREPARE_SSE_USAGE(); 4560 IEM_MC_REF_MXCSR(pfMxcsr); 4561 IEM_MC_REF_XREG_XMM_CONST(puSrc1, IEM_GET_MODRM_REG(pVCpu, bRm)); 4562 IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_ucomisd_u128, pfMxcsr, pEFlags, puSrc1, puSrc2); 4563 IEM_MC_IF_MXCSR_XCPT_PENDING() 4564 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT(); 4565 IEM_MC_ELSE() 4566 IEM_MC_STORE_EFLAGS(fEFlags); 4567 IEM_MC_ENDIF(); 4568 4569 IEM_MC_ADVANCE_RIP(); 4570 IEM_MC_END(); 4571 } 4572 return VINF_SUCCESS; 4573 } 4574 4575 4441 4576 /* Opcode 0xf3 0x0f 0x2e - invalid */ 4442 4577 /* Opcode 0xf2 0x0f 0x2e - invalid */ 4443 4578 4579 4444 4580 /** Opcode 0x0f 0x2f - comiss Vss, Wss */ 4445 FNIEMOP_STUB(iemOp_comiss_Vss_Wss); 4581 FNIEMOP_DEF(iemOp_comiss_Vss_Wss) 4582 { 4583 IEMOP_MNEMONIC2(RM, COMISS, comiss, Vss, Wss, DISOPTYPE_HARMLESS | DISOPTYPE_SSE, IEMOPHINT_IGNORES_OP_SIZES); 4584 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); 4585 if (IEM_IS_MODRM_REG_MODE(bRm)) 4586 { 4587 /* 4588 * Register, register. 4589 */ 4590 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 4591 IEM_MC_BEGIN(4, 1); 4592 IEM_MC_LOCAL(uint32_t, fEFlags); 4593 IEM_MC_ARG(uint32_t *, pfMxcsr, 0); 4594 IEM_MC_ARG_LOCAL_REF(uint32_t *, pEFlags, fEFlags, 1); 4595 IEM_MC_ARG(PCX86XMMREG, puSrc1, 2); 4596 IEM_MC_ARG(PCX86XMMREG, puSrc2, 3); 4597 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT(); 4598 IEM_MC_PREPARE_SSE_USAGE(); 4599 IEM_MC_FETCH_EFLAGS(fEFlags); 4600 IEM_MC_REF_MXCSR(pfMxcsr); 4601 IEM_MC_REF_XREG_XMM_CONST(puSrc1, IEM_GET_MODRM_REG(pVCpu, bRm)); 4602 IEM_MC_REF_XREG_XMM_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm)); 4603 IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_comiss_u128, pfMxcsr, pEFlags, puSrc1, puSrc2); 4604 IEM_MC_IF_MXCSR_XCPT_PENDING() 4605 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT(); 4606 IEM_MC_ELSE() 4607 IEM_MC_STORE_EFLAGS(fEFlags); 4608 IEM_MC_ENDIF(); 4609 4610 IEM_MC_ADVANCE_RIP(); 4611 IEM_MC_END(); 4612 } 4613 else 4614 { 4615 /* 4616 * Register, memory. 4617 */ 4618 IEM_MC_BEGIN(4, 3); 4619 IEM_MC_LOCAL(uint32_t, fEFlags); 4620 IEM_MC_ARG(uint32_t *, pfMxcsr, 0); 4621 IEM_MC_ARG_LOCAL_REF(uint32_t *, pEFlags, fEFlags, 1); 4622 IEM_MC_ARG(PCX86XMMREG, puSrc1, 2); 4623 IEM_MC_LOCAL(X86XMMREG, uSrc2); 4624 IEM_MC_ARG_LOCAL_REF(PCX86XMMREG, puSrc2, uSrc2, 3); 4625 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); 4626 4627 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); 4628 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 4629 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT(); 4630 IEM_MC_FETCH_MEM_XMM_U32(uSrc2, 0 /*a_DWord*/, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); 4631 4632 IEM_MC_PREPARE_SSE_USAGE(); 4633 IEM_MC_REF_MXCSR(pfMxcsr); 4634 IEM_MC_REF_XREG_XMM_CONST(puSrc1, IEM_GET_MODRM_REG(pVCpu, bRm)); 4635 IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_comiss_u128, pfMxcsr, pEFlags, puSrc1, puSrc2); 4636 IEM_MC_IF_MXCSR_XCPT_PENDING() 4637 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT(); 4638 IEM_MC_ELSE() 4639 IEM_MC_STORE_EFLAGS(fEFlags); 4640 IEM_MC_ENDIF(); 4641 4642 IEM_MC_ADVANCE_RIP(); 4643 IEM_MC_END(); 4644 } 4645 return VINF_SUCCESS; 4646 } 4647 4648 4446 4649 /** Opcode 0x66 0x0f 0x2f - comisd Vsd, Wsd */ 4447 FNIEMOP_STUB(iemOp_comisd_Vsd_Wsd); 4650 FNIEMOP_DEF(iemOp_comisd_Vsd_Wsd) 4651 { 4652 IEMOP_MNEMONIC2(RM, COMISD, comisd, Vsd, Wsd, DISOPTYPE_HARMLESS | DISOPTYPE_SSE, IEMOPHINT_IGNORES_OP_SIZES); 4653 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); 4654 if (IEM_IS_MODRM_REG_MODE(bRm)) 4655 { 4656 /* 4657 * Register, register. 4658 */ 4659 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 4660 IEM_MC_BEGIN(4, 1); 4661 IEM_MC_LOCAL(uint32_t, fEFlags); 4662 IEM_MC_ARG(uint32_t *, pfMxcsr, 0); 4663 IEM_MC_ARG_LOCAL_REF(uint32_t *, pEFlags, fEFlags, 1); 4664 IEM_MC_ARG(PCX86XMMREG, puSrc1, 2); 4665 IEM_MC_ARG(PCX86XMMREG, puSrc2, 3); 4666 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT(); 4667 IEM_MC_PREPARE_SSE_USAGE(); 4668 IEM_MC_FETCH_EFLAGS(fEFlags); 4669 IEM_MC_REF_MXCSR(pfMxcsr); 4670 IEM_MC_REF_XREG_XMM_CONST(puSrc1, IEM_GET_MODRM_REG(pVCpu, bRm)); 4671 IEM_MC_REF_XREG_XMM_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm)); 4672 IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_comisd_u128, pfMxcsr, pEFlags, puSrc1, puSrc2); 4673 IEM_MC_IF_MXCSR_XCPT_PENDING() 4674 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT(); 4675 IEM_MC_ELSE() 4676 IEM_MC_STORE_EFLAGS(fEFlags); 4677 IEM_MC_ENDIF(); 4678 4679 IEM_MC_ADVANCE_RIP(); 4680 IEM_MC_END(); 4681 } 4682 else 4683 { 4684 /* 4685 * Register, memory. 4686 */ 4687 IEM_MC_BEGIN(4, 3); 4688 IEM_MC_LOCAL(uint32_t, fEFlags); 4689 IEM_MC_ARG(uint32_t *, pfMxcsr, 0); 4690 IEM_MC_ARG_LOCAL_REF(uint32_t *, pEFlags, fEFlags, 1); 4691 IEM_MC_ARG(PCX86XMMREG, puSrc1, 2); 4692 IEM_MC_LOCAL(X86XMMREG, uSrc2); 4693 IEM_MC_ARG_LOCAL_REF(PCX86XMMREG, puSrc2, uSrc2, 3); 4694 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); 4695 4696 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); 4697 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 4698 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT(); 4699 IEM_MC_FETCH_MEM_XMM_U64(uSrc2, 0 /*a_QWord*/, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); 4700 4701 IEM_MC_PREPARE_SSE_USAGE(); 4702 IEM_MC_REF_MXCSR(pfMxcsr); 4703 IEM_MC_REF_XREG_XMM_CONST(puSrc1, IEM_GET_MODRM_REG(pVCpu, bRm)); 4704 IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_comisd_u128, pfMxcsr, pEFlags, puSrc1, puSrc2); 4705 IEM_MC_IF_MXCSR_XCPT_PENDING() 4706 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT(); 4707 IEM_MC_ELSE() 4708 IEM_MC_STORE_EFLAGS(fEFlags); 4709 IEM_MC_ENDIF(); 4710 4711 IEM_MC_ADVANCE_RIP(); 4712 IEM_MC_END(); 4713 } 4714 return VINF_SUCCESS; 4715 } 4716 4717 4448 4718 /* Opcode 0xf3 0x0f 0x2f - invalid */ 4449 4719 /* Opcode 0xf2 0x0f 0x2f - invalid */ -
trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsVexMap1.cpp.h
r96713 r96748 2302 2302 FNIEMOP_STUB(iemOp_vcvtsd2si_Gy_Wsd); 2303 2303 2304 2304 2305 /** Opcode VEX.0F 0x2e - vucomiss Vss, Wss */ 2305 FNIEMOP_STUB(iemOp_vucomiss_Vss_Wss); 2306 FNIEMOP_DEF(iemOp_vucomiss_Vss_Wss) 2307 { 2308 IEMOP_MNEMONIC2(RM, VUCOMISS, vucomiss, Vss, Wss, DISOPTYPE_HARMLESS | DISOPTYPE_SSE, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO); 2309 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); 2310 if (IEM_IS_MODRM_REG_MODE(bRm)) 2311 { 2312 /* 2313 * Register, register. 2314 */ 2315 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV(); 2316 IEM_MC_BEGIN(4, 1); 2317 IEM_MC_LOCAL(uint32_t, fEFlags); 2318 IEM_MC_ARG(uint32_t *, pfMxcsr, 0); 2319 IEM_MC_ARG_LOCAL_REF(uint32_t *, pEFlags, fEFlags, 1); 2320 IEM_MC_ARG(PCX86XMMREG, puSrc1, 2); 2321 IEM_MC_ARG(PCX86XMMREG, puSrc2, 3); 2322 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT(); 2323 IEM_MC_PREPARE_AVX_USAGE(); 2324 IEM_MC_FETCH_EFLAGS(fEFlags); 2325 IEM_MC_REF_MXCSR(pfMxcsr); 2326 IEM_MC_REF_XREG_XMM_CONST(puSrc1, IEM_GET_MODRM_REG(pVCpu, bRm)); 2327 IEM_MC_REF_XREG_XMM_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm)); 2328 IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_vucomiss_u128, pfMxcsr, pEFlags, puSrc1, puSrc2); 2329 IEM_MC_IF_MXCSR_XCPT_PENDING() 2330 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT(); 2331 IEM_MC_ELSE() 2332 IEM_MC_STORE_EFLAGS(fEFlags); 2333 IEM_MC_ENDIF(); 2334 2335 IEM_MC_ADVANCE_RIP(); 2336 IEM_MC_END(); 2337 } 2338 else 2339 { 2340 /* 2341 * Register, memory. 2342 */ 2343 IEM_MC_BEGIN(4, 3); 2344 IEM_MC_LOCAL(uint32_t, fEFlags); 2345 IEM_MC_ARG(uint32_t *, pfMxcsr, 0); 2346 IEM_MC_ARG_LOCAL_REF(uint32_t *, pEFlags, fEFlags, 1); 2347 IEM_MC_ARG(PCX86XMMREG, puSrc1, 2); 2348 IEM_MC_LOCAL(X86XMMREG, uSrc2); 2349 IEM_MC_ARG_LOCAL_REF(PCX86XMMREG, puSrc2, uSrc2, 3); 2350 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); 2351 2352 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); 2353 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV(); 2354 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT(); 2355 IEM_MC_FETCH_MEM_XMM_U32(uSrc2, 0 /*a_DWord*/, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); 2356 2357 IEM_MC_PREPARE_AVX_USAGE(); 2358 IEM_MC_REF_MXCSR(pfMxcsr); 2359 IEM_MC_REF_XREG_XMM_CONST(puSrc1, IEM_GET_MODRM_REG(pVCpu, bRm)); 2360 IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_vucomiss_u128, pfMxcsr, pEFlags, puSrc1, puSrc2); 2361 IEM_MC_IF_MXCSR_XCPT_PENDING() 2362 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT(); 2363 IEM_MC_ELSE() 2364 IEM_MC_STORE_EFLAGS(fEFlags); 2365 IEM_MC_ENDIF(); 2366 2367 IEM_MC_ADVANCE_RIP(); 2368 IEM_MC_END(); 2369 } 2370 return VINF_SUCCESS; 2371 } 2372 2373 2306 2374 /** Opcode VEX.66.0F 0x2e - vucomisd Vsd, Wsd */ 2307 FNIEMOP_STUB(iemOp_vucomisd_Vsd_Wsd); 2375 FNIEMOP_DEF(iemOp_vucomisd_Vsd_Wsd) 2376 { 2377 IEMOP_MNEMONIC2(RM, VUCOMISD, vucomisd, Vsd, Wsd, DISOPTYPE_HARMLESS | DISOPTYPE_SSE, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO); 2378 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); 2379 if (IEM_IS_MODRM_REG_MODE(bRm)) 2380 { 2381 /* 2382 * Register, register. 2383 */ 2384 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV(); 2385 IEM_MC_BEGIN(4, 1); 2386 IEM_MC_LOCAL(uint32_t, fEFlags); 2387 IEM_MC_ARG(uint32_t *, pfMxcsr, 0); 2388 IEM_MC_ARG_LOCAL_REF(uint32_t *, pEFlags, fEFlags, 1); 2389 IEM_MC_ARG(PCX86XMMREG, puSrc1, 2); 2390 IEM_MC_ARG(PCX86XMMREG, puSrc2, 3); 2391 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT(); 2392 IEM_MC_PREPARE_AVX_USAGE(); 2393 IEM_MC_FETCH_EFLAGS(fEFlags); 2394 IEM_MC_REF_MXCSR(pfMxcsr); 2395 IEM_MC_REF_XREG_XMM_CONST(puSrc1, IEM_GET_MODRM_REG(pVCpu, bRm)); 2396 IEM_MC_REF_XREG_XMM_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm)); 2397 IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_vucomisd_u128, pfMxcsr, pEFlags, puSrc1, puSrc2); 2398 IEM_MC_IF_MXCSR_XCPT_PENDING() 2399 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT(); 2400 IEM_MC_ELSE() 2401 IEM_MC_STORE_EFLAGS(fEFlags); 2402 IEM_MC_ENDIF(); 2403 2404 IEM_MC_ADVANCE_RIP(); 2405 IEM_MC_END(); 2406 } 2407 else 2408 { 2409 /* 2410 * Register, memory. 2411 */ 2412 IEM_MC_BEGIN(4, 3); 2413 IEM_MC_LOCAL(uint32_t, fEFlags); 2414 IEM_MC_ARG(uint32_t *, pfMxcsr, 0); 2415 IEM_MC_ARG_LOCAL_REF(uint32_t *, pEFlags, fEFlags, 1); 2416 IEM_MC_ARG(PCX86XMMREG, puSrc1, 2); 2417 IEM_MC_LOCAL(X86XMMREG, uSrc2); 2418 IEM_MC_ARG_LOCAL_REF(PCX86XMMREG, puSrc2, uSrc2, 3); 2419 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); 2420 2421 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); 2422 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV(); 2423 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT(); 2424 IEM_MC_FETCH_MEM_XMM_U32(uSrc2, 0 /*a_DWord*/, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); 2425 2426 IEM_MC_PREPARE_AVX_USAGE(); 2427 IEM_MC_REF_MXCSR(pfMxcsr); 2428 IEM_MC_REF_XREG_XMM_CONST(puSrc1, IEM_GET_MODRM_REG(pVCpu, bRm)); 2429 IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_vucomisd_u128, pfMxcsr, pEFlags, puSrc1, puSrc2); 2430 IEM_MC_IF_MXCSR_XCPT_PENDING() 2431 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT(); 2432 IEM_MC_ELSE() 2433 IEM_MC_STORE_EFLAGS(fEFlags); 2434 IEM_MC_ENDIF(); 2435 2436 IEM_MC_ADVANCE_RIP(); 2437 IEM_MC_END(); 2438 } 2439 return VINF_SUCCESS; 2440 } 2441 2442 2308 2443 /* Opcode VEX.F3.0F 0x2e - invalid */ 2309 2444 /* Opcode VEX.F2.0F 0x2e - invalid */ 2310 2445 2311 2446 /** Opcode VEX.0F 0x2f - vcomiss Vss, Wss */ 2312 FNIEMOP_STUB(iemOp_vcomiss_Vss_Wss); 2447 FNIEMOP_DEF(iemOp_vcomiss_Vss_Wss) 2448 { 2449 IEMOP_MNEMONIC2(RM, VCOMISS, vcomiss, Vss, Wss, DISOPTYPE_HARMLESS | DISOPTYPE_SSE, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO); 2450 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); 2451 if (IEM_IS_MODRM_REG_MODE(bRm)) 2452 { 2453 /* 2454 * Register, register. 2455 */ 2456 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV(); 2457 IEM_MC_BEGIN(4, 1); 2458 IEM_MC_LOCAL(uint32_t, fEFlags); 2459 IEM_MC_ARG(uint32_t *, pfMxcsr, 0); 2460 IEM_MC_ARG_LOCAL_REF(uint32_t *, pEFlags, fEFlags, 1); 2461 IEM_MC_ARG(PCX86XMMREG, puSrc1, 2); 2462 IEM_MC_ARG(PCX86XMMREG, puSrc2, 3); 2463 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT(); 2464 IEM_MC_PREPARE_AVX_USAGE(); 2465 IEM_MC_FETCH_EFLAGS(fEFlags); 2466 IEM_MC_REF_MXCSR(pfMxcsr); 2467 IEM_MC_REF_XREG_XMM_CONST(puSrc1, IEM_GET_MODRM_REG(pVCpu, bRm)); 2468 IEM_MC_REF_XREG_XMM_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm)); 2469 IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_vcomiss_u128, pfMxcsr, pEFlags, puSrc1, puSrc2); 2470 IEM_MC_IF_MXCSR_XCPT_PENDING() 2471 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT(); 2472 IEM_MC_ELSE() 2473 IEM_MC_STORE_EFLAGS(fEFlags); 2474 IEM_MC_ENDIF(); 2475 2476 IEM_MC_ADVANCE_RIP(); 2477 IEM_MC_END(); 2478 } 2479 else 2480 { 2481 /* 2482 * Register, memory. 2483 */ 2484 IEM_MC_BEGIN(4, 3); 2485 IEM_MC_LOCAL(uint32_t, fEFlags); 2486 IEM_MC_ARG(uint32_t *, pfMxcsr, 0); 2487 IEM_MC_ARG_LOCAL_REF(uint32_t *, pEFlags, fEFlags, 1); 2488 IEM_MC_ARG(PCX86XMMREG, puSrc1, 2); 2489 IEM_MC_LOCAL(X86XMMREG, uSrc2); 2490 IEM_MC_ARG_LOCAL_REF(PCX86XMMREG, puSrc2, uSrc2, 3); 2491 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); 2492 2493 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); 2494 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV(); 2495 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT(); 2496 IEM_MC_FETCH_MEM_XMM_U32(uSrc2, 0 /*a_DWord*/, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); 2497 2498 IEM_MC_PREPARE_AVX_USAGE(); 2499 IEM_MC_REF_MXCSR(pfMxcsr); 2500 IEM_MC_REF_XREG_XMM_CONST(puSrc1, IEM_GET_MODRM_REG(pVCpu, bRm)); 2501 IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_vcomiss_u128, pfMxcsr, pEFlags, puSrc1, puSrc2); 2502 IEM_MC_IF_MXCSR_XCPT_PENDING() 2503 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT(); 2504 IEM_MC_ELSE() 2505 IEM_MC_STORE_EFLAGS(fEFlags); 2506 IEM_MC_ENDIF(); 2507 2508 IEM_MC_ADVANCE_RIP(); 2509 IEM_MC_END(); 2510 } 2511 return VINF_SUCCESS; 2512 } 2513 2514 2313 2515 /** Opcode VEX.66.0F 0x2f - vcomisd Vsd, Wsd */ 2314 FNIEMOP_STUB(iemOp_vcomisd_Vsd_Wsd); 2516 FNIEMOP_DEF(iemOp_vcomisd_Vsd_Wsd) 2517 { 2518 IEMOP_MNEMONIC2(RM, VCOMISD, vcomisd, Vsd, Wsd, DISOPTYPE_HARMLESS | DISOPTYPE_SSE, IEMOPHINT_IGNORES_OP_SIZES | IEMOPHINT_VEX_L_ZERO); 2519 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); 2520 if (IEM_IS_MODRM_REG_MODE(bRm)) 2521 { 2522 /* 2523 * Register, register. 2524 */ 2525 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV(); 2526 IEM_MC_BEGIN(4, 1); 2527 IEM_MC_LOCAL(uint32_t, fEFlags); 2528 IEM_MC_ARG(uint32_t *, pfMxcsr, 0); 2529 IEM_MC_ARG_LOCAL_REF(uint32_t *, pEFlags, fEFlags, 1); 2530 IEM_MC_ARG(PCX86XMMREG, puSrc1, 2); 2531 IEM_MC_ARG(PCX86XMMREG, puSrc2, 3); 2532 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT(); 2533 IEM_MC_PREPARE_AVX_USAGE(); 2534 IEM_MC_FETCH_EFLAGS(fEFlags); 2535 IEM_MC_REF_MXCSR(pfMxcsr); 2536 IEM_MC_REF_XREG_XMM_CONST(puSrc1, IEM_GET_MODRM_REG(pVCpu, bRm)); 2537 IEM_MC_REF_XREG_XMM_CONST(puSrc2, IEM_GET_MODRM_RM(pVCpu, bRm)); 2538 IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_vcomisd_u128, pfMxcsr, pEFlags, puSrc1, puSrc2); 2539 IEM_MC_IF_MXCSR_XCPT_PENDING() 2540 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT(); 2541 IEM_MC_ELSE() 2542 IEM_MC_STORE_EFLAGS(fEFlags); 2543 IEM_MC_ENDIF(); 2544 2545 IEM_MC_ADVANCE_RIP(); 2546 IEM_MC_END(); 2547 } 2548 else 2549 { 2550 /* 2551 * Register, memory. 2552 */ 2553 IEM_MC_BEGIN(4, 3); 2554 IEM_MC_LOCAL(uint32_t, fEFlags); 2555 IEM_MC_ARG(uint32_t *, pfMxcsr, 0); 2556 IEM_MC_ARG_LOCAL_REF(uint32_t *, pEFlags, fEFlags, 1); 2557 IEM_MC_ARG(PCX86XMMREG, puSrc1, 2); 2558 IEM_MC_LOCAL(X86XMMREG, uSrc2); 2559 IEM_MC_ARG_LOCAL_REF(PCX86XMMREG, puSrc2, uSrc2, 3); 2560 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); 2561 2562 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); 2563 IEMOP_HLP_DONE_VEX_DECODING_L0_AND_NO_VVVV(); 2564 IEM_MC_MAYBE_RAISE_AVX_RELATED_XCPT(); 2565 IEM_MC_FETCH_MEM_XMM_U32(uSrc2, 0 /*a_DWord*/, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); 2566 2567 IEM_MC_PREPARE_AVX_USAGE(); 2568 IEM_MC_REF_MXCSR(pfMxcsr); 2569 IEM_MC_REF_XREG_XMM_CONST(puSrc1, IEM_GET_MODRM_REG(pVCpu, bRm)); 2570 IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_vcomisd_u128, pfMxcsr, pEFlags, puSrc1, puSrc2); 2571 IEM_MC_IF_MXCSR_XCPT_PENDING() 2572 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT(); 2573 IEM_MC_ELSE() 2574 IEM_MC_STORE_EFLAGS(fEFlags); 2575 IEM_MC_ENDIF(); 2576 2577 IEM_MC_ADVANCE_RIP(); 2578 IEM_MC_END(); 2579 } 2580 return VINF_SUCCESS; 2581 } 2582 2583 2315 2584 /* Opcode VEX.F3.0F 0x2f - invalid */ 2316 2585 /* Opcode VEX.F2.0F 0x2f - invalid */
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