Changeset 9675 in vbox for trunk/src/VBox
- Timestamp:
- Jun 13, 2008 9:49:54 AM (17 years ago)
- Location:
- trunk/src/VBox
- Files:
-
- 12 edited
-
Disassembler/Disasm.cpp (modified) (3 diffs)
-
Disassembler/DisasmCore.cpp (modified) (11 diffs)
-
Disassembler/DisasmFormatYasm.cpp (modified) (5 diffs)
-
Disassembler/DisasmInternal.h (modified) (1 diff)
-
Disassembler/DisasmReg.cpp (modified) (7 diffs)
-
VMM/DBGFDisas.cpp (modified) (1 diff)
-
VMM/EM.cpp (modified) (7 diffs)
-
VMM/PATM/CSAM.cpp (modified) (3 diffs)
-
VMM/PATM/PATM.cpp (modified) (6 diffs)
-
VMM/VMMAll/CPUMAllRegs.cpp (modified) (1 diff)
-
VMM/VMMAll/EMAll.cpp (modified) (3 diffs)
-
VMM/VMMAll/SELMAll.cpp (modified) (3 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/Disassembler/Disasm.cpp
r8936 r9675 123 123 124 124 //reset instruction settings 125 pCpu->prefix = PREFIX_NONE;126 pCpu-> prefix_seg = 0;127 pCpu->ModRM.u = 0;128 pCpu->SIB.u = 0;129 pCpu->lastprefix = 0;125 pCpu->prefix = PREFIX_NONE; 126 pCpu->enmPrefixSeg = DIS_SELREG_DS; 127 pCpu->ModRM.u = 0; 128 pCpu->SIB.u = 0; 129 pCpu->lastprefix = 0; 130 130 pCpu->param1.parval = 0; 131 131 pCpu->param2.parval = 0; … … 134 134 pCpu->param2.szParam[0] = 0; 135 135 pCpu->param3.szParam[0] = 0; 136 pCpu->param1.size = 0;137 pCpu->param2.size = 0;138 pCpu->param3.size = 0;139 pCpu->param1.flags = 0;140 pCpu->param2.flags = 0;141 pCpu->param3.flags = 0;142 pCpu->uFilter = uFilter;136 pCpu->param1.size = 0; 137 pCpu->param2.size = 0; 138 pCpu->param3.size = 0; 139 pCpu->param1.flags = 0; 140 pCpu->param2.flags = 0; 141 pCpu->param3.flags = 0; 142 pCpu->uFilter = uFilter; 143 143 pCpu->pfnDisasmFnTable = pfnFullDisasm; 144 144 … … 192 192 // segment override prefix byte 193 193 case OP_SEG: 194 pCpu-> prefix_seg = paOneByteMap[codebyte].param1 - OP_PARM_REG_SEG_START;194 pCpu->enmPrefixSeg = (DIS_SELREG)(paOneByteMap[codebyte].param1 - OP_PARM_REG_SEG_START); 195 195 /* Segment prefixes for CS, DS, ES and SS are ignored in long mode. */ 196 196 if ( pCpu->mode != CPUMODE_64BIT 197 || pCpu-> prefix_seg >= OP_PARM_REG_FS)197 || pCpu->enmPrefixSeg >= OP_PARM_REG_FS) 198 198 { 199 199 pCpu->prefix |= PREFIX_SEG; -
trunk/src/VBox/Disassembler/DisasmCore.cpp
r9131 r9675 173 173 * Reset instruction settings 174 174 */ 175 pCpu->prefix = PREFIX_NONE;176 pCpu-> prefix_seg = 0;177 pCpu->lastprefix = 0;178 pCpu->ModRM.u = 0;179 pCpu->SIB.u = 0;175 pCpu->prefix = PREFIX_NONE; 176 pCpu->enmPrefixSeg = DIS_SELREG_DS; 177 pCpu->lastprefix = 0; 178 pCpu->ModRM.u = 0; 179 pCpu->SIB.u = 0; 180 180 pCpu->param1.parval = 0; 181 181 pCpu->param2.parval = 0; … … 184 184 pCpu->param2.szParam[0] = '\0'; 185 185 pCpu->param3.szParam[0] = '\0'; 186 pCpu->param1.flags = 0;187 pCpu->param2.flags = 0;188 pCpu->param3.flags = 0;189 pCpu->param1.size = 0;190 pCpu->param2.size = 0;191 pCpu->param3.size = 0;192 pCpu->pfnReadBytes = 0;193 pCpu->uFilter = OPTYPE_ALL;186 pCpu->param1.flags = 0; 187 pCpu->param2.flags = 0; 188 pCpu->param3.flags = 0; 189 pCpu->param1.size = 0; 190 pCpu->param2.size = 0; 191 pCpu->param3.size = 0; 192 pCpu->pfnReadBytes = 0; 193 pCpu->uFilter = OPTYPE_ALL; 194 194 pCpu->pfnDisasmFnTable = pfnFullDisasm; 195 195 … … 217 217 * Reset instruction settings 218 218 */ 219 pCpu->prefix = PREFIX_NONE;220 pCpu-> prefix_seg = 0;221 pCpu->lastprefix = 0;222 pCpu->mode = enmCpuMode;223 pCpu->ModRM.u = 0;224 pCpu->SIB.u = 0;225 pCpu->param1.parval = 0;226 pCpu->param2.parval = 0;227 pCpu->param3.parval = 0;219 pCpu->prefix = PREFIX_NONE; 220 pCpu->enmPrefixSeg = DIS_SELREG_DS; 221 pCpu->lastprefix = 0; 222 pCpu->mode = enmCpuMode; 223 pCpu->ModRM.u = 0; 224 pCpu->SIB.u = 0; 225 pCpu->param1.parval = 0; 226 pCpu->param2.parval = 0; 227 pCpu->param3.parval = 0; 228 228 pCpu->param1.szParam[0] = '\0'; 229 229 pCpu->param2.szParam[0] = '\0'; … … 298 298 // segment override prefix byte 299 299 case OP_SEG: 300 pCpu-> prefix_seg = paOneByteMap[codebyte].param1 - OP_PARM_REG_SEG_START;300 pCpu->enmPrefixSeg = (DIS_SELREG)(paOneByteMap[codebyte].param1 - OP_PARM_REG_SEG_START); 301 301 /* Segment prefixes for CS, DS, ES and SS are ignored in long mode. */ 302 302 if ( pCpu->mode != CPUMODE_64BIT 303 || pCpu-> prefix_seg >= OP_PARM_REG_FS)303 || pCpu->enmPrefixSeg >= OP_PARM_REG_FS) 304 304 { 305 305 pCpu->prefix |= PREFIX_SEG; … … 1527 1527 { 1528 1528 /* Segment ES..GS registers. */ 1529 pParam->base.reg_seg = pParam->param - OP_PARM_REG_SEG_START;1529 pParam->base.reg_seg = (DIS_SELREG)(pParam->param - OP_PARM_REG_SEG_START); 1530 1530 pParam->flags |= USE_REG_SEG; 1531 1531 pParam->size = 2; … … 2121 2121 static const int IndexModRMReg16[4] = { USE_REG_SI, USE_REG_DI, USE_REG_SI, USE_REG_DI}; 2122 2122 //***************************************************************************** 2123 void disasmModRMReg(PDISCPUSTATE pCpu, PCOPCODE pOp, intidx, POP_PARAMETER pParam, int fRegAddr)2123 void disasmModRMReg(PDISCPUSTATE pCpu, PCOPCODE pOp, unsigned idx, POP_PARAMETER pParam, int fRegAddr) 2124 2124 { 2125 2125 int subtype, type, mod; … … 2155 2155 case OP_PARM_b: 2156 2156 #if !defined(DIS_CORE_ONLY) && defined(LOG_ENABLED) 2157 if (idx > (int)RT_ELEMENTS(szModRMReg8))2157 if (idx > RT_ELEMENTS(szModRMReg8)) 2158 2158 disasmAddString(pParam->szParam, szModRMReg8_64[idx]); 2159 2159 else … … 2194 2194 //***************************************************************************** 2195 2195 //***************************************************************************** 2196 void disasmModRMReg16(PDISCPUSTATE pCpu, PCOPCODE pOp, intidx, POP_PARAMETER pParam)2196 void disasmModRMReg16(PDISCPUSTATE pCpu, PCOPCODE pOp, unsigned idx, POP_PARAMETER pParam) 2197 2197 { 2198 2198 disasmAddString(pParam->szParam, szModRMReg1616[idx]); … … 2207 2207 //***************************************************************************** 2208 2208 //***************************************************************************** 2209 void disasmModRMSReg(PDISCPUSTATE pCpu, PCOPCODE pOp, intidx, POP_PARAMETER pParam)2209 void disasmModRMSReg(PDISCPUSTATE pCpu, PCOPCODE pOp, unsigned idx, POP_PARAMETER pParam) 2210 2210 { 2211 2211 #if 0 //def DEBUG_Sander 2212 AssertMsg(idx < (int)ELEMENTS(szModRMSegReg), ("idx=%d\n", idx));2212 AssertMsg(idx < ELEMENTS(szModRMSegReg), ("idx=%d\n", idx)); 2213 2213 #endif 2214 2214 #ifdef IN_RING3 2215 if (idx >= (int)ELEMENTS(szModRMSegReg))2215 if (idx >= ELEMENTS(szModRMSegReg)) 2216 2216 { 2217 2217 Log(("disasmModRMSReg %d failed!!\n", idx)); … … 2220 2220 #endif 2221 2221 2222 idx = RT_MIN(idx, (int)ELEMENTS(szModRMSegReg)-1);2222 idx = RT_MIN(idx, ELEMENTS(szModRMSegReg)-1); 2223 2223 disasmAddString(pParam->szParam, szModRMSegReg[idx]); 2224 2224 pParam->flags |= USE_REG_SEG; 2225 pParam->base.reg_seg = idx;2225 pParam->base.reg_seg = (DIS_SELREG)idx; 2226 2226 } 2227 2227 //***************************************************************************** … … 2309 2309 } 2310 2310 if (pCpu->prefix & PREFIX_SEG) 2311 disasmAddStringF(pParam->szParam, sizeof(pParam->szParam), "%s:", szModRMSegReg[pCpu-> prefix_seg]);2311 disasmAddStringF(pParam->szParam, sizeof(pParam->szParam), "%s:", szModRMSegReg[pCpu->enmPrefixSeg]); 2312 2312 } 2313 2313 #ifndef IN_GC -
trunk/src/VBox/Disassembler/DisasmFormatYasm.cpp
r9342 r9675 617 617 do { \ 618 618 if (pCpu->prefix & PREFIX_SEG) \ 619 PUT_STR(s_szSegPrefix[pCpu-> prefix_seg], 3); \619 PUT_STR(s_szSegPrefix[pCpu->enmPrefixSeg], 3); \ 620 620 } while (0) 621 621 … … 629 629 && !DIS_IS_EFFECTIVE_ADDR(pCpu->param3.flags)) 630 630 { 631 PUT_STR(s_szSegPrefix[pCpu-> prefix_seg], 2);631 PUT_STR(s_szSegPrefix[pCpu->enmPrefixSeg], 2); 632 632 PUT_C(' '); 633 633 } … … 899 899 if (pfnGetSymbol) 900 900 { 901 int rc = pfnGetSymbol(pCpu, DIS_FMT_SEL_FROM_REG( USE_REG_CS), uTrgAddr, szSymbol, sizeof(szSymbol), &off, pvUser);901 int rc = pfnGetSymbol(pCpu, DIS_FMT_SEL_FROM_REG(DIS_SELREG_CS), uTrgAddr, szSymbol, sizeof(szSymbol), &off, pvUser); 902 902 if (RT_SUCCESS(rc)) 903 903 { … … 950 950 PUT_NUM_16(pParam->parval); 951 951 if (pfnGetSymbol) 952 rc = pfnGetSymbol(pCpu, DIS_FMT_SEL_FROM_REG( USE_REG_CS), (uint16_t)pParam->parval, szSymbol, sizeof(szSymbol), &off, pvUser);952 rc = pfnGetSymbol(pCpu, DIS_FMT_SEL_FROM_REG(DIS_SELREG_CS), (uint16_t)pParam->parval, szSymbol, sizeof(szSymbol), &off, pvUser); 953 953 break; 954 954 case USE_DISPLACEMENT32: 955 955 PUT_NUM_32(pParam->parval); 956 956 if (pfnGetSymbol) 957 rc = pfnGetSymbol(pCpu, DIS_FMT_SEL_FROM_REG( USE_REG_CS), (uint32_t)pParam->parval, szSymbol, sizeof(szSymbol), &off, pvUser);957 rc = pfnGetSymbol(pCpu, DIS_FMT_SEL_FROM_REG(DIS_SELREG_CS), (uint32_t)pParam->parval, szSymbol, sizeof(szSymbol), &off, pvUser); 958 958 break; 959 959 case USE_DISPLACEMENT64: 960 960 PUT_NUM_64(pParam->parval); 961 961 if (pfnGetSymbol) 962 rc = pfnGetSymbol(pCpu, DIS_FMT_SEL_FROM_REG( USE_REG_CS), (uint64_t)pParam->parval, szSymbol, sizeof(szSymbol), &off, pvUser);962 rc = pfnGetSymbol(pCpu, DIS_FMT_SEL_FROM_REG(DIS_SELREG_CS), (uint64_t)pParam->parval, szSymbol, sizeof(szSymbol), &off, pvUser); 963 963 break; 964 964 default: … … 1014 1014 PUT_NUM_16(pParam->disp16); 1015 1015 if (pfnGetSymbol) 1016 rc = pfnGetSymbol(pCpu, DIS_FMT_SEL_FROM_REG( USE_REG_CS), (uint16_t)pParam->disp16, szSymbol, sizeof(szSymbol), &off, pvUser);1016 rc = pfnGetSymbol(pCpu, DIS_FMT_SEL_FROM_REG(DIS_SELREG_CS), (uint16_t)pParam->disp16, szSymbol, sizeof(szSymbol), &off, pvUser); 1017 1017 break; 1018 1018 case USE_DISPLACEMENT32: 1019 1019 PUT_NUM_32(pParam->disp32); 1020 1020 if (pfnGetSymbol) 1021 rc = pfnGetSymbol(pCpu, DIS_FMT_SEL_FROM_REG( USE_REG_CS), (uint32_t)pParam->disp32, szSymbol, sizeof(szSymbol), &off, pvUser);1021 rc = pfnGetSymbol(pCpu, DIS_FMT_SEL_FROM_REG(DIS_SELREG_CS), (uint32_t)pParam->disp32, szSymbol, sizeof(szSymbol), &off, pvUser); 1022 1022 break; 1023 1023 case USE_DISPLACEMENT64: 1024 1024 PUT_NUM_64(pParam->disp64); 1025 1025 if (pfnGetSymbol) 1026 rc = pfnGetSymbol(pCpu, DIS_FMT_SEL_FROM_REG( USE_REG_CS), (uint64_t)pParam->disp64, szSymbol, sizeof(szSymbol), &off, pvUser);1026 rc = pfnGetSymbol(pCpu, DIS_FMT_SEL_FROM_REG(DIS_SELREG_CS), (uint64_t)pParam->disp64, szSymbol, sizeof(szSymbol), &off, pvUser); 1027 1027 break; 1028 1028 default: -
trunk/src/VBox/Disassembler/DisasmInternal.h
r9266 r9675 149 149 void disasmSprintf(char *pszOutput, RTUINTPTR pu8Instruction, PDISCPUSTATE pCpu, POP_PARAMETER pParam1, POP_PARAMETER pParam2, POP_PARAMETER pParam3 = NULL); 150 150 void disasmGetPtrString(PDISCPUSTATE pCpu, PCOPCODE pOp, POP_PARAMETER pParam); 151 void disasmModRMReg(PDISCPUSTATE pCpu, PCOPCODE pOp, intidx, POP_PARAMETER pParam, int fRegAddr);152 void disasmModRMReg16(PDISCPUSTATE pCpu, PCOPCODE pOp, intidx, POP_PARAMETER pParam);153 void disasmModRMSReg(PDISCPUSTATE pCpu, PCOPCODE pOp, intidx, POP_PARAMETER pParam);151 void disasmModRMReg(PDISCPUSTATE pCpu, PCOPCODE pOp, unsigned idx, POP_PARAMETER pParam, int fRegAddr); 152 void disasmModRMReg16(PDISCPUSTATE pCpu, PCOPCODE pOp, unsigned idx, POP_PARAMETER pParam); 153 void disasmModRMSReg(PDISCPUSTATE pCpu, PCOPCODE pOp, unsigned idx, POP_PARAMETER pParam); 154 154 void disasmPrintAbs32(POP_PARAMETER pParam); 155 155 void disasmPrintDisp32(POP_PARAMETER pParam); -
trunk/src/VBox/Disassembler/DisasmReg.cpp
r9132 r9675 157 157 static const unsigned g_aRegSegIndex[] = 158 158 { 159 RT_OFFSETOF(CPUMCTXCORE, es), /* USE_REG_ES */160 RT_OFFSETOF(CPUMCTXCORE, cs), /* USE_REG_CS */161 RT_OFFSETOF(CPUMCTXCORE, ss), /* USE_REG_SS */162 RT_OFFSETOF(CPUMCTXCORE, ds), /* USE_REG_DS */163 RT_OFFSETOF(CPUMCTXCORE, fs), /* USE_REG_FS */164 RT_OFFSETOF(CPUMCTXCORE, gs) /* USE_REG_GS */159 RT_OFFSETOF(CPUMCTXCORE, es), /* DIS_SELREG_ES */ 160 RT_OFFSETOF(CPUMCTXCORE, cs), /* DIS_SELREG_CS */ 161 RT_OFFSETOF(CPUMCTXCORE, ss), /* DIS_SELREG_SS */ 162 RT_OFFSETOF(CPUMCTXCORE, ds), /* DIS_SELREG_DS */ 163 RT_OFFSETOF(CPUMCTXCORE, fs), /* DIS_SELREG_FS */ 164 RT_OFFSETOF(CPUMCTXCORE, gs) /* DIS_SELREG_GS */ 165 165 }; 166 166 167 167 static const unsigned g_aRegHidSegIndex[] = 168 168 { 169 RT_OFFSETOF(CPUMCTXCORE, esHid), /* USE_REG_ES */170 RT_OFFSETOF(CPUMCTXCORE, csHid), /* USE_REG_CS */171 RT_OFFSETOF(CPUMCTXCORE, ssHid), /* USE_REG_SS */172 RT_OFFSETOF(CPUMCTXCORE, dsHid), /* USE_REG_DS */173 RT_OFFSETOF(CPUMCTXCORE, fsHid), /* USE_REG_FS */174 RT_OFFSETOF(CPUMCTXCORE, gsHid) /* USE_REG_GS */169 RT_OFFSETOF(CPUMCTXCORE, esHid), /* DIS_SELREG_ES */ 170 RT_OFFSETOF(CPUMCTXCORE, csHid), /* DIS_SELREG_CS */ 171 RT_OFFSETOF(CPUMCTXCORE, ssHid), /* DIS_SELREG_SS */ 172 RT_OFFSETOF(CPUMCTXCORE, dsHid), /* DIS_SELREG_DS */ 173 RT_OFFSETOF(CPUMCTXCORE, fsHid), /* DIS_SELREG_FS */ 174 RT_OFFSETOF(CPUMCTXCORE, gsHid) /* DIS_SELREG_GS */ 175 175 }; 176 176 … … 223 223 //***************************************************************************** 224 224 //***************************************************************************** 225 DISDECL( int) DISDetectSegReg(PDISCPUSTATE pCpu, POP_PARAMETER pParam)225 DISDECL(DIS_SELREG) DISDetectSegReg(PDISCPUSTATE pCpu, POP_PARAMETER pParam) 226 226 { 227 227 if (pCpu->prefix & PREFIX_SEG) 228 228 { 229 229 /* Use specified SEG: prefix. */ 230 return pCpu-> prefix_seg;230 return pCpu->enmPrefixSeg; 231 231 } 232 232 else … … 240 240 AssertCompile(USE_REG_EBP == USE_REG_BP); 241 241 if (pParam->base.reg_gen == USE_REG_ESP || pParam->base.reg_gen == USE_REG_EBP) 242 return USE_REG_SS;242 return DIS_SELREG_SS; 243 243 } 244 244 /* Default is use DS: for data access. */ 245 return USE_REG_DS;245 return DIS_SELREG_DS; 246 246 } 247 247 } … … 251 251 { 252 252 Assert(pCpu->prefix & PREFIX_SEG); 253 switch(pCpu-> prefix_seg)253 switch(pCpu->enmPrefixSeg) 254 254 { 255 case USE_REG_ES:255 case DIS_SELREG_ES: 256 256 return 0x26; 257 case USE_REG_CS:257 case DIS_SELREG_CS: 258 258 return 0x2E; 259 case USE_REG_SS:259 case DIS_SELREG_SS: 260 260 return 0x36; 261 case USE_REG_DS:261 case DIS_SELREG_DS: 262 262 return 0x3E; 263 case USE_REG_FS:263 case DIS_SELREG_FS: 264 264 return 0x64; 265 case USE_REG_GS:265 case DIS_SELREG_GS: 266 266 return 0x65; 267 267 default: … … 372 372 * 373 373 */ 374 DISDECL(int) DISFetchRegSeg(PCPUMCTXCORE pCtx, unsignedsel, RTSEL *pVal)374 DISDECL(int) DISFetchRegSeg(PCPUMCTXCORE pCtx, DIS_SELREG sel, RTSEL *pVal) 375 375 { 376 376 AssertReturn(sel < ELEMENTS(g_aRegSegIndex), VERR_INVALID_PARAMETER); … … 385 385 * 386 386 */ 387 DISDECL(int) DISFetchRegSegEx(PCPUMCTXCORE pCtx, unsignedsel, RTSEL *pVal, CPUMSELREGHID **ppSelHidReg)387 DISDECL(int) DISFetchRegSegEx(PCPUMCTXCORE pCtx, DIS_SELREG sel, RTSEL *pVal, CPUMSELREGHID **ppSelHidReg) 388 388 { 389 389 AssertReturn(sel < ELEMENTS(g_aRegSegIndex), VERR_INVALID_PARAMETER); … … 447 447 * 448 448 */ 449 DISDECL(int) DISWriteRegSeg(PCPUMCTXCORE pCtx, unsignedsel, RTSEL val)449 DISDECL(int) DISWriteRegSeg(PCPUMCTXCORE pCtx, DIS_SELREG sel, RTSEL val) 450 450 { 451 451 AssertReturn(sel < ELEMENTS(g_aRegSegIndex), VERR_INVALID_PARAMETER); -
trunk/src/VBox/VMM/DBGFDisas.cpp
r9656 r9675 250 250 if (DIS_FMT_SEL_IS_REG(u32Sel)) 251 251 { 252 if (DIS_FMT_SEL_GET_REG(u32Sel) == USE_REG_CS)252 if (DIS_FMT_SEL_GET_REG(u32Sel) == DIS_SELREG_CS) 253 253 rc = DBGFR3SymbolByAddr(pState->pVM, uAddress + pSelInfo->GCPtrBase, &off, &Sym); 254 254 else -
trunk/src/VBox/VMM/EM.cpp
r9659 r9675 1411 1411 { 1412 1412 Assert(!PATMIsPatchGCAddr(pVM, pCtx->eip)); 1413 CSAMR3CheckCodeEx(pVM, pCtx->cs, &pCtx->csHid, pCtx->eip);1413 CSAMR3CheckCodeEx(pVM, CPUMCTX2CORE(pCtx), pCtx->eip); 1414 1414 } 1415 1415 … … 1507 1507 if (pCtx->SysEnter.cs != 0) 1508 1508 { 1509 rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid, pCtx->eip),1509 rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip), 1510 1510 (SELMGetCpuModeFromSelector(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) == CPUMODE_32BIT) ? PATMFL_CODE32 : 0); 1511 1511 if (VBOX_SUCCESS(rc)) … … 1758 1758 && !PATMIsPatchGCAddr(pVM, pCtx->eip)) 1759 1759 { 1760 int rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid, pCtx->eip),1760 int rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip), 1761 1761 (SELMGetCpuModeFromSelector(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) == CPUMODE_32BIT) ? PATMFL_CODE32 : 0); 1762 1762 if (VBOX_SUCCESS(rc)) … … 2108 2108 */ 2109 2109 case VINF_PATM_HC_MMIO_PATCH_READ: 2110 rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid, pCtx->eip),2110 rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip), 2111 2111 PATMFL_MMIO_ACCESS | ((SELMGetCpuModeFromSelector(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) == CPUMODE_32BIT) ? PATMFL_CODE32 : 0)); 2112 2112 if (VBOX_FAILURE(rc)) … … 2370 2370 /* Prefetch pages for EIP and ESP */ 2371 2371 /** @todo This is rather expensive. Should investigate if it really helps at all. */ 2372 rc = PGMPrefetchPage(pVM, SELMToFlat(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid, pCtx->eip));2372 rc = PGMPrefetchPage(pVM, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip)); 2373 2373 if (rc == VINF_SUCCESS) 2374 rc = PGMPrefetchPage(pVM, SELMToFlat(pVM, pCtx->eflags, pCtx->ss, &pCtx->ssHid, pCtx->esp));2374 rc = PGMPrefetchPage(pVM, SELMToFlat(pVM, DIS_SELREG_SS, CPUMCTX2CORE(pCtx), pCtx->esp)); 2375 2375 if (rc != VINF_SUCCESS) 2376 2376 { … … 2479 2479 { 2480 2480 STAM_PROFILE_ADV_SUSPEND(&pVM->em.s.StatRAWEntry, b); 2481 CSAMR3CheckCodeEx(pVM, pCtx->cs, &pCtx->csHid, pCtx->eip);2481 CSAMR3CheckCodeEx(pVM, CPUMCTX2CORE(pCtx), pCtx->eip); 2482 2482 STAM_PROFILE_ADV_RESUME(&pVM->em.s.StatRAWEntry, b); 2483 2483 } … … 2980 2980 Log(("Forced action VM_FF_CSAM_SCAN_PAGE\n")); 2981 2981 2982 CSAMR3CheckCodeEx(pVM, pCtx->cs, &pCtx->csHid, pCtx->eip);2982 CSAMR3CheckCodeEx(pVM, CPUMCTX2CORE(pCtx), pCtx->eip); 2983 2983 VM_FF_CLEAR(pVM, VM_FF_CSAM_SCAN_PAGE); 2984 2984 } -
trunk/src/VBox/VMM/PATM/CSAM.cpp
r9659 r9675 2099 2099 * @returns VBox status code. 2100 2100 * @param pVM The VM to operate on. 2101 * @param Sel selector 2102 * @param pHiddenSel The hidden selector register. 2101 * @param pCtxCore CPU context 2103 2102 * @param pInstrGC Instruction pointer 2104 2103 */ 2105 CSAMR3DECL(int) CSAMR3CheckCodeEx(PVM pVM, RTSEL Sel, CPUMSELREGHID *pHiddenSel, RTRCPTR pInstrGC)2104 CSAMR3DECL(int) CSAMR3CheckCodeEx(PVM pVM, PCPUMCTXCORE pCtxCore, RTRCPTR pInstrGC) 2106 2105 { 2107 2106 if (EMIsRawRing0Enabled(pVM) == false || PATMIsPatchGCAddr(pVM, pInstrGC) == true) … … 2113 2112 if (CSAMIsEnabled(pVM)) 2114 2113 { 2115 X86EFLAGS fakeflags;2116 2117 /* we're not in v86 mode here */2118 fakeflags.u32 = 0;2119 2120 2114 /* Assuming 32 bits code for now. */ 2121 Assert(SELMGetCpuModeFromSelector(pVM, fakeflags, Sel, pHiddenSel) == CPUMODE_32BIT); 2122 2123 pInstrGC = SELMToFlat(pVM, fakeflags, Sel, pHiddenSel, pInstrGC); 2124 2115 Assert(SELMGetCpuModeFromSelector(pVM, pCtxCore->eflags, pCtxCore->cs, &pCtxCore->csHid) == CPUMODE_32BIT); 2116 2117 pInstrGC = SELMToFlat(pVM, DIS_SELREG_CS, pCtxCore, pInstrGC); 2125 2118 return CSAMR3CheckCode(pVM, pInstrGC); 2126 2119 } … … 2366 2359 CSAMP2GLOOKUPREC cacheRec = {0}; /* Cache record for PATMGCVirtToHCVirt. */ 2367 2360 PCSAMPAGE pPage = NULL; 2368 X86EFLAGS fakeflags;2369 2361 SELMSELINFO selInfo; 2370 2362 2371 /* we're not in v86 mode here */2372 fakeflags.u32 = 0;2373 2374 2363 pHandler = VBOXIDTE_OFFSET(*pGuestIdte); 2375 pHandler = SELMToFlat (pVM, fakeflags, pGuestIdte->Gen.u16SegSel, 0, pHandler);2364 pHandler = SELMToFlatBySel(pVM, pGuestIdte->Gen.u16SegSel, pHandler); 2376 2365 2377 2366 rc = SELMR3GetSelectorInfo(pVM, pGuestIdte->Gen.u16SegSel, &selInfo); -
trunk/src/VBox/VMM/PATM/PATM.cpp
r9228 r9675 1658 1658 /* mov ss, src? */ 1659 1659 if ( (pCpu->param1.flags & USE_REG_SEG) 1660 && (pCpu->param1.base.reg_seg == USE_REG_SS))1660 && (pCpu->param1.base.reg_seg == DIS_SELREG_SS)) 1661 1661 { 1662 1662 Log(("Force recompilation of next instruction for OP_MOV at %VRv\n", pCurInstrGC)); … … 3373 3373 3374 3374 pBranchTarget = pCtx->edx; 3375 pBranchTarget = SELMToFlat(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid, pBranchTarget);3375 pBranchTarget = SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pBranchTarget); 3376 3376 3377 3377 /* First we check if the duplicate function target lies in some existing function patch already. Will save some space. */ … … 3987 3987 if (CPUMGetGuestCPL(pVM, CPUMCTX2CORE(pCtx)) == 0) 3988 3988 { 3989 RTRCPTR pInstrGCFlat = SELMToFlat(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid, pInstrGC);3989 RTRCPTR pInstrGCFlat = SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pInstrGC); 3990 3990 if (pInstrGCFlat != pInstrGC) 3991 3991 { … … 6052 6052 6053 6053 /* continue at the original instruction */ 6054 *ppNewEip = pNewEip - SELMToFlat(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid, 0);6054 *ppNewEip = pNewEip - SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), 0); 6055 6055 STAM_PROFILE_ADV_STOP(&pVM->patm.s.StatHandleTrap, a); 6056 6056 return VINF_SUCCESS; … … 6119 6119 } 6120 6120 6121 *ppNewEip = pNewEip - SELMToFlat(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid, 0);6121 *ppNewEip = pNewEip - SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), 0); 6122 6122 STAM_PROFILE_ADV_STOP(&pVM->patm.s.StatHandleTrap, a); 6123 6123 return rc; … … 6152 6152 6153 6153 /* Return original address, correct by subtracting the CS base address. */ 6154 *ppNewEip = pNewEip - SELMToFlat(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid, 0);6154 *ppNewEip = pNewEip - SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), 0); 6155 6155 6156 6156 /* Reset the PATM stack. */ -
trunk/src/VBox/VMM/VMMAll/CPUMAllRegs.cpp
r9661 r9675 889 889 } 890 890 891 CPUMDECL(uint64_t) CPUMGetGuestFSBASE(PVM pVM) 892 { 893 return pVM->cpum.s.Guest.msrFSBASE; 894 } 895 896 CPUMDECL(uint64_t) CPUMGetGuestGSBASE(PVM pVM) 897 { 898 return pVM->cpum.s.Guest.msrGSBASE; 899 } 900 891 901 /** 892 902 * Gets a CpuId leaf. -
trunk/src/VBox/VMM/VMMAll/EMAll.cpp
r9663 r9675 344 344 static RTGCPTR emConvertToFlatAddr(PVM pVM, PCPUMCTXCORE pRegFrame, PDISCPUSTATE pCpu, POP_PARAMETER pParam, RTGCPTR pvAddr) 345 345 { 346 int prefix_seg, rc; 347 RTSEL sel; 348 CPUMSELREGHID *pSelHidReg; 349 350 prefix_seg = DISDetectSegReg(pCpu, pParam); 351 rc = DISFetchRegSegEx(pRegFrame, prefix_seg, &sel, &pSelHidReg); 352 if (VBOX_FAILURE(rc)) 353 return pvAddr; 354 355 return SELMToFlat(pVM, pRegFrame->eflags, sel, pSelHidReg, pvAddr); 346 DIS_SELREG enmPrefixSeg = DISDetectSegReg(pCpu, pParam); 347 return SELMToFlat(pVM, enmPrefixSeg, pRegFrame, pvAddr); 356 348 } 357 349 … … 639 631 640 632 /* Convert address; don't bother checking limits etc, as we only read here */ 641 pStackVal = SELMToFlat(pVM, pRegFrame->eflags, pRegFrame->ss, &pRegFrame->ssHid, (RTGCPTR)pRegFrame->esp);633 pStackVal = SELMToFlat(pVM, DIS_SELREG_SS, pRegFrame, (RTGCPTR)pRegFrame->esp); 642 634 if (pStackVal == 0) 643 635 return VERR_EM_INTERPRETER; … … 2037 2029 2038 2030 Assert(pRegFrame->eflags.u32 & X86_EFL_IF); 2039 Assert(pvFault == SELMToFlat(pVM, pRegFrame->eflags, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->eip));2031 Assert(pvFault == SELMToFlat(pVM, DIS_SELREG_CS, pRegFrame, (RTGCPTR)pRegFrame->eip)); 2040 2032 2041 2033 pVM->em.s.GCPtrInhibitInterrupts = pRegFrame->eip + pCpu->opsize; -
trunk/src/VBox/VMM/VMMAll/SELMAll.cpp
r9659 r9675 50 50 * @param Addr Address part. 51 51 */ 52 static RTGCPTR selmToFlat(PVM pVM, RTSEL Sel, RTGCPTR Addr)52 SELMDECL(RTGCPTR) SELMToFlatBySel(PVM pVM, RTSEL Sel, RTGCPTR Addr) 53 53 { 54 54 Assert(!CPUMAreHiddenSelRegsValid(pVM)); … … 81 81 * @returns Flat address. 82 82 * @param pVM VM Handle. 83 * @param eflags Current eflags 84 * @param Sel Selector part. 85 * @param pHiddenSel Hidden selector register 83 * @param SelReg Selector register 84 * @param pCtxCore CPU context 86 85 * @param Addr Address part. 87 86 */ 88 SELMDECL(RTGCPTR) SELMToFlat(PVM pVM, X86EFLAGS eflags, RTSEL Sel, CPUMSELREGHID *pHiddenSel, RTGCPTR Addr) 89 { 90 Assert(!CPUMIsGuestInLongMode(pVM)); /** @todo */ 91 Assert(pHiddenSel || !CPUMAreHiddenSelRegsValid(pVM)); 92 93 /* 94 * Deal with real & v86 mode first. 95 */ 87 SELMDECL(RTGCPTR) SELMToFlat(PVM pVM, DIS_SELREG SelReg, PCPUMCTXCORE pCtxCore, RTGCPTR Addr) 88 { 89 PCPUMSELREGHID pHiddenSel; 90 RTSEL Sel; 91 int rc; 92 93 rc = DISFetchRegSegEx(pCtxCore, SelReg, &Sel, &pHiddenSel); AssertRC(rc); 94 95 /* 96 * Deal with real & v86 mode first. 97 */ 96 98 if ( CPUMIsGuestInRealMode(pVM) 97 || eflags.Bits.u1VM)99 || pCtxCore->eflags.Bits.u1VM) 98 100 { 99 101 RTGCUINTPTR uFlat = (RTGCUINTPTR)Addr & 0xffff; … … 108 110 /** @todo when we're in 16 bits mode, we should cut off the address as well.. */ 109 111 if (!CPUMAreHiddenSelRegsValid(pVM)) 110 return selmToFlat(pVM, Sel, Addr); 112 return SELMToFlatBySel(pVM, Sel, Addr); 113 114 /* 64 bits mode: CS, DS, ES and SS are treated as if each segment base is 0 (Intel® 64 and IA-32 Architectures Software Developer's Manual: 3.4.2.1). */ 115 if ( CPUMIsGuestInLongMode(pVM) 116 && pCtxCore->csHid.Attr.n.u1Long) 117 { 118 switch (SelReg) 119 { 120 case DIS_SELREG_FS: 121 return (RTGCPTR)(CPUMGetGuestFSBASE(pVM) + Addr); 122 123 case DIS_SELREG_GS: 124 return (RTGCPTR)(CPUMGetGuestGSBASE(pVM) + Addr); 125 126 default: 127 return Addr; /* base 0 */ 128 } 129 } 111 130 return (RTGCPTR)(pHiddenSel->u64Base + (RTGCUINTPTR)Addr); 112 131 }
Note:
See TracChangeset
for help on using the changeset viewer.
