Changeset 96789 in vbox for trunk/src/VBox/VMM
- Timestamp:
- Sep 19, 2022 1:04:06 PM (2 years ago)
- Location:
- trunk/src/VBox/VMM
- Files:
-
- 6 edited
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VMMAll/IEMAllAImpl.asm (modified) (1 diff)
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VMMAll/IEMAllAImplC.cpp (modified) (1 diff)
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VMMAll/IEMAllInstructionsTwoByte0f.cpp.h (modified) (1 diff)
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include/IEMInternal.h (modified) (1 diff)
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include/IEMMc.h (modified) (2 diffs)
-
testcase/tstIEMCheckMc.cpp (modified) (2 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/VMMAll/IEMAllAImpl.asm
r96748 r96789 5961 5961 EPILOGUE_3_ARGS 5962 5962 ENDPROC iemAImpl_vcomisd_u128 5963 5964 5965 ;; 5966 ; Need to move this as well somewhere better? 5967 ; 5968 struc IEMMEDIAF2XMMSRC 5969 .uSrc1 resd 4 5970 .uSrc2 resd 4 5971 endstruc 5972 5973 5974 ; 5975 ; CMPPS (SSE) 5976 ; 5977 ; @param A0 Pointer to the MXCSR value (input/output). 5978 ; @param A1 Pointer to the first media register size operand (output). 5979 ; @param A2 Pointer to the two media register sized inputs - IEMMEDIAF2XMMSRC (input). 5980 ; @param A3 The 8-bit immediate (input). 5981 ; 5982 BEGINPROC_FASTCALL iemAImpl_cmpps_u128, 16 5983 PROLOGUE_4_ARGS 5984 IEMIMPL_SSE_PROLOGUE 5985 SSE_LD_FXSTATE_MXCSR_ONLY A0 5986 5987 movdqu xmm0, [A2 + IEMMEDIAF2XMMSRC.uSrc1] 5988 movdqu xmm1, [A2 + IEMMEDIAF2XMMSRC.uSrc2] 5989 lea T0, [A3 + A3*4] ; sizeof(cmpps+ret) == 5 5990 lea T1, [.imm0 xWrtRIP] 5991 lea T1, [T1 + T0] 5992 call T1 5993 movdqu [A1], xmm0 5994 5995 SSE_ST_FXSTATE_MXCSR_ONLY_NO_FXSTATE A0 5996 IEMIMPL_SSE_EPILOGUE 5997 EPILOGUE_4_ARGS 5998 %assign bImm 0 5999 %rep 256 6000 .imm %+ bImm: 6001 cmpps xmm0, xmm1, bImm 6002 ret 6003 %assign bImm bImm + 1 6004 %endrep 6005 .immEnd: ; 256*5 == 0x500 6006 dw 0xfaff + (.immEnd - .imm0) ; will cause warning if entries are too big. 6007 dw 0x104ff - (.immEnd - .imm0) ; will cause warning if entries are too small. 6008 ENDPROC iemAImpl_cmpps_u128 6009 6010 ;; 6011 ; SSE instructions with 8-bit immediates of the form 6012 ; xxx xmm1, xmm2, imm8. 6013 ; where the instruction encoding takes up 5 bytes and we need to load and save the MXCSR 6014 ; register. 6015 ; 6016 ; @param 1 The instruction name. 6017 ; 6018 ; @param A0 Pointer to the MXCSR value (input/output). 6019 ; @param A1 Pointer to the first media register size operand (output). 6020 ; @param A2 Pointer to the two media register sized inputs - IEMMEDIAF2XMMSRC (input). 6021 ; @param A3 The 8-bit immediate (input). 6022 ; 6023 %macro IEMIMPL_MEDIA_SSE_INSN_IMM8_MXCSR_5 1 6024 BEGINPROC_FASTCALL iemAImpl_ %+ %1 %+ _u128, 16 6025 PROLOGUE_4_ARGS 6026 IEMIMPL_SSE_PROLOGUE 6027 SSE_LD_FXSTATE_MXCSR_ONLY A0 6028 6029 movdqu xmm0, [A2 + IEMMEDIAF2XMMSRC.uSrc1] 6030 movdqu xmm1, [A2 + IEMMEDIAF2XMMSRC.uSrc2] 6031 lea T1, [.imm0 xWrtRIP] 6032 lea T0, [A3 + A3*2] ; sizeof(pshufXX+ret) == 6: (A3 * 3) *2 6033 lea T1, [T1 + T0*2] 6034 call T1 6035 movdqu [A1], xmm0 6036 6037 SSE_ST_FXSTATE_MXCSR_ONLY_NO_FXSTATE A0 6038 IEMIMPL_SSE_EPILOGUE 6039 EPILOGUE_4_ARGS 6040 %assign bImm 0 6041 %rep 256 6042 .imm %+ bImm: 6043 %1 xmm0, xmm1, bImm 6044 ret 6045 %assign bImm bImm + 1 6046 %endrep 6047 .immEnd: ; 256*6 == 0x600 6048 dw 0xf9ff + (.immEnd - .imm0) ; will cause warning if entries are too big. 6049 dw 0x105ff - (.immEnd - .imm0) ; will cause warning if entries are too small. 6050 ENDPROC iemAImpl_ %+ %1 %+ _u128 6051 %endmacro 6052 6053 IEMIMPL_MEDIA_SSE_INSN_IMM8_MXCSR_5 cmppd 6054 IEMIMPL_MEDIA_SSE_INSN_IMM8_MXCSR_5 cmpss 6055 IEMIMPL_MEDIA_SSE_INSN_IMM8_MXCSR_5 cmpsd -
trunk/src/VBox/VMM/VMMAll/IEMAllAImplC.cpp
r96748 r96789 16346 16346 iemAImpl_comisd_u128(pfMxcsr, pfEFlags, puSrc1, puSrc2); 16347 16347 } 16348 16349 16350 /** 16351 * CMPPS / CMPPD / CMPSS / CMPSD 16352 */ 16353 #ifdef IEM_WITHOUT_ASSEMBLY 16354 /** 16355 * A compare truth table entry. 16356 */ 16357 typedef struct CMPTRUTHTBLENTRY 16358 { 16359 /** Flag whether the \#IA is signalled when one of the source oeprans is a QNaN */ 16360 bool fSignalsOnQNan; 16361 /** The boolean result when the input operands are unordered. */ 16362 bool fUnordered; 16363 /** The boolean result when A = B. */ 16364 bool fEqual; 16365 /** The boolean result when A < B. */ 16366 bool fLowerThan; 16367 /** The boolean result when A > B. */ 16368 bool fGreaterThan; 16369 } CMPTRUTHTBLENTRY; 16370 /** Pointer to a const truth table entry. */ 16371 typedef const CMPTRUTHTBLENTRY *PCCMPTRUTHTBLENTRY; 16372 16373 16374 /** The compare truth table (indexed by immediate). */ 16375 static const CMPTRUTHTBLENTRY g_aCmpTbl[] = 16376 { 16377 /* fSignalsOnQNan fUnordered fEqual fLowerThan fGreaterThan */ 16378 /* 00H (EQ_OQ) */ { false, false, true, false, false }, 16379 /* 01H (LT_OS) */ { true, false, false, true, false }, 16380 /* 02H (LE_OS) */ { true, false, true, true, false }, 16381 /* 03H (UNORD_Q) */ { false, true, false, false, false }, 16382 /* 04H (NEQ_UQ) */ { false, true, false, true, true }, 16383 /* 05H (NLT_US) */ { true, true, true, false, true }, 16384 /* 06H (NLE_US) */ { true, true, false, false, true }, 16385 /* 07H (ORQ_Q) */ { false, false, true, true, true }, 16386 /** @todo AVX variants. */ 16387 }; 16388 16389 16390 static bool iemAImpl_cmp_worker_r32(uint32_t *pfMxcsr, PCRTFLOAT32U pr32Src1, PCRTFLOAT32U pr32Src2, uint8_t bEvil) 16391 { 16392 AssertRelease(bEvil < RT_ELEMENTS(g_aCmpTbl)); 16393 16394 if (RTFLOAT32U_IS_SIGNALLING_NAN(pr32Src1) || RTFLOAT32U_IS_SIGNALLING_NAN(pr32Src2)) 16395 { 16396 *pfMxcsr |= X86_MXCSR_IE; 16397 return g_aCmpTbl[bEvil].fUnordered; 16398 } 16399 else if (RTFLOAT32U_IS_QUIET_NAN(pr32Src1) || RTFLOAT32U_IS_QUIET_NAN(pr32Src2)) 16400 { 16401 if (g_aCmpTbl[bEvil].fSignalsOnQNan) 16402 *pfMxcsr |= X86_MXCSR_IE; 16403 return g_aCmpTbl[bEvil].fUnordered; 16404 } 16405 else 16406 { 16407 softfloat_state_t SoftState = IEM_SOFTFLOAT_STATE_INITIALIZER_FROM_MXCSR(*pfMxcsr); 16408 16409 RTFLOAT32U r32Src1, r32Src2; 16410 uint32_t fDe = iemSsePrepareValueR32(&r32Src1, *pfMxcsr, pr32Src1); 16411 fDe |= iemSsePrepareValueR32(&r32Src2, *pfMxcsr, pr32Src2); 16412 16413 *pfMxcsr |= fDe; 16414 float32_t f32Src1 = iemFpSoftF32FromIprt(&r32Src1); 16415 float32_t f32Src2 = iemFpSoftF32FromIprt(&r32Src2); 16416 if (f32_eq(f32Src1, f32Src2, &SoftState)) 16417 return g_aCmpTbl[bEvil].fEqual; 16418 else if (f32_lt(f32Src1, f32Src2, &SoftState)) 16419 return g_aCmpTbl[bEvil].fLowerThan; 16420 else 16421 return g_aCmpTbl[bEvil].fGreaterThan; 16422 } 16423 16424 AssertReleaseFailed(); 16425 return false; 16426 } 16427 16428 16429 static bool iemAImpl_cmp_worker_r64(uint32_t *pfMxcsr, PCRTFLOAT64U pr64Src1, PCRTFLOAT64U pr64Src2, uint8_t bEvil) 16430 { 16431 AssertRelease(bEvil < RT_ELEMENTS(g_aCmpTbl)); 16432 16433 if (RTFLOAT64U_IS_SIGNALLING_NAN(pr64Src1) || RTFLOAT64U_IS_SIGNALLING_NAN(pr64Src2)) 16434 { 16435 *pfMxcsr |= X86_MXCSR_IE; 16436 return g_aCmpTbl[bEvil].fUnordered; 16437 } 16438 else if (RTFLOAT64U_IS_QUIET_NAN(pr64Src1) || RTFLOAT64U_IS_QUIET_NAN(pr64Src2)) 16439 { 16440 if (g_aCmpTbl[bEvil].fSignalsOnQNan) 16441 *pfMxcsr |= X86_MXCSR_IE; 16442 return g_aCmpTbl[bEvil].fUnordered; 16443 } 16444 else 16445 { 16446 softfloat_state_t SoftState = IEM_SOFTFLOAT_STATE_INITIALIZER_FROM_MXCSR(*pfMxcsr); 16447 16448 RTFLOAT64U r64Src1, r64Src2; 16449 uint32_t fDe = iemSsePrepareValueR64(&r64Src1, *pfMxcsr, pr64Src1); 16450 fDe |= iemSsePrepareValueR64(&r64Src2, *pfMxcsr, pr64Src2); 16451 16452 *pfMxcsr |= fDe; 16453 float64_t f64Src1 = iemFpSoftF64FromIprt(&r64Src1); 16454 float64_t f64Src2 = iemFpSoftF64FromIprt(&r64Src2); 16455 if (f64_eq(f64Src1, f64Src2, &SoftState)) 16456 return g_aCmpTbl[bEvil].fEqual; 16457 else if (f64_lt(f64Src1, f64Src2, &SoftState)) 16458 return g_aCmpTbl[bEvil].fLowerThan; 16459 else 16460 return g_aCmpTbl[bEvil].fGreaterThan; 16461 } 16462 16463 AssertReleaseFailed(); 16464 return false; 16465 } 16466 16467 16468 IEM_DECL_IMPL_DEF(void, iemAImpl_cmpps_u128,(uint32_t *pfMxcsr, PX86XMMREG puDst, PCIEMMEDIAF2XMMSRC pSrc, uint8_t bEvil)) 16469 { 16470 for (uint8_t i = 0; i < RT_ELEMENTS(puDst->ar32); i++) 16471 { 16472 if (iemAImpl_cmp_worker_r32(pfMxcsr, &pSrc->uSrc1.ar32[i], &pSrc->uSrc2.ar32[i], bEvil & 0x7)) 16473 puDst->au32[i] = UINT32_MAX; 16474 else 16475 puDst->au32[i] = 0; 16476 } 16477 } 16478 16479 16480 IEM_DECL_IMPL_DEF(void, iemAImpl_cmppd_u128,(uint32_t *pfMxcsr, PX86XMMREG puDst, PCIEMMEDIAF2XMMSRC pSrc, uint8_t bEvil)) 16481 { 16482 for (uint8_t i = 0; i < RT_ELEMENTS(puDst->ar64); i++) 16483 { 16484 if (iemAImpl_cmp_worker_r64(pfMxcsr, &pSrc->uSrc1.ar64[i], &pSrc->uSrc2.ar64[i], bEvil & 0x7)) 16485 puDst->au64[i] = UINT64_MAX; 16486 else 16487 puDst->au64[i] = 0; 16488 } 16489 } 16490 16491 16492 IEM_DECL_IMPL_DEF(void, iemAImpl_cmpss_u128,(uint32_t *pfMxcsr, PX86XMMREG puDst, PCIEMMEDIAF2XMMSRC pSrc, uint8_t bEvil)) 16493 { 16494 if (iemAImpl_cmp_worker_r32(pfMxcsr, &pSrc->uSrc1.ar32[0], &pSrc->uSrc2.ar32[0], bEvil & 0x7)) 16495 puDst->au32[0] = UINT32_MAX; 16496 else 16497 puDst->au32[0] = 0; 16498 16499 puDst->au32[1] = pSrc->uSrc1.au32[1]; 16500 puDst->au64[1] = pSrc->uSrc1.au64[1]; 16501 } 16502 16503 16504 IEM_DECL_IMPL_DEF(void, iemAImpl_cmpsd_u128,(uint32_t *pfMxcsr, PX86XMMREG puDst, PCIEMMEDIAF2XMMSRC pSrc, uint8_t bEvil)) 16505 { 16506 if (iemAImpl_cmp_worker_r64(pfMxcsr, &pSrc->uSrc1.ar64[0], &pSrc->uSrc2.ar64[0], bEvil & 0x7)) 16507 puDst->au64[0] = UINT64_MAX; 16508 else 16509 puDst->au64[0] = 0; 16510 16511 puDst->au64[1] = pSrc->uSrc1.au64[1]; 16512 } 16513 #endif -
trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsTwoByte0f.cpp.h
r96751 r96789 10955 10955 10956 10956 /** Opcode 0x0f 0xc2 - cmpps Vps,Wps,Ib */ 10957 FNIEMOP_STUB(iemOp_cmpps_Vps_Wps_Ib); 10957 FNIEMOP_DEF(iemOp_cmpps_Vps_Wps_Ib) 10958 { 10959 IEMOP_MNEMONIC3(RMI, CMPPS, cmpps, Vps, Wps, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_SSE, 0); 10960 10961 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); 10962 if (IEM_IS_MODRM_REG_MODE(bRm)) 10963 { 10964 /* 10965 * Register, register. 10966 */ 10967 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm); 10968 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 10969 IEM_MC_BEGIN(4, 2); 10970 IEM_MC_LOCAL(IEMMEDIAF2XMMSRC, Src); 10971 IEM_MC_LOCAL(X86XMMREG, Dst); 10972 IEM_MC_ARG(uint32_t *, pfMxcsr, 0); 10973 IEM_MC_ARG_LOCAL_REF(PX86XMMREG, pDst, Dst, 1); 10974 IEM_MC_ARG_LOCAL_REF(PCIEMMEDIAF2XMMSRC, pSrc, Src, 2); 10975 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3); 10976 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT(); 10977 IEM_MC_PREPARE_SSE_USAGE(); 10978 IEM_MC_REF_MXCSR(pfMxcsr); 10979 IEM_MC_FETCH_XREG_XMM(Src.uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm)); 10980 IEM_MC_FETCH_XREG_XMM(Src.uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm)); 10981 IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_cmpps_u128, pfMxcsr, pDst, pSrc, bImmArg); 10982 IEM_MC_IF_MXCSR_XCPT_PENDING() 10983 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT(); 10984 IEM_MC_ELSE() 10985 IEM_MC_STORE_XREG_XMM(IEM_GET_MODRM_REG(pVCpu, bRm), Dst); 10986 IEM_MC_ENDIF(); 10987 10988 IEM_MC_ADVANCE_RIP(); 10989 IEM_MC_END(); 10990 } 10991 else 10992 { 10993 /* 10994 * Register, memory. 10995 */ 10996 IEM_MC_BEGIN(4, 3); 10997 IEM_MC_LOCAL(IEMMEDIAF2XMMSRC, Src); 10998 IEM_MC_LOCAL(X86XMMREG, Dst); 10999 IEM_MC_ARG(uint32_t *, pfMxcsr, 0); 11000 IEM_MC_ARG_LOCAL_REF(PX86XMMREG, pDst, Dst, 1); 11001 IEM_MC_ARG_LOCAL_REF(PCIEMMEDIAF2XMMSRC, pSrc, Src, 2); 11002 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); 11003 11004 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); 11005 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm); 11006 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3); 11007 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 11008 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT(); 11009 IEM_MC_FETCH_MEM_XMM_ALIGN_SSE(Src.uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); 11010 11011 IEM_MC_PREPARE_SSE_USAGE(); 11012 IEM_MC_REF_MXCSR(pfMxcsr); 11013 IEM_MC_FETCH_XREG_XMM(Src.uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm)); 11014 IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_cmpps_u128, pfMxcsr, pDst, pSrc, bImmArg); 11015 IEM_MC_IF_MXCSR_XCPT_PENDING() 11016 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT(); 11017 IEM_MC_ELSE() 11018 IEM_MC_STORE_XREG_XMM(IEM_GET_MODRM_REG(pVCpu, bRm), Dst); 11019 IEM_MC_ENDIF(); 11020 11021 IEM_MC_ADVANCE_RIP(); 11022 IEM_MC_END(); 11023 } 11024 return VINF_SUCCESS; 11025 } 11026 11027 10958 11028 /** Opcode 0x66 0x0f 0xc2 - cmppd Vpd,Wpd,Ib */ 10959 FNIEMOP_STUB(iemOp_cmppd_Vpd_Wpd_Ib); 11029 FNIEMOP_DEF(iemOp_cmppd_Vpd_Wpd_Ib) 11030 { 11031 IEMOP_MNEMONIC3(RMI, CMPPD, cmppd, Vpd, Wpd, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_SSE, 0); 11032 11033 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); 11034 if (IEM_IS_MODRM_REG_MODE(bRm)) 11035 { 11036 /* 11037 * Register, register. 11038 */ 11039 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm); 11040 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 11041 IEM_MC_BEGIN(4, 2); 11042 IEM_MC_LOCAL(IEMMEDIAF2XMMSRC, Src); 11043 IEM_MC_LOCAL(X86XMMREG, Dst); 11044 IEM_MC_ARG(uint32_t *, pfMxcsr, 0); 11045 IEM_MC_ARG_LOCAL_REF(PX86XMMREG, pDst, Dst, 1); 11046 IEM_MC_ARG_LOCAL_REF(PCIEMMEDIAF2XMMSRC, pSrc, Src, 2); 11047 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3); 11048 IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT(); 11049 IEM_MC_PREPARE_SSE_USAGE(); 11050 IEM_MC_REF_MXCSR(pfMxcsr); 11051 IEM_MC_FETCH_XREG_XMM(Src.uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm)); 11052 IEM_MC_FETCH_XREG_XMM(Src.uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm)); 11053 IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_cmppd_u128, pfMxcsr, pDst, pSrc, bImmArg); 11054 IEM_MC_IF_MXCSR_XCPT_PENDING() 11055 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT(); 11056 IEM_MC_ELSE() 11057 IEM_MC_STORE_XREG_XMM(IEM_GET_MODRM_REG(pVCpu, bRm), Dst); 11058 IEM_MC_ENDIF(); 11059 11060 IEM_MC_ADVANCE_RIP(); 11061 IEM_MC_END(); 11062 } 11063 else 11064 { 11065 /* 11066 * Register, memory. 11067 */ 11068 IEM_MC_BEGIN(4, 3); 11069 IEM_MC_LOCAL(IEMMEDIAF2XMMSRC, Src); 11070 IEM_MC_LOCAL(X86XMMREG, Dst); 11071 IEM_MC_ARG(uint32_t *, pfMxcsr, 0); 11072 IEM_MC_ARG_LOCAL_REF(PX86XMMREG, pDst, Dst, 1); 11073 IEM_MC_ARG_LOCAL_REF(PCIEMMEDIAF2XMMSRC, pSrc, Src, 2); 11074 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); 11075 11076 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); 11077 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm); 11078 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3); 11079 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 11080 IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT(); 11081 IEM_MC_FETCH_MEM_XMM_ALIGN_SSE(Src.uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); 11082 11083 IEM_MC_PREPARE_SSE_USAGE(); 11084 IEM_MC_REF_MXCSR(pfMxcsr); 11085 IEM_MC_FETCH_XREG_XMM(Src.uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm)); 11086 IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_cmppd_u128, pfMxcsr, pDst, pSrc, bImmArg); 11087 IEM_MC_IF_MXCSR_XCPT_PENDING() 11088 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT(); 11089 IEM_MC_ELSE() 11090 IEM_MC_STORE_XREG_XMM(IEM_GET_MODRM_REG(pVCpu, bRm), Dst); 11091 IEM_MC_ENDIF(); 11092 11093 IEM_MC_ADVANCE_RIP(); 11094 IEM_MC_END(); 11095 } 11096 return VINF_SUCCESS; 11097 } 11098 11099 10960 11100 /** Opcode 0xf3 0x0f 0xc2 - cmpss Vss,Wss,Ib */ 10961 FNIEMOP_STUB(iemOp_cmpss_Vss_Wss_Ib); 11101 FNIEMOP_DEF(iemOp_cmpss_Vss_Wss_Ib) 11102 { 11103 IEMOP_MNEMONIC3(RMI, CMPSS, cmpss, Vss, Wss, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_SSE, 0); 11104 11105 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); 11106 if (IEM_IS_MODRM_REG_MODE(bRm)) 11107 { 11108 /* 11109 * Register, register. 11110 */ 11111 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm); 11112 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 11113 IEM_MC_BEGIN(4, 2); 11114 IEM_MC_LOCAL(IEMMEDIAF2XMMSRC, Src); 11115 IEM_MC_LOCAL(X86XMMREG, Dst); 11116 IEM_MC_ARG(uint32_t *, pfMxcsr, 0); 11117 IEM_MC_ARG_LOCAL_REF(PX86XMMREG, pDst, Dst, 1); 11118 IEM_MC_ARG_LOCAL_REF(PCIEMMEDIAF2XMMSRC, pSrc, Src, 2); 11119 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3); 11120 IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT(); 11121 IEM_MC_PREPARE_SSE_USAGE(); 11122 IEM_MC_REF_MXCSR(pfMxcsr); 11123 IEM_MC_FETCH_XREG_XMM(Src.uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm)); 11124 IEM_MC_FETCH_XREG_XMM(Src.uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm)); 11125 IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_cmpss_u128, pfMxcsr, pDst, pSrc, bImmArg); 11126 IEM_MC_IF_MXCSR_XCPT_PENDING() 11127 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT(); 11128 IEM_MC_ELSE() 11129 IEM_MC_STORE_XREG_XMM(IEM_GET_MODRM_REG(pVCpu, bRm), Dst); 11130 IEM_MC_ENDIF(); 11131 11132 IEM_MC_ADVANCE_RIP(); 11133 IEM_MC_END(); 11134 } 11135 else 11136 { 11137 /* 11138 * Register, memory. 11139 */ 11140 IEM_MC_BEGIN(4, 3); 11141 IEM_MC_LOCAL(IEMMEDIAF2XMMSRC, Src); 11142 IEM_MC_LOCAL(X86XMMREG, Dst); 11143 IEM_MC_ARG(uint32_t *, pfMxcsr, 0); 11144 IEM_MC_ARG_LOCAL_REF(PX86XMMREG, pDst, Dst, 1); 11145 IEM_MC_ARG_LOCAL_REF(PCIEMMEDIAF2XMMSRC, pSrc, Src, 2); 11146 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); 11147 11148 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); 11149 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm); 11150 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3); 11151 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 11152 IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT(); 11153 IEM_MC_FETCH_MEM_XMM_U32(Src.uSrc2, 0 /*a_iDword */, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); 11154 11155 IEM_MC_PREPARE_SSE_USAGE(); 11156 IEM_MC_REF_MXCSR(pfMxcsr); 11157 IEM_MC_FETCH_XREG_XMM(Src.uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm)); 11158 IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_cmpss_u128, pfMxcsr, pDst, pSrc, bImmArg); 11159 IEM_MC_IF_MXCSR_XCPT_PENDING() 11160 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT(); 11161 IEM_MC_ELSE() 11162 IEM_MC_STORE_XREG_XMM_U32(IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iDword*/, Dst); 11163 IEM_MC_ENDIF(); 11164 11165 IEM_MC_ADVANCE_RIP(); 11166 IEM_MC_END(); 11167 } 11168 return VINF_SUCCESS; 11169 } 11170 11171 10962 11172 /** Opcode 0xf2 0x0f 0xc2 - cmpsd Vsd,Wsd,Ib */ 10963 FNIEMOP_STUB(iemOp_cmpsd_Vsd_Wsd_Ib); 11173 FNIEMOP_DEF(iemOp_cmpsd_Vsd_Wsd_Ib) 11174 { 11175 IEMOP_MNEMONIC3(RMI, CMPSD, cmpsd, Vsd, Wsd, Ib, DISOPTYPE_HARMLESS | DISOPTYPE_SSE, 0); 11176 11177 uint8_t bRm; IEM_OPCODE_GET_NEXT_U8(&bRm); 11178 if (IEM_IS_MODRM_REG_MODE(bRm)) 11179 { 11180 /* 11181 * Register, register. 11182 */ 11183 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm); 11184 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 11185 IEM_MC_BEGIN(4, 2); 11186 IEM_MC_LOCAL(IEMMEDIAF2XMMSRC, Src); 11187 IEM_MC_LOCAL(X86XMMREG, Dst); 11188 IEM_MC_ARG(uint32_t *, pfMxcsr, 0); 11189 IEM_MC_ARG_LOCAL_REF(PX86XMMREG, pDst, Dst, 1); 11190 IEM_MC_ARG_LOCAL_REF(PCIEMMEDIAF2XMMSRC, pSrc, Src, 2); 11191 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3); 11192 IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT(); 11193 IEM_MC_PREPARE_SSE_USAGE(); 11194 IEM_MC_REF_MXCSR(pfMxcsr); 11195 IEM_MC_FETCH_XREG_XMM(Src.uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm)); 11196 IEM_MC_FETCH_XREG_XMM(Src.uSrc2, IEM_GET_MODRM_RM(pVCpu, bRm)); 11197 IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_cmpsd_u128, pfMxcsr, pDst, pSrc, bImmArg); 11198 IEM_MC_IF_MXCSR_XCPT_PENDING() 11199 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT(); 11200 IEM_MC_ELSE() 11201 IEM_MC_STORE_XREG_XMM(IEM_GET_MODRM_REG(pVCpu, bRm), Dst); 11202 IEM_MC_ENDIF(); 11203 11204 IEM_MC_ADVANCE_RIP(); 11205 IEM_MC_END(); 11206 } 11207 else 11208 { 11209 /* 11210 * Register, memory. 11211 */ 11212 IEM_MC_BEGIN(4, 3); 11213 IEM_MC_LOCAL(IEMMEDIAF2XMMSRC, Src); 11214 IEM_MC_LOCAL(X86XMMREG, Dst); 11215 IEM_MC_ARG(uint32_t *, pfMxcsr, 0); 11216 IEM_MC_ARG_LOCAL_REF(PX86XMMREG, pDst, Dst, 1); 11217 IEM_MC_ARG_LOCAL_REF(PCIEMMEDIAF2XMMSRC, pSrc, Src, 2); 11218 IEM_MC_LOCAL(RTGCPTR, GCPtrEffSrc); 11219 11220 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); 11221 uint8_t bImm; IEM_OPCODE_GET_NEXT_U8(&bImm); 11222 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3); 11223 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 11224 IEM_MC_MAYBE_RAISE_SSE2_RELATED_XCPT(); 11225 IEM_MC_FETCH_MEM_XMM_U32(Src.uSrc2, 0 /*a_iDword */, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); 11226 11227 IEM_MC_PREPARE_SSE_USAGE(); 11228 IEM_MC_REF_MXCSR(pfMxcsr); 11229 IEM_MC_FETCH_XREG_XMM(Src.uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm)); 11230 IEM_MC_CALL_VOID_AIMPL_4(iemAImpl_cmpsd_u128, pfMxcsr, pDst, pSrc, bImmArg); 11231 IEM_MC_IF_MXCSR_XCPT_PENDING() 11232 IEM_MC_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT(); 11233 IEM_MC_ELSE() 11234 IEM_MC_STORE_XREG_XMM_U32(IEM_GET_MODRM_REG(pVCpu, bRm), 0 /*a_iDword*/, Dst); 11235 IEM_MC_ENDIF(); 11236 11237 IEM_MC_ADVANCE_RIP(); 11238 IEM_MC_END(); 11239 } 11240 return VINF_SUCCESS; 11241 } 10964 11242 10965 11243 -
trunk/src/VBox/VMM/include/IEMInternal.h
r96748 r96789 2346 2346 FNIEMAIMPLF2EFLMXCSR128 iemAImpl_comisd_u128; 2347 2347 FNIEMAIMPLF2EFLMXCSR128 iemAImpl_vcomisd_u128, iemAImpl_vcomisd_u128_fallback; 2348 2349 2350 typedef struct IEMMEDIAF2XMMSRC 2351 { 2352 X86XMMREG uSrc1; 2353 X86XMMREG uSrc2; 2354 } IEMMEDIAF2XMMSRC; 2355 typedef IEMMEDIAF2XMMSRC *PIEMMEDIAF2XMMSRC; 2356 typedef const IEMMEDIAF2XMMSRC *PCIEMMEDIAF2XMMSRC; 2357 2358 typedef IEM_DECL_IMPL_TYPE(void, FNIEMAIMPLMXCSRF2XMMIMM8,(uint32_t *pfMxcsr, PX86XMMREG puDst, PCIEMMEDIAF2XMMSRC puSrc, uint8_t bEvil)); 2359 typedef FNIEMAIMPLMXCSRF2XMMIMM8 *PFNIEMAIMPLMXCSRF2XMMIMM8; 2360 2361 FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpps_u128; 2362 FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmppd_u128; 2363 FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpss_u128; 2364 FNIEMAIMPLMXCSRF2XMMIMM8 iemAImpl_cmpsd_u128; 2365 2348 2366 /** @} */ 2349 2367 -
trunk/src/VBox/VMM/include/IEMMc.h
r96751 r96789 452 452 (a_u128Value).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1]; \ 453 453 } while (0) 454 #define IEM_MC_FETCH_XREG_XMM(a_XmmValue, a_iXReg) \ 455 do { (a_XmmValue).au64[0] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0]; \ 456 (a_XmmValue).au64[1] = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1]; \ 457 } while (0) 454 458 #define IEM_MC_FETCH_XREG_U64(a_u64Value, a_iXReg) \ 455 459 do { (a_u64Value) = pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0]; } while (0) … … 462 466 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = (a_u128Value).au64[1]; \ 463 467 } while (0) 468 #define IEM_MC_STORE_XREG_XMM(a_iXReg, a_XmmValue) \ 469 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (a_XmmValue).au64[0]; \ 470 pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[1] = (a_XmmValue).au64[1]; \ 471 } while (0) 472 #define IEM_MC_STORE_XREG_XMM_U32(a_iXReg, a_iDword, a_XmmValue) \ 473 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au32[(a_iDword)] = (a_XmmValue).au32[(a_iDword)]; } while (0) 474 #define IEM_MC_STORE_XREG_XMM_U64(a_iXReg, a_iQword, a_XmmValue) \ 475 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[(a_iQword)] = (a_XmmValue).au64[(a_iQword)]; } while (0) 464 476 #define IEM_MC_STORE_XREG_U64(a_iXReg, a_u64Value) \ 465 477 do { pVCpu->cpum.GstCtx.XState.x87.aXMM[(a_iXReg)].au64[0] = (a_u64Value); } while (0) -
trunk/src/VBox/VMM/testcase/tstIEMCheckMc.cpp
r96751 r96789 50 50 uint8_t volatile g_bRandom; 51 51 RTUINT128U g_u128Zero; 52 X86XMMREG g_XmmZero; 52 53 53 54 … … 736 737 737 738 #define IEM_MC_FETCH_XREG_U128(a_u128Value, a_iXReg) do { (a_u128Value) = g_u128Zero; CHK_TYPE(RTUINT128U, a_u128Value); (void)fSseRead; (void)fMcBegin; } while (0) 739 #define IEM_MC_FETCH_XREG_XMM(a_XmmValue, a_iXReg) do { (a_XmmValue) = g_XmmZero; CHK_TYPE(X86XMMREG, a_XmmValue); (void)fSseRead; (void)fMcBegin; } while (0) 738 740 #define IEM_MC_FETCH_XREG_U64(a_u64Value, a_iXReg) do { (a_u64Value) = 0; CHK_TYPE(uint64_t, a_u64Value); (void)fSseRead; (void)fMcBegin; } while (0) 739 741 #define IEM_MC_FETCH_XREG_U32(a_u32Value, a_iXReg) do { (a_u32Value) = 0; CHK_TYPE(uint32_t, a_u32Value); (void)fSseRead; (void)fMcBegin; } while (0) 740 742 #define IEM_MC_FETCH_XREG_HI_U64(a_u64Value, a_iXReg) do { (a_u64Value) = 0; CHK_TYPE(uint64_t, a_u64Value); (void)fSseRead; (void)fMcBegin; } while (0) 741 743 #define IEM_MC_STORE_XREG_U128(a_iXReg, a_u128Value) do { CHK_TYPE(RTUINT128U, a_u128Value); (void)fSseWrite; (void)fMcBegin; } while (0) 744 #define IEM_MC_STORE_XREG_XMM(a_iXReg, a_XmmValue) do { CHK_TYPE(X86XMMREG, a_XmmValue); (void)fSseWrite; (void)fMcBegin; } while (0) 745 #define IEM_MC_STORE_XREG_XMM_U32(a_iXReg, a_iDword, a_XmmValue) do { CHK_TYPE(X86XMMREG, a_XmmValue); AssertCompile((a_iDword) < RT_ELEMENTS((a_XmmValue).au32)); (void)fSseWrite; (void)fMcBegin; } while (0) 746 #define IEM_MC_STORE_XREG_XMM_U64(a_iXReg, a_iQword, a_XmmValue) do { CHK_TYPE(X86XMMREG, a_XmmValue); AssertCompile((a_iQword) < RT_ELEMENTS((a_XmmValue).au64)); (void)fSseWrite; (void)fMcBegin; } while (0) 742 747 #define IEM_MC_STORE_XREG_U64(a_iXReg, a_u64Value) do { CHK_TYPE(uint64_t, a_u64Value); (void)fSseWrite; (void)fMcBegin; } while (0) 743 748 #define IEM_MC_STORE_XREG_U64_ZX_U128(a_iXReg, a_u64Value) do { CHK_TYPE(uint64_t, a_u64Value); (void)fSseWrite; (void)fMcBegin; } while (0)
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