Changeset 96948 in vbox for trunk/src/VBox/VMM/VMMAll

Timestamp:

Sep 30, 2022 6:58:20 AM (2 years ago)

Author:

vboxsync

Message:

IEM: Slightly corrected SYSCALL/SYSRET, fixed logging.

File:

• trunk/src/VBox/VMM/VMMAll/IEMAllCImpl.cpp (modified) (11 diffs)

trunk/src/VBox/VMM/VMMAll/IEMAllCImpl.cpp

@@ -4122 +4122 @@
     if (uNewCs == 0 || uNewSs == 0)
     {
+        /** @todo Neither Intel nor AMD document this check. */
         Log(("syscall: msrSTAR.CS = 0 or SS = 0 -> #GP(0)\n"));
         return iemRaiseGeneralProtectionFault0(pVCpu);
@@ -4135 +4136 @@
         if (!IEM_IS_CANONICAL(uNewRip))
         {
+            /** @todo Intel claims this can't happen because IA32_LSTAR MSR can't be written with non-canonical address. */
             Log(("syscall: New RIP not canonical -> #UD\n"));
             return iemRaiseUndefinedOpcode(pVCpu);
@@ -4142 +4144 @@
          * Commit it.
          */
-        Log(("syscall: %04x:%016RX64 [efl=%#llx] -> %04x:%016RX64\n", pVCpu->cpum.GstCtx.cs, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.rflags.u, uNewCs, uNewRip));
+        Log(("syscall: %04x:%016RX64 [efl=%#llx] -> %04x:%016RX64\n", pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.rflags.u, uNewCs, uNewRip));
         pVCpu->cpum.GstCtx.rcx           = pVCpu->cpum.GstCtx.rip + cbInstr;
         pVCpu->cpum.GstCtx.rip           = uNewRip;
@@ -4152 +4154 @@
 
         pVCpu->cpum.GstCtx.cs.Attr.u     = X86DESCATTR_P | X86DESCATTR_G | X86DESCATTR_L | X86DESCATTR_DT | X86_SEL_TYPE_ER_ACC;
-        pVCpu->cpum.GstCtx.ss.Attr.u     = X86DESCATTR_P | X86DESCATTR_G | X86DESCATTR_L | X86DESCATTR_DT | X86_SEL_TYPE_RW_ACC;
+        pVCpu->cpum.GstCtx.ss.Attr.u     = X86DESCATTR_P | X86DESCATTR_G | X86DESCATTR_D | X86DESCATTR_DT | X86_SEL_TYPE_RW_ACC;
     }
     else
@@ -4159 +4161 @@
          * Commit it.
          */
-        Log(("syscall: %04x:%08RX32 [efl=%#x] -> %04x:%08RX32\n",
-             pVCpu->cpum.GstCtx.cs, pVCpu->cpum.GstCtx.eip, pVCpu->cpum.GstCtx.eflags.u, uNewCs, (uint32_t)(pVCpu->cpum.GstCtx.msrSTAR & MSR_K6_STAR_SYSCALL_EIP_MASK)));
+        Log(("syscall: %04x:%08RX32 [efl=%#x] -> %04x:%08RX32\n", pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.eip, pVCpu->cpum.GstCtx.eflags.u, uNewCs, (uint32_t)(pVCpu->cpum.GstCtx.msrSTAR & MSR_K6_STAR_SYSCALL_EIP_MASK)));
         pVCpu->cpum.GstCtx.rcx           = pVCpu->cpum.GstCtx.eip + cbInstr;
         pVCpu->cpum.GstCtx.rip           = pVCpu->cpum.GstCtx.msrSTAR & MSR_K6_STAR_SYSCALL_EIP_MASK;
@@ -4179 +4180 @@
     pVCpu->cpum.GstCtx.ss.u32Limit   = UINT32_MAX;
     pVCpu->cpum.GstCtx.ss.fFlags     = CPUMSELREG_FLAGS_VALID;
+
+    pVCpu->iem.s.uCpl       = 0;
+    pVCpu->iem.s.enmCpuMode = iemCalcCpuMode(pVCpu);
 
     /* Flush the prefetch buffer. */
@@ -4247 +4251 @@
         if (pVCpu->iem.s.enmEffOpSize == IEMMODE_64BIT)
         {
-            Log(("sysret: %04x:%016RX64 [efl=%#llx] -> %04x:%016RX64 [r11=%#llx]\n",
-                 pVCpu->cpum.GstCtx.cs, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.rflags.u, uNewCs, pVCpu->cpum.GstCtx.rcx, pVCpu->cpum.GstCtx.r11));
-            /* Note! We disregard intel manual regarding the RCX cananonical
+            Log(("sysret: %04x:%016RX64 [efl=%#llx] -> %04x:%016RX64 [r11=%#llx]\n", pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.rflags.u, uNewCs, pVCpu->cpum.GstCtx.rcx, pVCpu->cpum.GstCtx.r11));
+            /* Note! We disregard intel manual regarding the RCX canonical
                      check, ask intel+xen why AMD doesn't do it. */
             pVCpu->cpum.GstCtx.rip       = pVCpu->cpum.GstCtx.rcx;
@@ -4257 +4260 @@
         else
         {
-            Log(("sysret: %04x:%016RX64 [efl=%#llx] -> %04x:%08RX32 [r11=%#llx]\n",
-                 pVCpu->cpum.GstCtx.cs, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.rflags.u, uNewCs, pVCpu->cpum.GstCtx.ecx, pVCpu->cpum.GstCtx.r11));
+            Log(("sysret: %04x:%016RX64 [efl=%#llx] -> %04x:%08RX32 [r11=%#llx]\n", pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.rflags.u, uNewCs, pVCpu->cpum.GstCtx.ecx, pVCpu->cpum.GstCtx.r11));
             pVCpu->cpum.GstCtx.rip       = pVCpu->cpum.GstCtx.ecx;
             pVCpu->cpum.GstCtx.cs.Attr.u = X86DESCATTR_P | X86DESCATTR_G | X86DESCATTR_D | X86DESCATTR_DT | X86_SEL_TYPE_ER_ACC
@@ -4264 +4266 @@
         }
         /** @todo testcase: See what kind of flags we can make SYSRET restore and
-         *        what it really ignores. RF and VM are hinted at being zero, by AMD. */
+         *        what it really ignores. RF and VM are hinted at being zero, by AMD.
+         *        Intel says:  RFLAGS := (R11 & 3C7FD7H) | 2; */
         pVCpu->cpum.GstCtx.rflags.u      = pVCpu->cpum.GstCtx.r11 & (X86_EFL_POPF_BITS | X86_EFL_VIF | X86_EFL_VIP);
         pVCpu->cpum.GstCtx.rflags.u     |= X86_EFL_1;
@@ -4270 +4273 @@
     else
     {
-        Log(("sysret: %04x:%08RX32 [efl=%#x] -> %04x:%08RX32\n", pVCpu->cpum.GstCtx.cs, pVCpu->cpum.GstCtx.eip, pVCpu->cpum.GstCtx.eflags.u, uNewCs, pVCpu->cpum.GstCtx.ecx));
+        Log(("sysret: %04x:%08RX32 [efl=%#x] -> %04x:%08RX32\n", pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.eip, pVCpu->cpum.GstCtx.eflags.u, uNewCs, pVCpu->cpum.GstCtx.ecx));
         pVCpu->cpum.GstCtx.rip           = pVCpu->cpum.GstCtx.rcx;
         pVCpu->cpum.GstCtx.rflags.u     |= X86_EFL_IF;
@@ -4289 +4292 @@
     /** @todo Testcase: verify that SS.u1Long and SS.u1DefBig are left unchanged
      *        on sysret. */
+
+    pVCpu->iem.s.uCpl       = 3;
+    pVCpu->iem.s.enmCpuMode = iemCalcCpuMode(pVCpu);
 
     /* Flush the prefetch buffer. */