Changeset 9708 in vbox for trunk/src/VBox

Timestamp:

Jun 16, 2008 10:01:38 AM (17 years ago)

Author:

vboxsync

Message:

Use RIP everywhere

Location:

trunk/src/VBox/VMM/VMMR0

Files:

• HWSVMR0.cpp (modified) (33 diffs)
• HWVMXR0.cpp (modified) (24 diffs)

trunk/src/VBox/VMM/VMMR0/HWSVMR0.cpp

@@ -349 +349 @@
 #ifdef VBOX_STRICT
     if (pEvent->n.u8Vector == 0xE)
-        Log(("SVM: Inject int %d at %VGv error code=%08x CR2=%08x intInfo=%08x\n", pEvent->n.u8Vector, pCtx->eip, pEvent->n.u32ErrorCode, pCtx->cr2, pEvent->au64[0]));
+        Log(("SVM: Inject int %d at %VGv error code=%08x CR2=%08x intInfo=%08x\n", pEvent->n.u8Vector, pCtx->rip, pEvent->n.u32ErrorCode, pCtx->cr2, pEvent->au64[0]));
     else
     if (pEvent->n.u8Vector < 0x20)
-        Log(("SVM: Inject int %d at %VGv error code=%08x\n", pEvent->n.u8Vector, pCtx->eip, pEvent->n.u32ErrorCode));
+        Log(("SVM: Inject int %d at %VGv error code=%08x\n", pEvent->n.u8Vector, pCtx->rip, pEvent->n.u32ErrorCode));
     else
     {
-        Log(("INJ-EI: %x at %VGv\n", pEvent->n.u8Vector, pCtx->eip));
+        Log(("INJ-EI: %x at %VGv\n", pEvent->n.u8Vector, pCtx->rip));
         Assert(!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS));
         Assert(pCtx->eflags.u32 & X86_EFL_IF);
@@ -383 +383 @@
         SVM_EVENT Event;
 
-        Log(("Reinjecting event %08x %08x at %VGv\n", pVM->hwaccm.s.Event.intInfo, pVM->hwaccm.s.Event.errCode, pCtx->eip));
+        Log(("Reinjecting event %08x %08x at %VGv\n", pVM->hwaccm.s.Event.intInfo, pVM->hwaccm.s.Event.errCode, pCtx->rip));
         STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntReinject);
         Event.au64[0] = pVM->hwaccm.s.Event.intInfo;
@@ -429 +429 @@
         }
         else
-            Log(("Pending interrupt blocked at %VGv by VM_FF_INHIBIT_INTERRUPTS!!\n", pCtx->eip));
+            Log(("Pending interrupt blocked at %VGv by VM_FF_INHIBIT_INTERRUPTS!!\n", pCtx->rip));
     }
 
@@ -772 +772 @@
     if (VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
     {
-        Log(("VM_FF_INHIBIT_INTERRUPTS at %VGv successor %VGv\n", pCtx->eip, EMGetInhibitInterruptsPC(pVM)));
-        if (pCtx->eip != EMGetInhibitInterruptsPC(pVM))
+        Log(("VM_FF_INHIBIT_INTERRUPTS at %VGv successor %VGv\n", pCtx->rip, EMGetInhibitInterruptsPC(pVM)));
+        if (pCtx->rip != EMGetInhibitInterruptsPC(pVM))
         {
             /** @note we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
@@ -1074 +1074 @@
     if (pVMCB->ctrl.u64IntShadow & SVM_INTERRUPT_SHADOW_ACTIVE)
     {
-        Log(("uInterruptState %x eip=%VGv\n", pVMCB->ctrl.u64IntShadow, pCtx->eip));
-        EMSetInhibitInterruptsPC(pVM, pCtx->eip);
+        Log(("uInterruptState %x eip=%VGv\n", pVMCB->ctrl.u64IntShadow, pCtx->rip));
+        EMSetInhibitInterruptsPC(pVM, pCtx->rip);
     }
     else
@@ -1092 +1092 @@
         &&  pVMCB->ctrl.ExitIntInfo.n.u3Type != SVM_EVENT_SOFTWARE_INT /* we don't care about 'int xx' as the instruction will be restarted. */)
     {
-        Log(("Pending inject %VX64 at %08x exit=%08x\n", pVM->hwaccm.s.Event.intInfo, pCtx->eip, exitCode));
+        Log(("Pending inject %VX64 at %VGv exit=%08x\n", pVM->hwaccm.s.Event.intInfo, pCtx->rip, exitCode));
         pVM->hwaccm.s.Event.fPending = true;
         /* Error code present? (redundant) */
@@ -1139 +1139 @@
             uint32_t oldCR0;
 
-            Log(("#NM fault at %VGv\n", pCtx->eip));
+            Log(("#NM fault at %VGv\n", pCtx->rip));
 
             /** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
@@ -1184 +1184 @@
                  * Forward the trap to the guest by injecting the exception and resuming execution.
                  */
-                Log(("Page fault at %VGv cr2=%VGv error code %x\n", pCtx->eip, uFaultAddress, errCode));
+                Log(("Page fault at %VGv cr2=%VGv error code %x\n", pCtx->rip, uFaultAddress, errCode));
                 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitGuestPF);
 
@@ -1205 +1205 @@
             Assert(!pVM->hwaccm.s.fNestedPaging);
 
-            Log2(("Page fault at %VGv cr2=%VGv error code %x\n", pCtx->eip, uFaultAddress, errCode));
+            Log2(("Page fault at %VGv cr2=%VGv error code %x\n", pCtx->rip, uFaultAddress, errCode));
             /* Exit qualification contains the linear address of the page fault. */
             TRPMAssertTrap(pVM, X86_XCPT_PF, TRPM_TRAP);
@@ -1213 +1213 @@
             /* Forward it to our trap handler first, in case our shadow pages are out of sync. */
             rc = PGMTrap0eHandler(pVM, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
-            Log2(("PGMTrap0eHandler %VGv returned %Vrc\n", pCtx->eip, rc));
+            Log2(("PGMTrap0eHandler %VGv returned %Vrc\n", pCtx->rip, rc));
             if (rc == VINF_SUCCESS)
             {   /* We've successfully synced our shadow pages, so let's just continue execution. */
-                Log2(("Shadow page fault at %VGv cr2=%VGv error code %x\n", pCtx->eip, uFaultAddress, errCode));
+                Log2(("Shadow page fault at %VGv cr2=%VGv error code %x\n", pCtx->rip, uFaultAddress, errCode));
                 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowPF);
 
@@ -1270 +1270 @@
                 break;
             }
-            Log(("Trap %x at %VGv\n", vector, pCtx->eip));
+            Log(("Trap %x at %VGv\n", vector, pCtx->rip));
 
             Event.au64[0]    = 0;
@@ -1319 +1319 @@
                 break;
             }
-            Log(("Trap %x at %VGv esi=%x\n", vector, pCtx->eip, pCtx->esi));
+            Log(("Trap %x at %VGv esi=%x\n", vector, pCtx->rip, pCtx->esi));
             SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
 
@@ -1343 +1343 @@
         Assert(pVM->hwaccm.s.fNestedPaging);
 
-        Log(("Nested page fault at %VGv cr2=%VGp error code %x\n", pCtx->eip, uFaultAddress, errCode));
+        Log(("Nested page fault at %VGv cr2=%VGp error code %x\n", pCtx->rip, uFaultAddress, errCode));
         /* Exit qualification contains the linear address of the page fault. */
         TRPMAssertTrap(pVM, X86_XCPT_PF, TRPM_TRAP);
@@ -1351 +1351 @@
         /* Handle the pagefault trap for the nested shadow table. */
         rc = PGMR0Trap0eHandlerNestedPaging(pVM, PGMGetHostMode(pVM), errCode, CPUMCTX2CORE(pCtx), uFaultAddress);
-        Log2(("PGMR0Trap0eHandlerNestedPaging %VGv returned %Vrc\n", pCtx->eip, rc));
+        Log2(("PGMR0Trap0eHandlerNestedPaging %VGv returned %Vrc\n", pCtx->rip, rc));
         if (rc == VINF_SUCCESS)
         {   /* We've successfully synced our shadow pages, so let's just continue execution. */
-            Log2(("Shadow page fault at %VGv cr2=%VGp error code %x\n", pCtx->eip, uFaultAddress, errCode));
+            Log2(("Shadow page fault at %VGv cr2=%VGp error code %x\n", pCtx->rip, uFaultAddress, errCode));
             STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowPF);
 
@@ -1393 +1393 @@
         STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvd);
         /* Skip instruction and continue directly. */
-        pCtx->eip += 2;     /** @note hardcoded opcode size! */
+        pCtx->rip += 2;     /** @note hardcoded opcode size! */
         /* Continue execution.*/
         STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
@@ -1406 +1406 @@
         {
             /* Update EIP and continue execution. */
-            pCtx->eip += 2;             /** @note hardcoded opcode size! */
+            pCtx->rip += 2;             /** @note hardcoded opcode size! */
             STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
             goto ResumeExecution;
@@ -1423 +1423 @@
         {
             /* Update EIP and continue execution. */
-            pCtx->eip += 2;             /** @note hardcoded opcode size! */
+            pCtx->rip += 2;             /** @note hardcoded opcode size! */
             STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
             goto ResumeExecution;
@@ -1456 +1456 @@
         uint32_t cbSize;
 
-        Log2(("SVM: %VGv mov cr%d, \n", pCtx->eip, exitCode - SVM_EXIT_WRITE_CR0));
+        Log2(("SVM: %VGv mov cr%d, \n", pCtx->rip, exitCode - SVM_EXIT_WRITE_CR0));
         STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxWrite);
         rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
@@ -1508 +1508 @@
         uint32_t cbSize;
 
-        Log2(("SVM: %VGv mov x, cr%d\n", pCtx->eip, exitCode - SVM_EXIT_READ_CR0));
+        Log2(("SVM: %VGv mov x, cr%d\n", pCtx->rip, exitCode - SVM_EXIT_READ_CR0));
         STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxRead);
         rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
@@ -1530 +1530 @@
         uint32_t cbSize;
 
-        Log2(("SVM: %VGv mov dr%d, x\n", pCtx->eip, exitCode - SVM_EXIT_WRITE_DR0));
+        Log2(("SVM: %VGv mov dr%d, x\n", pCtx->rip, exitCode - SVM_EXIT_WRITE_DR0));
         STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxRead);
         rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
@@ -1552 +1552 @@
         uint32_t cbSize;
 
-        Log2(("SVM: %VGv mov dr%d, x\n", pCtx->eip, exitCode - SVM_EXIT_READ_DR0));
+        Log2(("SVM: %VGv mov dr%d, x\n", pCtx->rip, exitCode - SVM_EXIT_READ_DR0));
         STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitDRxRead);
         rc = EMInterpretInstruction(pVM, CPUMCTX2CORE(pCtx), 0, &cbSize);
@@ -1609 +1609 @@
             if (IoExitInfo.n.u1Type == 0)
             {
-                Log2(("IOMInterpretOUTSEx %VGv %x size=%d\n", pCtx->eip, IoExitInfo.n.u16Port, uIOSize));
+                Log2(("IOMInterpretOUTSEx %VGv %x size=%d\n", pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
                 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringWrite);
                 rc = IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, prefix, uIOSize);
@@ -1615 +1615 @@
             else
             {
-                Log2(("IOMInterpretINSEx  %VGv %x size=%d\n", pCtx->eip, IoExitInfo.n.u16Port, uIOSize));
+                Log2(("IOMInterpretINSEx  %VGv %x size=%d\n", pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
                 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringRead);
                 rc = IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), IoExitInfo.n.u16Port, prefix, uIOSize);
@@ -1627 +1627 @@
             if (IoExitInfo.n.u1Type == 0)
             {
-                Log2(("IOMIOPortWrite %VGv %x %x size=%d\n", pCtx->eip, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize));
+                Log2(("IOMIOPortWrite %VGv %x %x size=%d\n", pCtx->rip, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize));
                 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOWrite);
                 rc = IOMIOPortWrite(pVM, IoExitInfo.n.u16Port, pCtx->eax & uAndVal, uIOSize);
@@ -1641 +1641 @@
                     /* Write back to the EAX register. */
                     pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
-                    Log2(("IOMIOPortRead %VGv %x %x size=%d\n", pCtx->eip, IoExitInfo.n.u16Port, u32Val & uAndVal, uIOSize));
+                    Log2(("IOMIOPortRead %VGv %x %x size=%d\n", pCtx->rip, IoExitInfo.n.u16Port, u32Val & uAndVal, uIOSize));
                 }
             }
@@ -1652 +1652 @@
         {
             /* Update EIP and continue execution. */
-            pCtx->eip = pVMCB->ctrl.u64ExitInfo2;      /* RIP/EIP of the next instruction is saved in EXITINFO2. */
+            pCtx->rip = pVMCB->ctrl.u64ExitInfo2;      /* RIP/EIP of the next instruction is saved in EXITINFO2. */
             if (RT_LIKELY(rc == VINF_SUCCESS))
             {
@@ -1658 +1658 @@
                 goto ResumeExecution;
             }
-            Log2(("EM status from IO at %VGv %x size %d: %Vrc\n", pCtx->eip, IoExitInfo.n.u16Port, uIOSize, rc));
+            Log2(("EM status from IO at %VGv %x size %d: %Vrc\n", pCtx->rip, IoExitInfo.n.u16Port, uIOSize, rc));
             break;
         }
@@ -1670 +1670 @@
             AssertMsg(VBOX_FAILURE(rc) || rc == VINF_EM_RAW_EMULATE_INSTR || rc == VINF_EM_RAW_GUEST_TRAP || rc == VINF_TRPM_XCPT_DISPATCHED, ("%Vrc\n", rc));
 #endif
-        Log2(("Failed IO at %VGv %x size %d\n", pCtx->eip, IoExitInfo.n.u16Port, uIOSize));
+        Log2(("Failed IO at %VGv %x size %d\n", pCtx->rip, IoExitInfo.n.u16Port, uIOSize));
         break;
     }
@@ -1679 +1679 @@
             &&  VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC|VM_FF_INTERRUPT_PIC)))
         {
-            pCtx->eip++;    /* skip hlt */
+            pCtx->rip++;    /* skip hlt */
             goto ResumeExecution;
         }
@@ -1705 +1705 @@
         Event.n.u8Vector = X86_XCPT_UD;
 
-        Log(("Forced #UD trap at %VGv\n", pCtx->eip));
+        Log(("Forced #UD trap at %VGv\n", pCtx->rip));
         SVMR0InjectEvent(pVM, pVMCB, pCtx, &Event);
 
@@ -1883 +1883 @@
     {
         RTGCPTR pbCode;
-        int rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->eip, &pbCode);
+        int rc = SELMValidateAndConvertCSAddr(pVM, pRegFrame->eflags, pRegFrame->ss, pRegFrame->cs, &pRegFrame->csHid, (RTGCPTR)pRegFrame->rip, &pbCode);
         if (VBOX_SUCCESS(rc))
         {
@@ -1898 +1898 @@
                 if (VBOX_SUCCESS(rc))
                 {
-                    pRegFrame->eip += cbOp; /* Move on to the next instruction. */
+                    pRegFrame->rip += cbOp; /* Move on to the next instruction. */
                 }
                 return rc;
@@ -1978 +1978 @@
         {
             RTGCPTR pbCode;
-            int rc = SELMValidateAndConvertCSAddr(pVM, pCtx->eflags, pCtx->ss, pCtx->cs, &pCtx->csHid, (RTGCPTR)pCtx->eip, &pbCode);
+            int rc = SELMValidateAndConvertCSAddr(pVM, pCtx->eflags, pCtx->ss, pCtx->cs, &pCtx->csHid, (RTGCPTR)pCtx->rip, &pbCode);
             if (VBOX_SUCCESS(rc))
             {

trunk/src/VBox/VMM/VMMR0/HWVMXR0.cpp

@@ -396 +396 @@
     uint32_t    iGate = VMX_EXIT_INTERRUPTION_INFO_VECTOR(intInfo);
     if (iGate == 0xE)
-        Log2(("VMXR0InjectEvent: Injecting interrupt %d at %VGv error code=%08x CR2=%08x intInfo=%08x\n", iGate, pCtx->eip, errCode, pCtx->cr2, intInfo));
+        Log2(("VMXR0InjectEvent: Injecting interrupt %d at %VGv error code=%08x CR2=%08x intInfo=%08x\n", iGate, pCtx->rip, errCode, pCtx->cr2, intInfo));
     else
     if (iGate < 0x20)
-        Log2(("VMXR0InjectEvent: Injecting interrupt %d at %VGv error code=%08x\n", iGate, pCtx->eip, errCode));
+        Log2(("VMXR0InjectEvent: Injecting interrupt %d at %VGv error code=%08x\n", iGate, pCtx->rip, errCode));
     else
     {
-        Log2(("INJ-EI: %x at %VGv\n", iGate, pCtx->eip));
+        Log2(("INJ-EI: %x at %VGv\n", iGate, pCtx->rip));
         Assert(!VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS));
         Assert(pCtx->eflags.u32 & X86_EFL_IF);
@@ -435 +435 @@
     if (pVM->hwaccm.s.Event.fPending)
     {
-        Log(("Reinjecting event %VX64 %08x at %VGv\n", pVM->hwaccm.s.Event.intInfo, pVM->hwaccm.s.Event.errCode, pCtx->eip));
+        Log(("Reinjecting event %VX64 %08x at %VGv\n", pVM->hwaccm.s.Event.intInfo, pVM->hwaccm.s.Event.errCode, pCtx->rip));
         STAM_COUNTER_INC(&pVM->hwaccm.s.StatIntReinject);
         rc = VMXR0InjectEvent(pVM, pCtx, pVM->hwaccm.s.Event.intInfo, 0, pVM->hwaccm.s.Event.errCode);
@@ -476 +476 @@
         }
         else
-            Log(("Pending interrupt blocked at %VGv by VM_FF_INHIBIT_INTERRUPTS!!\n", pCtx->eip));
+            Log(("Pending interrupt blocked at %VGv by VM_FF_INHIBIT_INTERRUPTS!!\n", pCtx->rip));
     }
 
@@ -1089 +1089 @@
     if (VM_FF_ISSET(pVM, VM_FF_INHIBIT_INTERRUPTS))
     {
-        Log(("VM_FF_INHIBIT_INTERRUPTS at %VGv successor %VGv\n", pCtx->eip, EMGetInhibitInterruptsPC(pVM)));
-        if (pCtx->eip != EMGetInhibitInterruptsPC(pVM))
+        Log(("VM_FF_INHIBIT_INTERRUPTS at %VGv successor %VGv\n", pCtx->rip, EMGetInhibitInterruptsPC(pVM)));
+        if (pCtx->rip != EMGetInhibitInterruptsPC(pVM))
         {
             /** @note we intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here.
@@ -1219 +1219 @@
 
             VMXReadVMCS(VMX_VMCS_GUEST_RIP, &val);
-            Log(("Old eip %VGv new %VGv\n", pCtx->eip, (RTGCPTR)val));
+            Log(("Old eip %VGv new %VGv\n", pCtx->rip, (RTGCPTR)val));
             VMXReadVMCS(VMX_VMCS_CTRL_PIN_EXEC_CONTROLS, &val);
             Log(("VMX_VMCS_CTRL_PIN_EXEC_CONTROLS   %08x\n", val));
@@ -1369 +1369 @@
     {
         Assert(uInterruptState <= 2);    /* only sti & mov ss */
-        Log(("uInterruptState %x eip=%VGv\n", uInterruptState, pCtx->eip));
-        EMSetInhibitInterruptsPC(pVM, pCtx->eip);
+        Log(("uInterruptState %x eip=%VGv\n", uInterruptState, pCtx->rip));
+        EMSetInhibitInterruptsPC(pVM, pCtx->rip);
     }
     else
@@ -1419 +1419 @@
         &&  VMX_EXIT_INTERRUPTION_INFO_TYPE(pVM->hwaccm.s.Event.intInfo) != VMX_EXIT_INTERRUPTION_INFO_TYPE_SW)
     {
-        Log(("Pending inject %VX64 at %08x exit=%08x intInfo=%08x exitQualification=%08x\n", pVM->hwaccm.s.Event.intInfo, pCtx->eip, exitReason, intInfo, exitQualification));
+        Log(("Pending inject %VX64 at %VGv exit=%08x intInfo=%08x exitQualification=%08x\n", pVM->hwaccm.s.Event.intInfo, pCtx->rip, exitReason, intInfo, exitQualification));
         pVM->hwaccm.s.Event.fPending = true;
         /* Error code present? */
@@ -1442 +1442 @@
     Log2(("Interruption error code %d\n", errCode));
     Log2(("IntInfo = %08x\n", intInfo));
-    Log2(("New EIP=%VGv\n", pCtx->eip));
+    Log2(("New EIP=%VGv\n", pCtx->rip));
 
     /* Some cases don't need a complete resync of the guest CPU state; handle them here. */
@@ -1481 +1481 @@
                 uint32_t oldCR0;
 
-                Log(("#NM fault at %VGv error code %x\n", pCtx->eip, errCode));
+                Log(("#NM fault at %VGv error code %x\n", pCtx->rip, errCode));
 
                 /** @todo don't intercept #NM exceptions anymore when we've activated the guest FPU state. */
@@ -1521 +1521 @@
                 /* Forward it to our trap handler first, in case our shadow pages are out of sync. */
                 rc = PGMTrap0eHandler(pVM, errCode, CPUMCTX2CORE(pCtx), (RTGCPTR)exitQualification);
-                Log2(("PGMTrap0eHandler %VGv returned %Vrc\n", pCtx->eip, rc));
+                Log2(("PGMTrap0eHandler %VGv returned %Vrc\n", pCtx->rip, rc));
                 if (rc == VINF_SUCCESS)
                 {   /* We've successfully synced our shadow pages, so let's just continue execution. */
-                    Log2(("Shadow page fault at %VGv cr2=%VGv error code %x\n", pCtx->eip, exitQualification ,errCode));
+                    Log2(("Shadow page fault at %VGv cr2=%VGv error code %x\n", pCtx->rip, exitQualification ,errCode));
                     STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitShadowPF);
 
@@ -1571 +1571 @@
                     break;
                 }
-                Log(("Trap %x at %VGv\n", vector, pCtx->eip));
+                Log(("Trap %x at %VGv\n", vector, pCtx->rip));
                 rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
                 AssertRC(rc);
@@ -1605 +1605 @@
                 }
 
-                Log(("Trap %x at %VGv\n", vector, pCtx->eip));
+                Log(("Trap %x at %VGv\n", vector, pCtx->rip));
                 rc = VMXR0InjectEvent(pVM, pCtx, VMX_VMCS_CTRL_ENTRY_IRQ_INFO_FROM_EXIT_INT_INFO(intInfo), cbInstr, errCode);
                 AssertRC(rc);
@@ -1632 +1632 @@
     case VMX_EXIT_IRQ_WINDOW:           /* 7 Interrupt window. */
         /* Clear VM-exit on IF=1 change. */
-        Log2(("VMX_EXIT_IRQ_WINDOW %VGv\n", pCtx->eip));
+        Log2(("VMX_EXIT_IRQ_WINDOW %VGv\n", pCtx->rip));
         pVM->hwaccm.s.vmx.proc_ctls &= ~VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT;
         rc = VMXWriteVMCS(VMX_VMCS_CTRL_PROC_EXEC_CONTROLS, pVM->hwaccm.s.vmx.proc_ctls);
@@ -1642 +1642 @@
         STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitInvd);
         /* Skip instruction and continue directly. */
-        pCtx->eip += cbInstr;
+        pCtx->rip += cbInstr;
         /* Continue execution.*/
         STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
@@ -1656 +1656 @@
             /* Update EIP and continue execution. */
             Assert(cbInstr == 2);
-            pCtx->eip += cbInstr;
+            pCtx->rip += cbInstr;
             STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
             goto ResumeExecution;
@@ -1674 +1674 @@
             /* Update EIP and continue execution. */
             Assert(cbInstr == 2);
-            pCtx->eip += cbInstr;
+            pCtx->rip += cbInstr;
             STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
             goto ResumeExecution;
@@ -1691 +1691 @@
         {
             /* Update EIP and continue execution. */
-            pCtx->eip += cbInstr;
+            pCtx->rip += cbInstr;
             STAM_PROFILE_ADV_STOP(&pVM->hwaccm.s.StatExit, x);
             goto ResumeExecution;
@@ -1704 +1704 @@
         {
         case VMX_EXIT_QUALIFICATION_CRX_ACCESS_WRITE:
-            Log2(("VMX: %VGv mov cr%d, x\n", pCtx->eip, VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification)));
+            Log2(("VMX: %VGv mov cr%d, x\n", pCtx->rip, VMX_EXIT_QUALIFICATION_CRX_REGISTER(exitQualification)));
             STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitCRxWrite);
             rc = EMInterpretCRxWrite(pVM, CPUMCTX2CORE(pCtx),
@@ -1760 +1760 @@
         /* Update EIP if no error occurred. */
         if (VBOX_SUCCESS(rc))
-            pCtx->eip += cbInstr;
+            pCtx->rip += cbInstr;
 
         if (rc == VINF_SUCCESS)
@@ -1794 +1794 @@
         /* Update EIP if no error occurred. */
         if (VBOX_SUCCESS(rc))
-            pCtx->eip += cbInstr;
+            pCtx->rip += cbInstr;
 
         if (rc == VINF_SUCCESS)
@@ -1839 +1839 @@
             if (fIOWrite)
             {
-                Log2(("IOMInterpretOUTSEx %VGv %x size=%d\n", pCtx->eip, uPort, cbSize));
+                Log2(("IOMInterpretOUTSEx %VGv %x size=%d\n", pCtx->rip, uPort, cbSize));
                 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringWrite);
                 rc = IOMInterpretOUTSEx(pVM, CPUMCTX2CORE(pCtx), uPort, prefix, cbSize);
@@ -1845 +1845 @@
             else
             {
-                Log2(("IOMInterpretINSEx  %VGv %x size=%d\n", pCtx->eip, uPort, cbSize));
+                Log2(("IOMInterpretINSEx  %VGv %x size=%d\n", pCtx->rip, uPort, cbSize));
                 STAM_COUNTER_INC(&pVM->hwaccm.s.StatExitIOStringRead);
                 rc = IOMInterpretINSEx(pVM, CPUMCTX2CORE(pCtx), uPort, prefix, cbSize);
@@ -1882 +1882 @@
         {
             /* Update EIP and continue execution. */
-            pCtx->eip += cbInstr;
+            pCtx->rip += cbInstr;
             if (RT_LIKELY(rc == VINF_SUCCESS))
             {
@@ -1942 +1942 @@
             &&  VM_FF_ISPENDING(pVM, (VM_FF_INTERRUPT_APIC|VM_FF_INTERRUPT_PIC)))
         {
-            pCtx->eip++;    /* skip hlt */
+            pCtx->rip++;    /* skip hlt */
             goto ResumeExecution;
         }