Changeset 97178 in vbox for trunk/src/VBox/VMM/VMMR0

Timestamp:

Oct 17, 2022 9:06:03 PM (3 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

154153

Message:

VMM/CPUM,EM,HM,IEM,++: Moved VMCPU_FF_INHIBIT_INTERRUPTS and VMCPU_FF_BLOCK_NMIS to CPUMCTX::fInhibit. Moved ldtr and tr up to the CPUMCTXCORE area in hope for better cache alignment of rip, rflags and crX register fields. bugref:9941

File:

• trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp (modified) (8 diffs)

trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp

@@ -2692 +2692 @@
 
         if (fWhat & CPUMCTX_EXTRN_INHIBIT_INT)
-        {
-            if (pVmcbCtrl->IntShadow.n.u1IntShadow)
-                EMSetInhibitInterruptsPC(pVCpu, pVmcbGuest->u64RIP);
-            else if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
-                VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
-        }
+            CPUMUpdateInterruptShadowEx(pCtx, pVmcbCtrl->IntShadow.n.u1IntShadow, pVmcbGuest->u64RIP);
 
         if (fWhat & CPUMCTX_EXTRN_RIP)
@@ -3504 +3499 @@
 
 /**
- * Checks if the guest (or nested-guest) has an interrupt shadow active right
- * now.
- *
- * @returns @c true if the interrupt shadow is active, @c false otherwise.
- * @param   pVCpu   The cross context virtual CPU structure.
- *
- * @remarks No-long-jump zone!!!
- * @remarks Has side-effects with VMCPU_FF_INHIBIT_INTERRUPTS force-flag.
- */
-static bool hmR0SvmIsIntrShadowActive(PVMCPUCC pVCpu)
-{
-    /*
-     * Instructions like STI and MOV SS inhibit interrupts till the next instruction
-     * completes. Check if we should inhibit interrupts or clear any existing
-     * interrupt inhibition.
-     */
-    if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS))
-    {
-        if (pVCpu->cpum.GstCtx.rip != EMGetInhibitInterruptsPC(pVCpu))
-        {
-            /*
-             * We can clear the inhibit force flag as even if we go back to the recompiler
-             * without executing guest code in AMD-V, the flag's condition to be cleared is
-             * met and thus the cleared state is correct.
-             */
-            VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
-            return false;
-        }
-        return true;
-    }
-    return false;
-}
-
-
-/**
  * Sets the virtual interrupt intercept control in the VMCB.
  *
@@ -3612 +3572 @@
 
     bool const fGif        = CPUMGetGuestGif(pCtx);
-    bool const fIntShadow  = hmR0SvmIsIntrShadowActive(pVCpu);
-    bool const fBlockNmi   = VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
+    bool const fIntShadow  = CPUMIsInInterruptShadowWithUpdate(pCtx);
+    bool const fBlockNmi   = CPUMAreInterruptsInhibitedByNmi(pCtx);
 
     Log4Func(("fGif=%RTbool fBlockNmi=%RTbool fIntShadow=%RTbool fIntPending=%RTbool fNmiPending=%RTbool\n",
@@ -3734 +3694 @@
     Assert(!VMMRZCallRing3IsEnabled(pVCpu));
 
-    bool const fIntShadow = hmR0SvmIsIntrShadowActive(pVCpu);
+    bool const fIntShadow = CPUMIsInInterruptShadowWithUpdate(&pVCpu->cpum.GstCtx);
 #ifdef VBOX_STRICT
     PCCPUMCTX  pCtx       = &pVCpu->cpum.GstCtx;
@@ -3782 +3742 @@
          * VM-exit to determine the state.
          */
-        if (    Event.n.u3Type   == SVM_EVENT_NMI
-            &&  Event.n.u8Vector == X86_XCPT_NMI
-            && !VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
-        {
-            VMCPU_FF_SET(pVCpu, VMCPU_FF_BLOCK_NMIS);
-        }
+        if (   Event.n.u3Type   == SVM_EVENT_NMI
+            && Event.n.u8Vector == X86_XCPT_NMI)
+            CPUMSetInterruptInhibitingByNmi(&pVCpu->cpum.GstCtx);
 
         /*
@@ -3809 +3766 @@
      * but we still need to intercept IRET in order to eventually clear NMI inhibition.
      */
-    if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_BLOCK_NMIS))
+    if (CPUMAreInterruptsInhibitedByNmi(&pVCpu->cpum.GstCtx))
         hmR0SvmSetCtrlIntercept(pVmcb, SVM_CTRL_INTERCEPT_IRET);
 
@@ -6711 +6668 @@
                     /* If we are re-injecting an NMI, clear NMI blocking. */
                     if (pVmcb->ctrl.ExitIntInfo.n.u3Type == SVM_EVENT_NMI)
-                        VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_BLOCK_NMIS);
+                        CPUMClearInterruptInhibitingByNmi(&pVCpu->cpum.GstCtx);
 
                     /* Determine a vectoring #PF condition, see comment in hmR0SvmExitXcptPF(). */
@@ -6802 +6759 @@
 DECLINLINE(void) hmR0SvmAdvanceRip(PVMCPUCC pVCpu, uint32_t cb)
 {
-    PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
-    pCtx->rip += cb;
-
-    /* Update interrupt shadow. */
-    if (   VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
-        && pCtx->rip != EMGetInhibitInterruptsPC(pVCpu))
-        VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
+    pVCpu->cpum.GstCtx.rip += cb;
+    CPUMClearInterruptShadow(&pVCpu->cpum.GstCtx);
+    /** @todo clear RF. */
 }