Changeset 97197 in vbox for trunk/src/VBox/VMM/VMMR0

Timestamp:

Oct 18, 2022 11:09:55 AM (2 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

154172

Message:

VMM/PGM,IEM,EM: Changed FNPGMRZPHYSPFHANDLER, PGMTrap0eHandler and PGMR0Trap0eHandlerNPMisconfig to take PCPUMCTX instead of PCPUMCTXCORE parameters; dropped PCPUMCTXCORE parameters from IEMExecOneBypassEx, PGMInterpretInstruction and EMInterpretInstruction together with some associated cleanups.

Location:

trunk/src/VBox/VMM/VMMR0

Files:

• HMSVMR0.cpp (modified) (4 diffs)
• PGMR0.cpp (modified) (3 diffs)

trunk/src/VBox/VMM/VMMR0/HMSVMR0.cpp

@@ -7570 +7570 @@
      */
     /** @todo Decode assist.  */
-    VBOXSTRICTRC rc = EMInterpretInstruction(pVCpu, CPUMCTX2CORE(pCtx), 0 /* pvFault */);
+    VBOXSTRICTRC rc = EMInterpretInstruction(pVCpu);
     Log5(("hmR0SvmExitReadDRx: Emulated DRx access: rc=%Rrc\n", VBOXSTRICTRC_VAL(rc)));
     if (RT_LIKELY(rc == VINF_SUCCESS))
@@ -7949 +7949 @@
         {
 
-            rcStrict = PGMR0Trap0eHandlerNPMisconfig(pVM, pVCpu, enmNestedPagingMode, CPUMCTX2CORE(pCtx), GCPhysFaultAddr,
-                                                     u32ErrCode);
+            rcStrict = PGMR0Trap0eHandlerNPMisconfig(pVM, pVCpu, enmNestedPagingMode, pCtx, GCPhysFaultAddr, u32ErrCode);
 
             /*
@@ -8293 +8292 @@
 
     TRPMAssertXcptPF(pVCpu, uFaultAddress, uErrCode);
-    int rc = PGMTrap0eHandler(pVCpu, uErrCode, CPUMCTX2CORE(pCtx), (RTGCPTR)uFaultAddress);
+    int rc = PGMTrap0eHandler(pVCpu, uErrCode, pCtx, (RTGCPTR)uFaultAddress);
 
     Log4Func(("#PF: rc=%Rrc\n", rc));
@@ -9113 +9112 @@
            instruction(s) when interrupt inhibition is set as part of emulating the VMRUN
            instruction itself, see @bugref{7243#c126} */
-        rcStrict = IEMExecOneBypassEx(pVCpu, CPUMCTX2CORE(&pVCpu->cpum.GstCtx), NULL /* pcbWritten */);
+        rcStrict = IEMExecOneBypassEx(pVCpu, NULL /* pcbWritten */);
     }
     STAM_PROFILE_ADV_STOP(&pVCpu->hm.s.StatExitVmentry, z);

trunk/src/VBox/VMM/VMMR0/PGMR0.cpp

@@ -1279 +1279 @@
  *                              EMT.
  * @param   enmShwPagingMode    Paging mode for the nested page tables.
- * @param   pRegFrame           Trap register frame.
+ * @param   pCtx                Pointer to the register context for the CPU.
  * @param   GCPhysFault         The fault address.
  * @param   uErr                The error code, UINT32_MAX if not available
@@ -1285 +1285 @@
  */
 VMMR0DECL(VBOXSTRICTRC) PGMR0Trap0eHandlerNPMisconfig(PGVM pGVM, PGVMCPU pGVCpu, PGMMODE enmShwPagingMode,
-                                                      PCPUMCTXCORE pRegFrame, RTGCPHYS GCPhysFault, uint32_t uErr)
+                                                      PCPUMCTX pCtx, RTGCPHYS GCPhysFault, uint32_t uErr)
 {
 #ifdef PGM_WITH_MMIO_OPTIMIZATIONS
@@ -1330 +1330 @@
 
                     Log6(("PGMR0Trap0eHandlerNPMisconfig: calling %p(,%#x,,%RGp,%p)\n", pHandlerType->pfnPfHandler, uErr, GCPhysFault, uUser));
-                    rc = pHandlerType->pfnPfHandler(pGVM, pGVCpu, uErr == UINT32_MAX ? RTGCPTR_MAX : uErr, pRegFrame,
+                    rc = pHandlerType->pfnPfHandler(pGVM, pGVCpu, uErr == UINT32_MAX ? RTGCPTR_MAX : uErr, pCtx,
                                                     GCPhysFault, GCPhysFault, uUser);