Changeset 97203 in vbox

Timestamp:

Oct 18, 2022 12:28:22 PM (3 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

154179

Message:

VMM/SELM,DIS: Changed SELMToFlat and SELMToFlatEx to use PCPUMCTX instead of PCPUMCTXCORE and use X86_SREG_XX indexes instead of DISSELREG.

Location:

trunk

Files:

• include/VBox/dis.h (modified) (1 diff)
• include/VBox/vmm/selm.h (modified) (2 diffs)
• src/VBox/Disassembler/DisasmReg.cpp (modified) (1 diff)
• src/VBox/VMM/VMMAll/SELMAll.cpp (modified) (6 diffs)
• src/VBox/VMM/VMMR3/EMHM.cpp (modified) (1 diff)

trunk/include/VBox/dis.h

@@ -790 +790 @@
 DISDECL(int) DISFetchReg64(PCCPUMCTXCORE pCtx, unsigned reg64, uint64_t *pVal);
 DISDECL(int) DISFetchRegSeg(PCCPUMCTXCORE pCtx, DISSELREG sel, RTSEL *pVal);
-DISDECL(int) DISFetchRegSegEx(PCPUMCTXCORE pCtx, DISSELREG sel, PCPUMSELREG *ppSelReg);
 DISDECL(int) DISWriteReg8(PCPUMCTXCORE pRegFrame, unsigned reg8, uint8_t val8);
 DISDECL(int) DISWriteReg16(PCPUMCTXCORE pRegFrame, unsigned reg32, uint16_t val16);

trunk/include/VBox/vmm/selm.h

@@ -54 +54 @@
 
 VMMDECL(int)            SELMGetTSSInfo(PVM pVM, PVMCPU pVCpu, PRTGCUINTPTR pGCPtrTss, PRTGCUINTPTR pcbTss, bool *pfCanHaveIOBitmap);
-VMMDECL(RTGCPTR)        SELMToFlat(PVMCC pVM, DISSELREG SelReg, PCPUMCTXCORE pCtxCore, RTGCPTR Addr);
+VMMDECL(RTGCPTR)        SELMToFlat(PVMCPUCC pVCpu, unsigned idxSeg, PCPUMCTX pCtx, RTGCPTR Addr);
 VMMDECL(RTGCPTR)        SELMToFlatBySel(PVM pVM, RTSEL Sel, RTGCPTR Addr);
 
@@ -76 +76 @@
 /** @} */
 
-VMMDECL(int)            SELMToFlatEx(PVMCPU pVCpu, DISSELREG SelReg, PCPUMCTXCORE pCtxCore, RTGCPTR Addr, uint32_t fFlags,
-                                     PRTGCPTR ppvGC);
+VMMDECL(int)            SELMToFlatEx(PVMCPU pVCpu, unsigned idxSeg, PCPUMCTX pCtx, RTGCPTR Addr, uint32_t fFlags, PRTGCPTR ppvGC);
 VMMDECL(int)            SELMValidateAndConvertCSAddr(PVMCPU pVCpu, X86EFLAGS eflags, RTSEL SelCPL, RTSEL SelCS,
                                                      PCPUMSELREG pSRegCS, RTGCPTR Addr, PRTGCPTR ppvFlat);

trunk/src/VBox/Disassembler/DisasmReg.cpp

@@ -452 +452 @@
 
 /**
- * Returns the value of the specified segment register including a pointer to the hidden register in the supplied cpu context
- *
- */
-DISDECL(int) DISFetchRegSegEx(PCPUMCTXCORE pCtx, DISSELREG sel, PCPUMSELREG *ppSelReg)
-{
-    AssertReturnStmt((unsigned)sel < RT_ELEMENTS(g_aRegSegIndex), *ppSelReg = NULL, VERR_INVALID_PARAMETER);
-    *ppSelReg = (CPUMSELREG *)((uintptr_t)pCtx + g_aRegHidSegIndex[sel]);
-    return VINF_SUCCESS;
-}
-
-/**
  * Updates the value of the specified 64 bits general purpose register
  *

trunk/src/VBox/VMM/VMMAll/SELMAll.cpp

@@ -56 +56 @@
  *
  * @returns Flat address.
- * @param   pVM         The cross context VM structure.
- * @param   SelReg      Selector register
- * @param   pCtxCore    CPU context
+ * @param   pVCpu       The cross context virtual CPU structure.
+ * @param   idxSeg      The selector register to use (X86_SREG_XXX).
+ * @param   pCtx        Pointer to the register context for the CPU.
  * @param   Addr        Address part.
  */
-VMMDECL(RTGCPTR) SELMToFlat(PVMCC pVM, DISSELREG SelReg, PCPUMCTXCORE pCtxCore, RTGCPTR Addr)
-{
-    PCPUMSELREG    pSReg;
-    PVMCPUCC       pVCpu = VMMGetCpu(pVM);
-
-    int rc = DISFetchRegSegEx(pCtxCore, SelReg, &pSReg); AssertRC(rc);
+VMMDECL(RTGCPTR) SELMToFlat(PVMCPUCC pVCpu, unsigned idxSeg, PCPUMCTX pCtx, RTGCPTR Addr)
+{
+    Assert(idxSeg < RT_ELEMENTS(pCtx->aSRegs));
+    PCPUMSELREG pSReg = &pCtx->aSRegs[idxSeg];
 
     /*
      * Deal with real & v86 mode first.
      */
-    if (    pCtxCore->eflags.Bits.u1VM
+    if (    pCtx->eflags.Bits.u1VM
         ||  CPUMIsGuestInRealMode(pVCpu))
     {
@@ -83 +81 @@
 
     Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, pSReg));
-    Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtxCore->cs));
+    Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs));
 
     /* 64 bits mode: CS, DS, ES and SS are treated as if each segment base is 0
        (Intel(r) 64 and IA-32 Architectures Software Developer's Manual: 3.4.2.1). */
-    if (    pCtxCore->cs.Attr.n.u1Long
+    if (    pCtx->cs.Attr.n.u1Long
         &&  CPUMIsGuestInLongMode(pVCpu))
     {
-        switch (SelReg)
-        {
-            case DISSELREG_FS:
-            case DISSELREG_GS:
+        switch (idxSeg)
+        {
+            case X86_SREG_FS:
+            case X86_SREG_GS:
                 return (RTGCPTR)(pSReg->u64Base + Addr);
 
@@ -114 +112 @@
  * @returns VBox status
  * @param   pVCpu       The cross context virtual CPU structure.
- * @param   SelReg      Selector register.
- * @param   pCtxCore    CPU context.
+ * @param   idxSeg      The selector register to use (X86_SREG_XXX).
+ * @param   pCtx        Pointer to the register context for the CPU.
  * @param   Addr        Address part.
  * @param   fFlags      SELMTOFLAT_FLAGS_*
@@ -121 +119 @@
  * @param   ppvGC       Where to store the GC flat address.
  */
-VMMDECL(int) SELMToFlatEx(PVMCPU pVCpu, DISSELREG SelReg, PCPUMCTXCORE pCtxCore, RTGCPTR Addr, uint32_t fFlags, PRTGCPTR ppvGC)
-{
-    /*
-     * Fetch the selector first.
-     */
-    PCPUMSELREG pSReg;
-    int rc = DISFetchRegSegEx(pCtxCore, SelReg, &pSReg);
-    AssertRCReturn(rc, rc); AssertPtr(pSReg);
+VMMDECL(int) SELMToFlatEx(PVMCPU pVCpu, unsigned idxSeg, PCPUMCTX pCtx, RTGCPTR Addr, uint32_t fFlags, PRTGCPTR ppvGC)
+{
+    AssertReturn(idxSeg < RT_ELEMENTS(pCtx->aSRegs), VERR_INVALID_PARAMETER);
+    PCPUMSELREG pSReg = &pCtx->aSRegs[idxSeg];
 
     /*
      * Deal with real & v86 mode first.
      */
-    if (    pCtxCore->eflags.Bits.u1VM
+    if (    pCtx->eflags.Bits.u1VM
         ||  CPUMIsGuestInRealMode(pVCpu))
     {
@@ -148 +142 @@
 
     Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, pSReg));
-    Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtxCore->cs));
+    Assert(CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, &pCtx->cs));
 
     /* 64 bits mode: CS, DS, ES and SS are treated as if each segment base is 0
@@ -154 +148 @@
     RTGCPTR  pvFlat;
     bool     fCheckLimit   = true;
-    if (    pCtxCore->cs.Attr.n.u1Long
+    if (    pCtx->cs.Attr.n.u1Long
         &&  CPUMIsGuestInLongMode(pVCpu))
     {
         fCheckLimit = false;
-        switch (SelReg)
-        {
-            case DISSELREG_FS:
-            case DISSELREG_GS:
+        switch (idxSeg)
+        {
+            case X86_SREG_FS:
+            case X86_SREG_GS:
                 pvFlat = pSReg->u64Base + Addr;
                 break;

trunk/src/VBox/VMM/VMMR3/EMHM.cpp

@@ -301 +301 @@
         /** @todo this should be skipped! */
         CPUM_IMPORT_EXTRN_RET(pVCpu, CPUMCTX_EXTRN_CS | CPUMCTX_EXTRN_SS);
-        rc = PGMPrefetchPage(pVCpu, SELMToFlat(pVM, DISSELREG_CS, CPUMCTX2CORE(&pVCpu->cpum.GstCtx), pVCpu->cpum.GstCtx.rip));
+        rc = PGMPrefetchPage(pVCpu, SELMToFlat(pVCpu, X86_SREG_CS, &pVCpu->cpum.GstCtx, pVCpu->cpum.GstCtx.rip));
         if (rc == VINF_SUCCESS)
-            rc = PGMPrefetchPage(pVCpu, SELMToFlat(pVM, DISSELREG_SS, CPUMCTX2CORE(&pVCpu->cpum.GstCtx), pVCpu->cpum.GstCtx.rsp));
+            rc = PGMPrefetchPage(pVCpu, SELMToFlat(pVCpu, X86_SREG_SS, &pVCpu->cpum.GstCtx, pVCpu->cpum.GstCtx.rsp));
         if (rc != VINF_SUCCESS)
         {