VirtualBox

Changeset 97208 in vbox


Ignore:
Timestamp:
Oct 18, 2022 1:56:59 PM (2 years ago)
Author:
vboxsync
svn:sync-xref-src-repo-rev:
154184
Message:

VMM/IEM,EM,HMVMX: Replaced EMInterpretDRxWrite and EMInterpretDRxRead with IEMExecDecodedDrXWrite/Read equivalents.

Location:
trunk
Files:
6 edited

Legend:

Unmodified
Added
Removed

  • trunk/include/VBox/vmm/em.h

    r97206 r97208  
    273273VMM_INT_DECL(VBOXSTRICTRC)      EMInterpretInstruction(PVMCPUCC pVCpu);
    274274VMM_INT_DECL(VBOXSTRICTRC)      EMInterpretInstructionDisasState(PVMCPUCC pVCpu, PDISCPUSTATE pDis, uint64_t rip);
    275 VMM_INT_DECL(int)               EMInterpretDRxWrite(PVMCC pVM, PVMCPUCC pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegDrx, uint32_t SrcRegGen);
    276 VMM_INT_DECL(int)               EMInterpretDRxRead(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegDrx);
    277275/** @} */
    278276

  • trunk/include/VBox/vmm/iem.h

    r97200 r97208  
    335335VMM_INT_DECL(VBOXSTRICTRC)  IEMExecDecodedMovCRxWrite(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iCrReg, uint8_t iGReg);
    336336VMM_INT_DECL(VBOXSTRICTRC)  IEMExecDecodedMovCRxRead(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iGReg, uint8_t iCrReg);
     337VMM_INT_DECL(VBOXSTRICTRC)  IEMExecDecodedMovDRxWrite(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iDrReg, uint8_t iGReg);
     338VMM_INT_DECL(VBOXSTRICTRC)  IEMExecDecodedMovDRxRead(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iGReg, uint8_t iDrReg);
    337339VMM_INT_DECL(VBOXSTRICTRC)  IEMExecDecodedClts(PVMCPUCC pVCpu, uint8_t cbInstr);
    338340VMM_INT_DECL(VBOXSTRICTRC)  IEMExecDecodedLmsw(PVMCPUCC pVCpu, uint8_t cbInstr, uint16_t uValue, RTGCPTR GCPtrEffDst);

  • trunk/src/VBox/VMM/VMMAll/EMAll.cpp

    r97206 r97208  
    10171017}
    10181018
    1019 
    1020 
    1021 
    1022 /*
    1023  *
    1024  * Old interpreter primitives used by HM, move/eliminate later.
    1025  * Old interpreter primitives used by HM, move/eliminate later.
    1026  * Old interpreter primitives used by HM, move/eliminate later.
    1027  * Old interpreter primitives used by HM, move/eliminate later.
    1028  * Old interpreter primitives used by HM, move/eliminate later.
    1029  *
    1030  */
    1031 
    1032 /* VT-x only: */
    1033 
    1034 /**
    1035  * Interpret DRx write.
    1036  *
    1037  * @returns VBox status code.
    1038  * @param   pVM         The cross context VM structure.
    1039  * @param   pVCpu       The cross context virtual CPU structure.
    1040  * @param   pRegFrame   The register frame.
    1041  * @param   DestRegDrx  DRx register index (USE_REG_DR*)
    1042  * @param   SrcRegGen   General purpose register index (USE_REG_E**))
    1043  *
    1044  */
    1045 VMM_INT_DECL(int) EMInterpretDRxWrite(PVMCC pVM, PVMCPUCC pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegDrx, uint32_t SrcRegGen)
    1046 {
    1047     Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
    1048     uint64_t uNewDrX;
    1049     int      rc;
    1050     NOREF(pVM);
    1051 
    1052     if (CPUMIsGuestIn64BitCode(pVCpu))
    1053         rc = DISFetchReg64(pRegFrame, SrcRegGen, &uNewDrX);
    1054     else
    1055     {
    1056         uint32_t val32;
    1057         rc = DISFetchReg32(pRegFrame, SrcRegGen, &val32);
    1058         uNewDrX = val32;
    1059     }
    1060 
    1061     if (RT_SUCCESS(rc))
    1062     {
    1063         if (DestRegDrx == 6)
    1064         {
    1065             uNewDrX |= X86_DR6_RA1_MASK;
    1066             uNewDrX &= ~X86_DR6_RAZ_MASK;
    1067         }
    1068         else if (DestRegDrx == 7)
    1069         {
    1070             uNewDrX |= X86_DR7_RA1_MASK;
    1071             uNewDrX &= ~X86_DR7_RAZ_MASK;
    1072         }
    1073 
    1074         /** @todo we don't fail if illegal bits are set/cleared for e.g. dr7 */
    1075         rc = CPUMSetGuestDRx(pVCpu, DestRegDrx, uNewDrX);
    1076         if (RT_SUCCESS(rc))
    1077             return rc;
    1078         AssertMsgFailed(("CPUMSetGuestDRx %d failed\n", DestRegDrx));
    1079     }
    1080     return VERR_EM_INTERPRETER;
    1081 }
    1082 
    1083 
    1084 /**
    1085  * Interpret DRx read.
    1086  *
    1087  * @returns VBox status code.
    1088  * @param   pVM         The cross context VM structure.
    1089  * @param   pVCpu       The cross context virtual CPU structure.
    1090  * @param   pRegFrame   The register frame.
    1091  * @param   DestRegGen  General purpose register index (USE_REG_E**))
    1092  * @param   SrcRegDrx   DRx register index (USE_REG_DR*)
    1093  */
    1094 VMM_INT_DECL(int) EMInterpretDRxRead(PVM pVM, PVMCPU pVCpu, PCPUMCTXCORE pRegFrame, uint32_t DestRegGen, uint32_t SrcRegDrx)
    1095 {
    1096     uint64_t val64;
    1097     Assert(pRegFrame == CPUMGetGuestCtxCore(pVCpu));
    1098     NOREF(pVM);
    1099 
    1100     int rc = CPUMGetGuestDRx(pVCpu, SrcRegDrx, &val64);
    1101     AssertMsgRCReturn(rc, ("CPUMGetGuestDRx %d failed\n", SrcRegDrx), VERR_EM_INTERPRETER);
    1102     if (CPUMIsGuestIn64BitCode(pVCpu))
    1103         rc = DISWriteReg64(pRegFrame, DestRegGen, val64);
    1104     else
    1105         rc = DISWriteReg32(pRegFrame, DestRegGen, (uint32_t)val64);
    1106 
    1107     if (RT_SUCCESS(rc))
    1108         return VINF_SUCCESS;
    1109 
    1110     return VERR_EM_INTERPRETER;
    1111 }
    1112 

  • trunk/src/VBox/VMM/VMMAll/IEMAll.cpp

    r97200 r97208  
    1079810798
    1079910799/**
     10800 * Interface for HM and EM to write to a DRx register.
     10801 *
     10802 * @returns Strict VBox status code.
     10803 * @param   pVCpu       The cross context virtual CPU structure.
     10804 * @param   cbInstr     The instruction length in bytes.
     10805 * @param   iDrReg      The debug register number (destination).
     10806 * @param   iGReg       The general purpose register number (source).
     10807 *
     10808 * @remarks In ring-0 not all of the state needs to be synced in.
     10809 */
     10810VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedMovDRxWrite(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iDrReg, uint8_t iGReg)
     10811{
     10812    IEMEXEC_ASSERT_INSTR_LEN_RETURN(cbInstr, 2);
     10813    IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK);
     10814    Assert(iDrReg < 8);
     10815    Assert(iGReg < 16);
     10816
     10817    iemInitExec(pVCpu, false /*fBypassHandlers*/);
     10818    VBOXSTRICTRC rcStrict = IEM_CIMPL_CALL_2(iemCImpl_mov_Dd_Rd, iDrReg, iGReg);
     10819    Assert(!pVCpu->iem.s.cActiveMappings);
     10820    return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
     10821}
     10822
     10823
     10824/**
     10825 * Interface for HM and EM to read from a DRx register.
     10826 *
     10827 * @returns Strict VBox status code.
     10828 * @param   pVCpu       The cross context virtual CPU structure.
     10829 * @param   cbInstr     The instruction length in bytes.
     10830 * @param   iGReg       The general purpose register number (destination).
     10831 * @param   iDrReg      The debug register number (source).
     10832 *
     10833 * @remarks In ring-0 not all of the state needs to be synced in.
     10834 */
     10835VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedMovDRxRead(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iGReg, uint8_t iDrReg)
     10836{
     10837    IEMEXEC_ASSERT_INSTR_LEN_RETURN(cbInstr, 2);
     10838    IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK);
     10839    Assert(iDrReg < 8);
     10840    Assert(iGReg < 16);
     10841
     10842    iemInitExec(pVCpu, false /*fBypassHandlers*/);
     10843    VBOXSTRICTRC rcStrict = IEM_CIMPL_CALL_2(iemCImpl_mov_Rd_Dd, iGReg, iDrReg);
     10844    Assert(!pVCpu->iem.s.cActiveMappings);
     10845    return iemUninitExecAndFiddleStatusAndMaybeReenter(pVCpu, rcStrict);
     10846}
     10847
     10848
     10849/**
    1080010850 * Interface for HM and EM to clear the CR0[TS] bit.
    1080110851 *

  • trunk/src/VBox/VMM/VMMAll/IEMAllCImpl.cpp

    r97196 r97208  
    64276427            drX &= ~X86_DR7_RAZ_MASK;
    64286428            break;
    6429         IEM_NOT_REACHED_DEFAULT_CASE_RET(); /* call checks */
     6429        IEM_NOT_REACHED_DEFAULT_CASE_RET(); /* caller checks */
    64306430    }
    64316431
    … …  
    64396439        IEM_SVM_UPDATE_NRIP(pVCpu);
    64406440        IEM_SVM_VMEXIT_RET(pVCpu, SVM_EXIT_READ_DR0 + (iDrReg & 0xf),
    6441                               IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSvmDecodeAssists ? (iGReg & 7) : 0, 0 /* uExitInfo2 */);
     6441                           IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fSvmDecodeAssists ? (iGReg & 7) : 0, 0 /* uExitInfo2 */);
    64426442    }
    64436443

  • trunk/src/VBox/VMM/VMMAll/VMXAllTemplate.cpp.h

    r97206 r97208  
    91709170
    91719171    /*
    9172      * EMInterpretDRx[Write|Read]() calls CPUMIsGuestIn64BitCode() which requires EFER MSR, CS.
    9173      * The EFER MSR is always up-to-date.
    9174      * Update the segment registers and DR7 from the CPU.
     9172     * Import state.  We must have DR7 loaded here as it's always consulted,
     9173     * both for reading and writing.  The other debug registers are never
     9174     * exported as such.
    91759175     */
    9176     PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
    9177     vmxHCReadToTransient<HMVMX_READ_EXIT_QUALIFICATION>(pVCpu, pVmxTransient);
    9178     int rc = vmxHCImportGuestState<CPUMCTX_EXTRN_SREG_MASK | CPUMCTX_EXTRN_DR7>(pVCpu, pVmcsInfo, __FUNCTION__);
     9176    vmxHCReadToTransient<HMVMX_READ_EXIT_QUALIFICATION | HMVMX_READ_EXIT_INSTR_LEN>(pVCpu, pVmxTransient);
     9177    int rc = vmxHCImportGuestState<  IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK
     9178                                   | CPUMCTX_EXTRN_GPRS_MASK
     9179                                   | CPUMCTX_EXTRN_DR7>(pVCpu, pVmcsInfo, __FUNCTION__);
    91799180    AssertRCReturn(rc, rc);
    9180     Log4Func(("cs:rip=%#04x:%08RX64\n", pCtx->cs.Sel, pCtx->rip));
    9181 
    9182     PVMCC pVM = pVCpu->CTX_SUFF(pVM);
     9181    Log4Func(("cs:rip=%#04x:%08RX64\n", pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip));
     9182
     9183    uint8_t const iGReg  = VMX_EXIT_QUAL_DRX_GENREG(pVmxTransient->uExitQual);
     9184    uint8_t const iDrReg = VMX_EXIT_QUAL_DRX_REGISTER(pVmxTransient->uExitQual);
     9185
     9186    VBOXSTRICTRC  rcStrict;
    91839187    if (VMX_EXIT_QUAL_DRX_DIRECTION(pVmxTransient->uExitQual) == VMX_EXIT_QUAL_DRX_DIRECTION_WRITE)
    91849188    {
    9185         rc = EMInterpretDRxWrite(pVM, pVCpu, CPUMCTX2CORE(pCtx),
    9186                                  VMX_EXIT_QUAL_DRX_REGISTER(pVmxTransient->uExitQual),
    9187                                  VMX_EXIT_QUAL_DRX_GENREG(pVmxTransient->uExitQual));
    9188         if (RT_SUCCESS(rc))
    9189             ASMAtomicUoOrU64(&VCPU_2_VMXSTATE(pVCpu).fCtxChanged, HM_CHANGED_GUEST_DR7);
     9189        /*
     9190         * Write DRx register.
     9191         */
     9192        rcStrict = IEMExecDecodedMovDRxWrite(pVCpu, pVmxTransient->cbExitInstr, iDrReg, iGReg);
     9193        AssertMsg(   rcStrict == VINF_SUCCESS
     9194                  || rcStrict == VINF_IEM_RAISED_XCPT, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
     9195
     9196        if (rcStrict == VINF_SUCCESS)
     9197            /** @todo r=bird: Not sure why we always flag DR7 as modified here, but I've
     9198             * kept it for now to avoid breaking something non-obvious. */
     9199            ASMAtomicUoOrU64(&VCPU_2_VMXSTATE(pVCpu).fCtxChanged, HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS
     9200                                                                | HM_CHANGED_GUEST_DR7);
     9201        else if (rcStrict == VINF_IEM_RAISED_XCPT)
     9202        {
     9203            ASMAtomicUoOrU64(&VCPU_2_VMXSTATE(pVCpu).fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
     9204            rcStrict = VINF_SUCCESS;
     9205        }
     9206
    91909207        STAM_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).StatExitDRxWrite);
    91919208    }
    91929209    else
    91939210    {
    9194         rc = EMInterpretDRxRead(pVM, pVCpu, CPUMCTX2CORE(pCtx),
    9195                                 VMX_EXIT_QUAL_DRX_GENREG(pVmxTransient->uExitQual),
    9196                                 VMX_EXIT_QUAL_DRX_REGISTER(pVmxTransient->uExitQual));
     9211        /*
     9212         * Read DRx register into a general purpose register.
     9213         */
     9214        rcStrict = IEMExecDecodedMovDRxRead(pVCpu, pVmxTransient->cbExitInstr, iGReg, iDrReg);
     9215        AssertMsg(   rcStrict == VINF_SUCCESS
     9216                  || rcStrict == VINF_IEM_RAISED_XCPT, ("%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
     9217
     9218        if (rcStrict == VINF_SUCCESS)
     9219        {
     9220            if (iGReg == X86_GREG_xSP)
     9221                ASMAtomicUoOrU64(&VCPU_2_VMXSTATE(pVCpu).fCtxChanged, HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS
     9222                                                                    | HM_CHANGED_GUEST_RSP);
     9223            else
     9224                ASMAtomicUoOrU64(&VCPU_2_VMXSTATE(pVCpu).fCtxChanged, HM_CHANGED_GUEST_RIP | HM_CHANGED_GUEST_RFLAGS);
     9225        }
     9226        else if (rcStrict == VINF_IEM_RAISED_XCPT)
     9227        {
     9228            ASMAtomicUoOrU64(&VCPU_2_VMXSTATE(pVCpu).fCtxChanged, HM_CHANGED_RAISED_XCPT_MASK);
     9229            rcStrict = VINF_SUCCESS;
     9230        }
     9231
    91979232        STAM_COUNTER_INC(&VCPU_2_VMXSTATS(pVCpu).StatExitDRxRead);
    91989233    }
    91999234
    9200     Assert(rc == VINF_SUCCESS || rc == VERR_EM_INTERPRETER);
    9201     if (RT_SUCCESS(rc))
    9202     {
    9203         int rc2 = vmxHCAdvanceGuestRip(pVCpu, pVmxTransient);
    9204         AssertRCReturn(rc2, rc2);
    9205         return VINF_SUCCESS;
    9206     }
    9207     return rc;
     9235    return rcStrict;
    92089236}
    92099237
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