Index: /trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsOneByte.cpp.h
===================================================================
--- /trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsOneByte.cpp.h	(revision 97356)
+++ /trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsOneByte.cpp.h	(revision 97357)
@@ -2804,5 +2804,5 @@
     IEM_MC_BEGIN(0, 0);
     IEM_MC_IF_EFL_BIT_SET(X86_EFL_OF) {
-        IEM_MC_REL_JMP_S8(i8Imm);
+        IEM_MC_REL_JMP_S8_AND_FINISH(i8Imm);
     } IEM_MC_ELSE() {
         IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -2827,5 +2827,5 @@
         IEM_MC_ADVANCE_RIP_AND_FINISH();
     } IEM_MC_ELSE() {
-        IEM_MC_REL_JMP_S8(i8Imm);
+        IEM_MC_REL_JMP_S8_AND_FINISH(i8Imm);
     } IEM_MC_ENDIF();
     IEM_MC_END();
@@ -2845,5 +2845,5 @@
     IEM_MC_BEGIN(0, 0);
     IEM_MC_IF_EFL_BIT_SET(X86_EFL_CF) {
-        IEM_MC_REL_JMP_S8(i8Imm);
+        IEM_MC_REL_JMP_S8_AND_FINISH(i8Imm);
     } IEM_MC_ELSE() {
         IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -2868,5 +2868,5 @@
         IEM_MC_ADVANCE_RIP_AND_FINISH();
     } IEM_MC_ELSE() {
-        IEM_MC_REL_JMP_S8(i8Imm);
+        IEM_MC_REL_JMP_S8_AND_FINISH(i8Imm);
     } IEM_MC_ENDIF();
     IEM_MC_END();
@@ -2887,5 +2887,5 @@
     IEM_MC_BEGIN(0, 0);
     IEM_MC_IF_EFL_BIT_SET(X86_EFL_ZF) {
-        IEM_MC_REL_JMP_S8(i8Imm);
+        IEM_MC_REL_JMP_S8_AND_FINISH(i8Imm);
     } IEM_MC_ELSE() {
         IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -2910,5 +2910,5 @@
         IEM_MC_ADVANCE_RIP_AND_FINISH();
     } IEM_MC_ELSE() {
-        IEM_MC_REL_JMP_S8(i8Imm);
+        IEM_MC_REL_JMP_S8_AND_FINISH(i8Imm);
     } IEM_MC_ENDIF();
     IEM_MC_END();
@@ -2929,5 +2929,5 @@
     IEM_MC_BEGIN(0, 0);
     IEM_MC_IF_EFL_ANY_BITS_SET(X86_EFL_CF | X86_EFL_ZF) {
-        IEM_MC_REL_JMP_S8(i8Imm);
+        IEM_MC_REL_JMP_S8_AND_FINISH(i8Imm);
     } IEM_MC_ELSE() {
         IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -2952,5 +2952,5 @@
         IEM_MC_ADVANCE_RIP_AND_FINISH();
     } IEM_MC_ELSE() {
-        IEM_MC_REL_JMP_S8(i8Imm);
+        IEM_MC_REL_JMP_S8_AND_FINISH(i8Imm);
     } IEM_MC_ENDIF();
     IEM_MC_END();
@@ -2971,5 +2971,5 @@
     IEM_MC_BEGIN(0, 0);
     IEM_MC_IF_EFL_BIT_SET(X86_EFL_SF) {
-        IEM_MC_REL_JMP_S8(i8Imm);
+        IEM_MC_REL_JMP_S8_AND_FINISH(i8Imm);
     } IEM_MC_ELSE() {
         IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -2994,5 +2994,5 @@
         IEM_MC_ADVANCE_RIP_AND_FINISH();
     } IEM_MC_ELSE() {
-        IEM_MC_REL_JMP_S8(i8Imm);
+        IEM_MC_REL_JMP_S8_AND_FINISH(i8Imm);
     } IEM_MC_ENDIF();
     IEM_MC_END();
@@ -3013,5 +3013,5 @@
     IEM_MC_BEGIN(0, 0);
     IEM_MC_IF_EFL_BIT_SET(X86_EFL_PF) {
-        IEM_MC_REL_JMP_S8(i8Imm);
+        IEM_MC_REL_JMP_S8_AND_FINISH(i8Imm);
     } IEM_MC_ELSE() {
         IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -3036,5 +3036,5 @@
         IEM_MC_ADVANCE_RIP_AND_FINISH();
     } IEM_MC_ELSE() {
-        IEM_MC_REL_JMP_S8(i8Imm);
+        IEM_MC_REL_JMP_S8_AND_FINISH(i8Imm);
     } IEM_MC_ENDIF();
     IEM_MC_END();
@@ -3055,5 +3055,5 @@
     IEM_MC_BEGIN(0, 0);
     IEM_MC_IF_EFL_BITS_NE(X86_EFL_SF, X86_EFL_OF) {
-        IEM_MC_REL_JMP_S8(i8Imm);
+        IEM_MC_REL_JMP_S8_AND_FINISH(i8Imm);
     } IEM_MC_ELSE() {
         IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -3078,5 +3078,5 @@
         IEM_MC_ADVANCE_RIP_AND_FINISH();
     } IEM_MC_ELSE() {
-        IEM_MC_REL_JMP_S8(i8Imm);
+        IEM_MC_REL_JMP_S8_AND_FINISH(i8Imm);
     } IEM_MC_ENDIF();
     IEM_MC_END();
@@ -3097,5 +3097,5 @@
     IEM_MC_BEGIN(0, 0);
     IEM_MC_IF_EFL_BIT_SET_OR_BITS_NE(X86_EFL_ZF, X86_EFL_SF, X86_EFL_OF) {
-        IEM_MC_REL_JMP_S8(i8Imm);
+        IEM_MC_REL_JMP_S8_AND_FINISH(i8Imm);
     } IEM_MC_ELSE() {
         IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -3120,5 +3120,5 @@
         IEM_MC_ADVANCE_RIP_AND_FINISH();
     } IEM_MC_ELSE() {
-        IEM_MC_REL_JMP_S8(i8Imm);
+        IEM_MC_REL_JMP_S8_AND_FINISH(i8Imm);
     } IEM_MC_ENDIF();
     IEM_MC_END();
@@ -10313,5 +10313,5 @@
             IEM_MC_SUB_GREG_U16(X86_GREG_xCX, 1);
             IEM_MC_IF_CX_IS_NZ_AND_EFL_BIT_NOT_SET(X86_EFL_ZF) {
-                IEM_MC_REL_JMP_S8(i8Imm);
+                IEM_MC_REL_JMP_S8_AND_FINISH(i8Imm);
             } IEM_MC_ELSE() {
                 IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -10324,5 +10324,5 @@
             IEM_MC_SUB_GREG_U32(X86_GREG_xCX, 1);
             IEM_MC_IF_ECX_IS_NZ_AND_EFL_BIT_NOT_SET(X86_EFL_ZF) {
-                IEM_MC_REL_JMP_S8(i8Imm);
+                IEM_MC_REL_JMP_S8_AND_FINISH(i8Imm);
             } IEM_MC_ELSE() {
                 IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -10335,5 +10335,5 @@
             IEM_MC_SUB_GREG_U64(X86_GREG_xCX, 1);
             IEM_MC_IF_RCX_IS_NZ_AND_EFL_BIT_NOT_SET(X86_EFL_ZF) {
-                IEM_MC_REL_JMP_S8(i8Imm);
+                IEM_MC_REL_JMP_S8_AND_FINISH(i8Imm);
             } IEM_MC_ELSE() {
                 IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -10363,5 +10363,5 @@
             IEM_MC_SUB_GREG_U16(X86_GREG_xCX, 1);
             IEM_MC_IF_CX_IS_NZ_AND_EFL_BIT_SET(X86_EFL_ZF) {
-                IEM_MC_REL_JMP_S8(i8Imm);
+                IEM_MC_REL_JMP_S8_AND_FINISH(i8Imm);
             } IEM_MC_ELSE() {
                 IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -10374,5 +10374,5 @@
             IEM_MC_SUB_GREG_U32(X86_GREG_xCX, 1);
             IEM_MC_IF_ECX_IS_NZ_AND_EFL_BIT_SET(X86_EFL_ZF) {
-                IEM_MC_REL_JMP_S8(i8Imm);
+                IEM_MC_REL_JMP_S8_AND_FINISH(i8Imm);
             } IEM_MC_ELSE() {
                 IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -10385,5 +10385,5 @@
             IEM_MC_SUB_GREG_U64(X86_GREG_xCX, 1);
             IEM_MC_IF_RCX_IS_NZ_AND_EFL_BIT_SET(X86_EFL_ZF) {
-                IEM_MC_REL_JMP_S8(i8Imm);
+                IEM_MC_REL_JMP_S8_AND_FINISH(i8Imm);
             } IEM_MC_ELSE() {
                 IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -10451,5 +10451,5 @@
             IEM_MC_SUB_GREG_U16(X86_GREG_xCX, 1);
             IEM_MC_IF_CX_IS_NZ() {
-                IEM_MC_REL_JMP_S8(i8Imm);
+                IEM_MC_REL_JMP_S8_AND_FINISH(i8Imm);
             } IEM_MC_ELSE() {
                 IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -10462,5 +10462,5 @@
             IEM_MC_SUB_GREG_U32(X86_GREG_xCX, 1);
             IEM_MC_IF_ECX_IS_NZ() {
-                IEM_MC_REL_JMP_S8(i8Imm);
+                IEM_MC_REL_JMP_S8_AND_FINISH(i8Imm);
             } IEM_MC_ELSE() {
                 IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -10473,5 +10473,5 @@
             IEM_MC_SUB_GREG_U64(X86_GREG_xCX, 1);
             IEM_MC_IF_RCX_IS_NZ() {
-                IEM_MC_REL_JMP_S8(i8Imm);
+                IEM_MC_REL_JMP_S8_AND_FINISH(i8Imm);
             } IEM_MC_ELSE() {
                 IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -10502,5 +10502,5 @@
                 IEM_MC_ADVANCE_RIP_AND_FINISH();
             } IEM_MC_ELSE() {
-                IEM_MC_REL_JMP_S8(i8Imm);
+                IEM_MC_REL_JMP_S8_AND_FINISH(i8Imm);
             } IEM_MC_ENDIF();
             IEM_MC_END();
@@ -10512,5 +10512,5 @@
                 IEM_MC_ADVANCE_RIP_AND_FINISH();
             } IEM_MC_ELSE() {
-                IEM_MC_REL_JMP_S8(i8Imm);
+                IEM_MC_REL_JMP_S8_AND_FINISH(i8Imm);
             } IEM_MC_ENDIF();
             IEM_MC_END();
@@ -10522,5 +10522,5 @@
                 IEM_MC_ADVANCE_RIP_AND_FINISH();
             } IEM_MC_ELSE() {
-                IEM_MC_REL_JMP_S8(i8Imm);
+                IEM_MC_REL_JMP_S8_AND_FINISH(i8Imm);
             } IEM_MC_ENDIF();
             IEM_MC_END();
@@ -10617,5 +10617,5 @@
             int16_t i16Imm; IEM_OPCODE_GET_NEXT_S16(&i16Imm);
             IEM_MC_BEGIN(0, 0);
-            IEM_MC_REL_JMP_S16(i16Imm);
+            IEM_MC_REL_JMP_S16_AND_FINISH(i16Imm);
             IEM_MC_END();
             return VINF_SUCCESS;
@@ -10627,5 +10627,5 @@
             int32_t i32Imm; IEM_OPCODE_GET_NEXT_S32(&i32Imm);
             IEM_MC_BEGIN(0, 0);
-            IEM_MC_REL_JMP_S32(i32Imm);
+            IEM_MC_REL_JMP_S32_AND_FINISH(i32Imm);
             IEM_MC_END();
             return VINF_SUCCESS;
@@ -10668,5 +10668,5 @@
 
     IEM_MC_BEGIN(0, 0);
-    IEM_MC_REL_JMP_S8(i8Imm);
+    IEM_MC_REL_JMP_S8_AND_FINISH(i8Imm);
     IEM_MC_END();
     return VINF_SUCCESS;
@@ -11717,5 +11717,5 @@
                 IEM_MC_LOCAL(uint16_t, u16Target);
                 IEM_MC_FETCH_GREG_U16(u16Target, IEM_GET_MODRM_RM(pVCpu, bRm));
-                IEM_MC_SET_RIP_U16(u16Target);
+                IEM_MC_SET_RIP_U16_AND_FINISH(u16Target);
                 IEM_MC_END()
                 return VINF_SUCCESS;
@@ -11725,5 +11725,5 @@
                 IEM_MC_LOCAL(uint32_t, u32Target);
                 IEM_MC_FETCH_GREG_U32(u32Target, IEM_GET_MODRM_RM(pVCpu, bRm));
-                IEM_MC_SET_RIP_U32(u32Target);
+                IEM_MC_SET_RIP_U32_AND_FINISH(u32Target);
                 IEM_MC_END()
                 return VINF_SUCCESS;
@@ -11733,5 +11733,5 @@
                 IEM_MC_LOCAL(uint64_t, u64Target);
                 IEM_MC_FETCH_GREG_U64(u64Target, IEM_GET_MODRM_RM(pVCpu, bRm));
-                IEM_MC_SET_RIP_U64(u64Target);
+                IEM_MC_SET_RIP_U64_AND_FINISH(u64Target);
                 IEM_MC_END()
                 return VINF_SUCCESS;
@@ -11752,5 +11752,5 @@
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_FETCH_MEM_U16(u16Target, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
-                IEM_MC_SET_RIP_U16(u16Target);
+                IEM_MC_SET_RIP_U16_AND_FINISH(u16Target);
                 IEM_MC_END()
                 return VINF_SUCCESS;
@@ -11763,5 +11763,5 @@
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_FETCH_MEM_U32(u32Target, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
-                IEM_MC_SET_RIP_U32(u32Target);
+                IEM_MC_SET_RIP_U32_AND_FINISH(u32Target);
                 IEM_MC_END()
                 return VINF_SUCCESS;
@@ -11774,5 +11774,5 @@
                 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();
                 IEM_MC_FETCH_MEM_U64(u64Target, pVCpu->iem.s.iEffSeg, GCPtrEffSrc);
-                IEM_MC_SET_RIP_U64(u64Target);
+                IEM_MC_SET_RIP_U64_AND_FINISH(u64Target);
                 IEM_MC_END()
                 return VINF_SUCCESS;
Index: /trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsTwoByte0f.cpp.h
===================================================================
--- /trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsTwoByte0f.cpp.h	(revision 97356)
+++ /trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsTwoByte0f.cpp.h	(revision 97357)
@@ -7779,5 +7779,5 @@
         IEM_MC_BEGIN(0, 0);
         IEM_MC_IF_EFL_BIT_SET(X86_EFL_OF) {
-            IEM_MC_REL_JMP_S16(i16Imm);
+            IEM_MC_REL_JMP_S16_AND_FINISH(i16Imm);
         } IEM_MC_ELSE() {
             IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -7792,5 +7792,5 @@
         IEM_MC_BEGIN(0, 0);
         IEM_MC_IF_EFL_BIT_SET(X86_EFL_OF) {
-            IEM_MC_REL_JMP_S32(i32Imm);
+            IEM_MC_REL_JMP_S32_AND_FINISH(i32Imm);
         } IEM_MC_ELSE() {
             IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -7817,5 +7817,5 @@
             IEM_MC_ADVANCE_RIP_AND_FINISH();
         } IEM_MC_ELSE() {
-            IEM_MC_REL_JMP_S16(i16Imm);
+            IEM_MC_REL_JMP_S16_AND_FINISH(i16Imm);
         } IEM_MC_ENDIF();
         IEM_MC_END();
@@ -7830,5 +7830,5 @@
             IEM_MC_ADVANCE_RIP_AND_FINISH();
         } IEM_MC_ELSE() {
-            IEM_MC_REL_JMP_S32(i32Imm);
+            IEM_MC_REL_JMP_S32_AND_FINISH(i32Imm);
         } IEM_MC_ENDIF();
         IEM_MC_END();
@@ -7851,5 +7851,5 @@
         IEM_MC_BEGIN(0, 0);
         IEM_MC_IF_EFL_BIT_SET(X86_EFL_CF) {
-            IEM_MC_REL_JMP_S16(i16Imm);
+            IEM_MC_REL_JMP_S16_AND_FINISH(i16Imm);
         } IEM_MC_ELSE() {
             IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -7864,5 +7864,5 @@
         IEM_MC_BEGIN(0, 0);
         IEM_MC_IF_EFL_BIT_SET(X86_EFL_CF) {
-            IEM_MC_REL_JMP_S32(i32Imm);
+            IEM_MC_REL_JMP_S32_AND_FINISH(i32Imm);
         } IEM_MC_ELSE() {
             IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -7889,5 +7889,5 @@
             IEM_MC_ADVANCE_RIP_AND_FINISH();
         } IEM_MC_ELSE() {
-            IEM_MC_REL_JMP_S16(i16Imm);
+            IEM_MC_REL_JMP_S16_AND_FINISH(i16Imm);
         } IEM_MC_ENDIF();
         IEM_MC_END();
@@ -7902,5 +7902,5 @@
             IEM_MC_ADVANCE_RIP_AND_FINISH();
         } IEM_MC_ELSE() {
-            IEM_MC_REL_JMP_S32(i32Imm);
+            IEM_MC_REL_JMP_S32_AND_FINISH(i32Imm);
         } IEM_MC_ENDIF();
         IEM_MC_END();
@@ -7923,5 +7923,5 @@
         IEM_MC_BEGIN(0, 0);
         IEM_MC_IF_EFL_BIT_SET(X86_EFL_ZF) {
-            IEM_MC_REL_JMP_S16(i16Imm);
+            IEM_MC_REL_JMP_S16_AND_FINISH(i16Imm);
         } IEM_MC_ELSE() {
             IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -7936,5 +7936,5 @@
         IEM_MC_BEGIN(0, 0);
         IEM_MC_IF_EFL_BIT_SET(X86_EFL_ZF) {
-            IEM_MC_REL_JMP_S32(i32Imm);
+            IEM_MC_REL_JMP_S32_AND_FINISH(i32Imm);
         } IEM_MC_ELSE() {
             IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -7961,5 +7961,5 @@
             IEM_MC_ADVANCE_RIP_AND_FINISH();
         } IEM_MC_ELSE() {
-            IEM_MC_REL_JMP_S16(i16Imm);
+            IEM_MC_REL_JMP_S16_AND_FINISH(i16Imm);
         } IEM_MC_ENDIF();
         IEM_MC_END();
@@ -7974,5 +7974,5 @@
             IEM_MC_ADVANCE_RIP_AND_FINISH();
         } IEM_MC_ELSE() {
-            IEM_MC_REL_JMP_S32(i32Imm);
+            IEM_MC_REL_JMP_S32_AND_FINISH(i32Imm);
         } IEM_MC_ENDIF();
         IEM_MC_END();
@@ -7995,5 +7995,5 @@
         IEM_MC_BEGIN(0, 0);
         IEM_MC_IF_EFL_ANY_BITS_SET(X86_EFL_CF | X86_EFL_ZF) {
-            IEM_MC_REL_JMP_S16(i16Imm);
+            IEM_MC_REL_JMP_S16_AND_FINISH(i16Imm);
         } IEM_MC_ELSE() {
             IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -8008,5 +8008,5 @@
         IEM_MC_BEGIN(0, 0);
         IEM_MC_IF_EFL_ANY_BITS_SET(X86_EFL_CF | X86_EFL_ZF) {
-            IEM_MC_REL_JMP_S32(i32Imm);
+            IEM_MC_REL_JMP_S32_AND_FINISH(i32Imm);
         } IEM_MC_ELSE() {
             IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -8033,5 +8033,5 @@
             IEM_MC_ADVANCE_RIP_AND_FINISH();
         } IEM_MC_ELSE() {
-            IEM_MC_REL_JMP_S16(i16Imm);
+            IEM_MC_REL_JMP_S16_AND_FINISH(i16Imm);
         } IEM_MC_ENDIF();
         IEM_MC_END();
@@ -8046,5 +8046,5 @@
             IEM_MC_ADVANCE_RIP_AND_FINISH();
         } IEM_MC_ELSE() {
-            IEM_MC_REL_JMP_S32(i32Imm);
+            IEM_MC_REL_JMP_S32_AND_FINISH(i32Imm);
         } IEM_MC_ENDIF();
         IEM_MC_END();
@@ -8067,5 +8067,5 @@
         IEM_MC_BEGIN(0, 0);
         IEM_MC_IF_EFL_BIT_SET(X86_EFL_SF) {
-            IEM_MC_REL_JMP_S16(i16Imm);
+            IEM_MC_REL_JMP_S16_AND_FINISH(i16Imm);
         } IEM_MC_ELSE() {
             IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -8080,5 +8080,5 @@
         IEM_MC_BEGIN(0, 0);
         IEM_MC_IF_EFL_BIT_SET(X86_EFL_SF) {
-            IEM_MC_REL_JMP_S32(i32Imm);
+            IEM_MC_REL_JMP_S32_AND_FINISH(i32Imm);
         } IEM_MC_ELSE() {
             IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -8105,5 +8105,5 @@
             IEM_MC_ADVANCE_RIP_AND_FINISH();
         } IEM_MC_ELSE() {
-            IEM_MC_REL_JMP_S16(i16Imm);
+            IEM_MC_REL_JMP_S16_AND_FINISH(i16Imm);
         } IEM_MC_ENDIF();
         IEM_MC_END();
@@ -8118,5 +8118,5 @@
             IEM_MC_ADVANCE_RIP_AND_FINISH();
         } IEM_MC_ELSE() {
-            IEM_MC_REL_JMP_S32(i32Imm);
+            IEM_MC_REL_JMP_S32_AND_FINISH(i32Imm);
         } IEM_MC_ENDIF();
         IEM_MC_END();
@@ -8139,5 +8139,5 @@
         IEM_MC_BEGIN(0, 0);
         IEM_MC_IF_EFL_BIT_SET(X86_EFL_PF) {
-            IEM_MC_REL_JMP_S16(i16Imm);
+            IEM_MC_REL_JMP_S16_AND_FINISH(i16Imm);
         } IEM_MC_ELSE() {
             IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -8152,5 +8152,5 @@
         IEM_MC_BEGIN(0, 0);
         IEM_MC_IF_EFL_BIT_SET(X86_EFL_PF) {
-            IEM_MC_REL_JMP_S32(i32Imm);
+            IEM_MC_REL_JMP_S32_AND_FINISH(i32Imm);
         } IEM_MC_ELSE() {
             IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -8177,5 +8177,5 @@
             IEM_MC_ADVANCE_RIP_AND_FINISH();
         } IEM_MC_ELSE() {
-            IEM_MC_REL_JMP_S16(i16Imm);
+            IEM_MC_REL_JMP_S16_AND_FINISH(i16Imm);
         } IEM_MC_ENDIF();
         IEM_MC_END();
@@ -8190,5 +8190,5 @@
             IEM_MC_ADVANCE_RIP_AND_FINISH();
         } IEM_MC_ELSE() {
-            IEM_MC_REL_JMP_S32(i32Imm);
+            IEM_MC_REL_JMP_S32_AND_FINISH(i32Imm);
         } IEM_MC_ENDIF();
         IEM_MC_END();
@@ -8211,5 +8211,5 @@
         IEM_MC_BEGIN(0, 0);
         IEM_MC_IF_EFL_BITS_NE(X86_EFL_SF, X86_EFL_OF) {
-            IEM_MC_REL_JMP_S16(i16Imm);
+            IEM_MC_REL_JMP_S16_AND_FINISH(i16Imm);
         } IEM_MC_ELSE() {
             IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -8224,5 +8224,5 @@
         IEM_MC_BEGIN(0, 0);
         IEM_MC_IF_EFL_BITS_NE(X86_EFL_SF, X86_EFL_OF) {
-            IEM_MC_REL_JMP_S32(i32Imm);
+            IEM_MC_REL_JMP_S32_AND_FINISH(i32Imm);
         } IEM_MC_ELSE() {
             IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -8249,5 +8249,5 @@
             IEM_MC_ADVANCE_RIP_AND_FINISH();
         } IEM_MC_ELSE() {
-            IEM_MC_REL_JMP_S16(i16Imm);
+            IEM_MC_REL_JMP_S16_AND_FINISH(i16Imm);
         } IEM_MC_ENDIF();
         IEM_MC_END();
@@ -8262,5 +8262,5 @@
             IEM_MC_ADVANCE_RIP_AND_FINISH();
         } IEM_MC_ELSE() {
-            IEM_MC_REL_JMP_S32(i32Imm);
+            IEM_MC_REL_JMP_S32_AND_FINISH(i32Imm);
         } IEM_MC_ENDIF();
         IEM_MC_END();
@@ -8283,5 +8283,5 @@
         IEM_MC_BEGIN(0, 0);
         IEM_MC_IF_EFL_BIT_SET_OR_BITS_NE(X86_EFL_ZF, X86_EFL_SF, X86_EFL_OF) {
-            IEM_MC_REL_JMP_S16(i16Imm);
+            IEM_MC_REL_JMP_S16_AND_FINISH(i16Imm);
         } IEM_MC_ELSE() {
             IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -8296,5 +8296,5 @@
         IEM_MC_BEGIN(0, 0);
         IEM_MC_IF_EFL_BIT_SET_OR_BITS_NE(X86_EFL_ZF, X86_EFL_SF, X86_EFL_OF) {
-            IEM_MC_REL_JMP_S32(i32Imm);
+            IEM_MC_REL_JMP_S32_AND_FINISH(i32Imm);
         } IEM_MC_ELSE() {
             IEM_MC_ADVANCE_RIP_AND_FINISH();
@@ -8321,5 +8321,5 @@
             IEM_MC_ADVANCE_RIP_AND_FINISH();
         } IEM_MC_ELSE() {
-            IEM_MC_REL_JMP_S16(i16Imm);
+            IEM_MC_REL_JMP_S16_AND_FINISH(i16Imm);
         } IEM_MC_ENDIF();
         IEM_MC_END();
@@ -8334,5 +8334,5 @@
             IEM_MC_ADVANCE_RIP_AND_FINISH();
         } IEM_MC_ELSE() {
-            IEM_MC_REL_JMP_S32(i32Imm);
+            IEM_MC_REL_JMP_S32_AND_FINISH(i32Imm);
         } IEM_MC_ENDIF();
         IEM_MC_END();
Index: /trunk/src/VBox/VMM/include/IEMMc.h
===================================================================
--- /trunk/src/VBox/VMM/include/IEMMc.h	(revision 97356)
+++ /trunk/src/VBox/VMM/include/IEMMc.h	(revision 97357)
@@ -58,10 +58,17 @@
  *       if not the last MC statement. */
 #define IEM_MC_ADVANCE_RIP_AND_FINISH()                 iemRegUpdateRipAndClearRF(pVCpu)
-#define IEM_MC_REL_JMP_S8(a_i8)                         IEM_MC_RETURN_ON_FAILURE(iemRegRipRelativeJumpS8(pVCpu, a_i8))
-#define IEM_MC_REL_JMP_S16(a_i16)                       IEM_MC_RETURN_ON_FAILURE(iemRegRipRelativeJumpS16(pVCpu, a_i16))
-#define IEM_MC_REL_JMP_S32(a_i32)                       IEM_MC_RETURN_ON_FAILURE(iemRegRipRelativeJumpS32(pVCpu, a_i32))
-#define IEM_MC_SET_RIP_U16(a_u16NewIP)                  IEM_MC_RETURN_ON_FAILURE(iemRegRipJump((pVCpu), (a_u16NewIP)))
-#define IEM_MC_SET_RIP_U32(a_u32NewIP)                  IEM_MC_RETURN_ON_FAILURE(iemRegRipJump((pVCpu), (a_u32NewIP)))
-#define IEM_MC_SET_RIP_U64(a_u64NewIP)                  IEM_MC_RETURN_ON_FAILURE(iemRegRipJump((pVCpu), (a_u64NewIP)))
+/** Tries to set RIP (may trigger \#GP) and finishes the instruction. */
+#define IEM_MC_REL_JMP_S8_AND_FINISH(a_i8)              IEM_MC_RETURN_ON_FAILURE(iemRegRipRelativeJumpS8(pVCpu, a_i8))
+/** Tries to set RIP (may trigger \#GP) and finishes the instruction. */
+#define IEM_MC_REL_JMP_S16_AND_FINISH(a_i16)            IEM_MC_RETURN_ON_FAILURE(iemRegRipRelativeJumpS16(pVCpu, a_i16))
+/** Tries to set RIP (may trigger \#GP) and finishes the instruction. */
+#define IEM_MC_REL_JMP_S32_AND_FINISH(a_i32)            IEM_MC_RETURN_ON_FAILURE(iemRegRipRelativeJumpS32(pVCpu, a_i32))
+/** Tries to set RIP (may trigger \#GP) and finishes the instruction. */
+#define IEM_MC_SET_RIP_U16_AND_FINISH(a_u16NewIP)       IEM_MC_RETURN_ON_FAILURE(iemRegRipJump((pVCpu), (a_u16NewIP)))
+/** Tries to set RIP (may trigger \#GP) and finishes the instruction. */
+#define IEM_MC_SET_RIP_U32_AND_FINISH(a_u32NewIP)       IEM_MC_RETURN_ON_FAILURE(iemRegRipJump((pVCpu), (a_u32NewIP)))
+/** Tries to set RIP (may trigger \#GP) and finishes the instruction. */
+#define IEM_MC_SET_RIP_U64_AND_FINISH(a_u64NewIP)       IEM_MC_RETURN_ON_FAILURE(iemRegRipJump((pVCpu), (a_u64NewIP)))
+
 #define IEM_MC_RAISE_DIVIDE_ERROR()                     return iemRaiseDivideError(pVCpu)
 #define IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE()       \
Index: /trunk/src/VBox/VMM/testcase/tstIEMCheckMc.cpp
===================================================================
--- /trunk/src/VBox/VMM/testcase/tstIEMCheckMc.cpp	(revision 97356)
+++ /trunk/src/VBox/VMM/testcase/tstIEMCheckMc.cpp	(revision 97357)
@@ -576,10 +576,10 @@
 
 #define IEM_MC_ADVANCE_RIP_AND_FINISH()                 do { (void)fMcBegin; return VINF_SUCCESS; } while (0)
-#define IEM_MC_REL_JMP_S8(a_i8)                         do { (void)fMcBegin; CHK_TYPE(int8_t, a_i8); } while (0)
-#define IEM_MC_REL_JMP_S16(a_i16)                       do { (void)fMcBegin; CHK_TYPE(int16_t, a_i16); } while (0)
-#define IEM_MC_REL_JMP_S32(a_i32)                       do { (void)fMcBegin; CHK_TYPE(int32_t, a_i32); } while (0)
-#define IEM_MC_SET_RIP_U16(a_u16NewIP)                  do { (void)fMcBegin; CHK_TYPE(uint16_t, a_u16NewIP); } while (0)
-#define IEM_MC_SET_RIP_U32(a_u32NewIP)                  do { (void)fMcBegin; CHK_TYPE(uint32_t, a_u32NewIP); } while (0)
-#define IEM_MC_SET_RIP_U64(a_u64NewIP)                  do { (void)fMcBegin; CHK_TYPE(uint64_t, a_u64NewIP); } while (0)
+#define IEM_MC_REL_JMP_S8_AND_FINISH(a_i8)              do { (void)fMcBegin; CHK_TYPE(int8_t, a_i8); return VINF_SUCCESS; } while (0)
+#define IEM_MC_REL_JMP_S16_AND_FINISH(a_i16)            do { (void)fMcBegin; CHK_TYPE(int16_t, a_i16); return VINF_SUCCESS; } while (0)
+#define IEM_MC_REL_JMP_S32_AND_FINISH(a_i32)            do { (void)fMcBegin; CHK_TYPE(int32_t, a_i32); return VINF_SUCCESS; } while (0)
+#define IEM_MC_SET_RIP_U16_AND_FINISH(a_u16NewIP)       do { (void)fMcBegin; CHK_TYPE(uint16_t, a_u16NewIP); return VINF_SUCCESS; } while (0)
+#define IEM_MC_SET_RIP_U32_AND_FINISH(a_u32NewIP)       do { (void)fMcBegin; CHK_TYPE(uint32_t, a_u32NewIP); return VINF_SUCCESS; } while (0)
+#define IEM_MC_SET_RIP_U64_AND_FINISH(a_u64NewIP)       do { (void)fMcBegin; CHK_TYPE(uint64_t, a_u64NewIP); return VINF_SUCCESS; } while (0)
 #define IEM_MC_RAISE_DIVIDE_ERROR()                     do { (void)fMcBegin; return VERR_TRPM_ACTIVE_TRAP; } while (0)
 #define IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE()       do { (void)fMcBegin; } while (0)
