Changeset 97406 in vbox for trunk/include/VBox/vmm

Timestamp:

Nov 5, 2022 12:42:14 PM (3 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

154411

Message:

VMM/IEM,CPUM: Partial single stepping support in the interpreter. bugref:9898

Location:

trunk/include/VBox/vmm

Files:

• cpumctx.h (modified) (3 diffs)
• vm.h (modified) (1 diff)

trunk/include/VBox/vmm/cpumctx.h

@@ -276 +276 @@
 /** Mask of internal flags kept with EFLAGS, 64-bit version.
  * The first 3 available bits are taken by CPUMCTX_INHIBIT_SHADOW_SS,
- * CPUMCTX_INHIBIT_SHADOW_STI and CPUMCTX_INHIBIT_NMI.
- */
-#define CPUMX86EFLAGS_INT_MASK_64   UINT64_C(0x0000000007000000)
+ * CPUMCTX_INHIBIT_SHADOW_STI and CPUMCTX_INHIBIT_NMI.  The next 4 bits are
+ * taken by CPUMCTX_DBG_HIT_DRX_MASK.
+ */
+#define CPUMX86EFLAGS_INT_MASK_64   UINT64_C(0x000000007f000000)
 /** Mask of internal flags kept with EFLAGS, 32-bit version. */
-#define CPUMX86EFLAGS_INT_MASK_32           UINT32_C(0x07000000)
+#define CPUMX86EFLAGS_INT_MASK_32           UINT32_C(0x7f000000)
 
 
@@ -1025 +1026 @@
  * other interrupts, including NMI interrupts, are received until the NMI
  * handler has completed executing."  This flag indicates that these
- * conditions are currently active.  */
+ * conditions are currently active.
+ *
+ * @todo this does not really need to be in the lower 32-bits of EFLAGS.
+ */
 #define CPUMCTX_INHIBIT_NMI             RT_BIT_32(2 + CPUMX86EFLAGS_HW_BITS)
 
@@ -1032 +1036 @@
 AssertCompile(CPUMCTX_INHIBIT_ALL_MASK < UINT32_MAX);
 /** @} */
+
+/** @name CPUMCTX_DBG_XXX - Pending debug events.
+ * @{ */
+/** Hit guest DR0 breakpoint. */
+#define CPUMCTX_DBG_HIT_DR0             RT_BIT_32(CPUMCTX_DBG_HIT_DR0_BIT)
+#define CPUMCTX_DBG_HIT_DR0_BIT         (3 + CPUMX86EFLAGS_HW_BITS)
+/** Hit guest DR1 breakpoint. */
+#define CPUMCTX_DBG_HIT_DR1             RT_BIT_32(CPUMCTX_DBG_HIT_DR1_BIT)
+#define CPUMCTX_DBG_HIT_DR1_BIT         (4 + CPUMX86EFLAGS_HW_BITS)
+/** Hit guest DR2 breakpoint. */
+#define CPUMCTX_DBG_HIT_DR2             RT_BIT_32(CPUMCTX_DBG_HIT_DR2_BIT)
+#define CPUMCTX_DBG_HIT_DR2_BIT         (5 + CPUMX86EFLAGS_HW_BITS)
+/** Hit guest DR3 breakpoint. */
+#define CPUMCTX_DBG_HIT_DR3             RT_BIT_32(CPUMCTX_DBG_HIT_DR3_BIT)
+#define CPUMCTX_DBG_HIT_DR3_BIT         (6 + CPUMX86EFLAGS_HW_BITS)
+/** Shift for the CPUMCTX_DBG_HIT_DRx bits. */
+#define CPUMCTX_DBG_HIT_DRX_SHIFT       CPUMCTX_DBG_HIT_DR0_BIT
+/** Mask of all guest pending DR0-DR3 breakpoint indicators. */
+#define CPUMCTX_DBG_HIT_DRX_MASK       (CPUMCTX_DBG_HIT_DR0 | CPUMCTX_DBG_HIT_DR1 | CPUMCTX_DBG_HIT_DR2 | CPUMCTX_DBG_HIT_DR3)
+AssertCompile(CPUMCTX_DBG_HIT_DRX_MASK < UINT32_MAX);
+/** @}  */
+
 
 

trunk/include/VBox/vmm/vm.h

@@ -539 +539 @@
 #define VMCPU_FF_VMX_MTF                    RT_BIT_64(VMCPU_FF_VMX_MTF_BIT)
 #define VMCPU_FF_VMX_MTF_BIT                32
-/** VMX APIC-write emulation pending.  */
+/** VMX APIC-write emulation pending.
+ * @todo possible candidate for internal EFLAGS, or maybe just a summary bit
+ *       (see also VMCPU_FF_VMX_INT_WINDOW). */
 #define VMCPU_FF_VMX_APIC_WRITE             RT_BIT_64(VMCPU_FF_VMX_APIC_WRITE_BIT)
 #define VMCPU_FF_VMX_APIC_WRITE_BIT         33
-/** VMX interrupt-window event pending. */
+/** VMX interrupt-window event pending.
+ *
+ * "Pending" is misleading here, it would be better to say that the event need
+ * to be generated at the next opportunity and that this flag causes it to be
+ * polled for on every instruction boundrary and such.
+ *
+ * @todo Change the IEM side of this to not poll but to track down the places
+ *       where it can be generated and set an internal EFLAGS bit that causes it
+ *       to be checked out when finishing the current instruction. */
 #define VMCPU_FF_VMX_INT_WINDOW             RT_BIT_64(VMCPU_FF_VMX_INT_WINDOW_BIT)
 #define VMCPU_FF_VMX_INT_WINDOW_BIT         34
-/** VMX NMI-window event pending. */
+/** VMX NMI-window event pending.
+ * Same "pending" comment and todo in VMCPU_FF_VMX_INT_WINDOW. */
 #define VMCPU_FF_VMX_NMI_WINDOW             RT_BIT_64(VMCPU_FF_VMX_NMI_WINDOW_BIT)
 #define VMCPU_FF_VMX_NMI_WINDOW_BIT         35