Changeset 97431 in vbox
- Timestamp:
- Nov 7, 2022 1:53:24 PM (2 years ago)
- svn:sync-xref-src-repo-rev:
- 154436
- Location:
- trunk/src/VBox/ValidationKit/bootsectors
- Files:
-
- 4 edited
-
bs3-cpu-basic-2-asm.asm (modified) (1 diff)
-
bs3-cpu-basic-2-template.mac (modified) (1 diff)
-
bs3-cpu-basic-2-x0.c (modified) (1 diff)
-
bs3-cpu-basic-2.c (modified) (3 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-basic-2-asm.asm
r96407 r97431 160 160 161 161 162 ; 163 ; Jump code segment 64KB. 164 ; 165 ; There is no ORG directive in OMF mode of course. :-( 166 ; 167 section BS3JMPTEXT16 align=16 CLASS=BS3CLASS16JMPCODE PRIVATE USE16 168 GROUP BS3GROUPJMPTEXT16 BS3JMPTEXT16 169 BS3_SET_BITS 16 170 171 ; 0000: Start with two int3 filler instructions. 172 BS3_GLOBAL_NAME_EX NAME(bs3CpuBasic2_jmptext16_start), function, 2 173 int3 174 int3 175 176 ; 0002: This is the target for forward wrap around jumps, should they succeed. 177 BS3_GLOBAL_NAME_EX NAME(bs3CpuBasic2_jmp_target_wrap_forward), function, 2 178 ud2 179 align 8, int3 180 181 ; 0008 182 BS3_GLOBAL_NAME_EX NAME(bs3CpuBasic2_jmp_jb_wrap_backward__ud2), function, 2 183 db 0ebh, -012h ; jmp (0x0008 + 2 - 0x12 = 0xFFFFFFF8 (-8)) 184 int3 185 186 ; 000b 187 BS3_GLOBAL_NAME_EX NAME(bs3CpuBasic2_jmp_jb_opsize_wrap_backward__ud2), function, 3 188 db 066h, 0ebh, -016h ; jmp (0x000b + 3 - 0x16 = 0xFFFFFFF8 (-8)) 189 int3 190 191 align 0x80, int3 192 ; 0080 193 BS3_GLOBAL_NAME_EX NAME(bs3CpuBasic2_jmp_jv16_wrap_backward__ud2), function, 3 194 db 0e9h ; jmp (0x0080 + 3 - 0x8b = 0xFFFFFFF8 (-8)) 195 dw -08bh 196 int3 197 198 ; 0084 199 BS3_GLOBAL_NAME_EX NAME(bs3CpuBasic2_jmp_jv16_opsize_wrap_backward__ud2), function, 3 200 db 066h, 0e9h ; jmp (0x0084 + 6 - 0x92 = 0xFFFFFFF8 (-8)) 201 dd -092h 202 int3 203 204 205 align 0x100, int3 ; Note! Doesn't work correctly for higher values. 206 times (0xff76 - 0x100) int3 207 208 209 ; ff76 210 BS3_GLOBAL_NAME_EX NAME(bs3CpuBasic2_jmp_jv16_wrap_forward__ud2), function, 5 211 db 0e9h ; jmp (0xff76+4 + 0x88 = 0x10002 (65538)) 212 dw 089h 213 int3 214 215 ; ff7a 216 BS3_GLOBAL_NAME_EX NAME(bs3CpuBasic2_jmp_jv16_opsize_wrap_forward__ud2), function, 7 217 db 066h, 0e9h ; o32 jmp (0xff7a+6 + 0x82 = 0x10002 (65538)) 218 dd 082h 219 int3 220 221 ; ff81 222 BS3_GLOBAL_NAME_EX NAME(bs3CpuBasic2_jmp_jb_wrap_forward__ud2), function, 2 223 db 0ebh, 07fh ; jmp (0xff81+2 + 0x7f = 0x10002 (65538)) 224 int3 225 226 ; ff84 227 BS3_GLOBAL_NAME_EX NAME(bs3CpuBasic2_jmp_jb_opsize_wrap_forward__ud2), function, 3 228 db 066h, 0ebh, 07bh ; o32 jmp (0xff84+3 + 0x7b = 0x10002 (65538)) 229 ; ff87 230 231 times (0xfff8 - 0xff87) int3 232 233 ; fff8: This is the target for backward wrap around jumps, should they succeed. 234 BS3_GLOBAL_NAME_EX NAME(bs3CpuBasic2_jmp_target_wrap_backward), function, 2 235 ud2 236 times 6 int3 237 ; End of segment. 238 162 239 BS3_BEGIN_TEXT16 163 240 -
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-basic-2-template.mac
r96407 r97431 499 499 500 500 501 ;********************************************************************************************************************************* 502 ;* JMP Tests (simple ones). * 503 ;********************************************************************************************************************************* 504 505 ; jmp rel8 (forwards) 506 BS3_CPUBAS2_UD_OFF bs3CpuBasic2_jmp_jb__ud2 507 BS3_PROC_BEGIN_CMN bs3CpuBasic2_jmp_jb__ud2, BS3_PBC_NEAR 508 jmp short .again 509 .post_jmp: 510 times 7 int3 511 .again: ud2 512 int3 513 jmp .again 514 AssertCompile(.post_jmp - BS3_LAST_LABEL == 2) 515 BS3_PROC_END_CMN bs3CpuBasic2_jmp_jb__ud2 516 517 518 ; jmp rel8 (backwards) 519 BS3_CPUBAS2_UD_OFF bs3CpuBasic2_jmp_jb_back__ud2 520 BS3_PROC_BEGIN_CMN bs3CpuBasic2_jmp_jb_back__ud2, BS3_PBC_NEAR 521 jmp .start 522 .again: ud2 523 times 7 int3 524 jmp .again 525 .start: 526 jmp short .again 527 .post_jmp: 528 int3 529 AssertCompile(.post_jmp - .start == 2) 530 BS3_PROC_END_CMN bs3CpuBasic2_jmp_jb_back__ud2 531 532 533 ; jmp rel16 (forwards) 534 BS3_CPUBAS2_UD_OFF bs3CpuBasic2_jmp_jv__ud2 535 BS3_PROC_BEGIN_CMN bs3CpuBasic2_jmp_jv__ud2, BS3_PBC_NEAR 536 jmp near .again 537 .post_jmp: 538 times 9 int3 539 .again: ud2 540 int3 541 jmp .again 542 %if TMPL_BITS == 16 543 AssertCompile(.post_jmp - BS3_LAST_LABEL == 3) 544 %else 545 AssertCompile(.post_jmp - BS3_LAST_LABEL == 5) 546 %endif 547 BS3_PROC_END_CMN bs3CpuBasic2_jmp_jv__ud2 548 549 550 ; jmp rel16 (backwards) 551 BS3_CPUBAS2_UD_OFF bs3CpuBasic2_jmp_jv_back__ud2 552 BS3_PROC_BEGIN_CMN bs3CpuBasic2_jmp_jv_back__ud2, BS3_PBC_NEAR 553 jmp .start 554 .again: ud2 555 times 6 int3 556 jmp .again 557 .start: 558 jmp near .again 559 .post_jmp: 560 int3 561 %if TMPL_BITS == 16 562 AssertCompile(.post_jmp - .start == 3) 563 %else 564 AssertCompile(.post_jmp - .start == 5) 565 %endif 566 BS3_PROC_END_CMN bs3CpuBasic2_jmp_jv_back__ud2 567 568 569 ; 570 ; When applying opsize, we need to put this in the 16-bit text segment to 571 ; better control where we end up in 32-bit and 64-bit mode. 572 ; 573 ; Try keep the code out of the IVT and BIOS data area. This unfortunately 574 ; requires manual padding here. 575 ; 576 BS3_BEGIN_TEXT16 577 BS3_SET_BITS TMPL_BITS 578 %if TMPL_BITS == 32 579 align 0x100, int3 ; Currently takes us up to 0x400 (max align value is 0x100) 580 times 0x200 int3 ; Brings us up to 0x600. 581 %endif 582 583 BS3_GLOBAL_NAME_EX BS3_CMN_NM(bs3CpuBasic2_jmp_opsize_begin), , 1 584 585 586 ; jmp rel8 (forwards) with opsize override. 587 BS3_CPUBAS2_UD_OFF bs3CpuBasic2_jmp_jb_opsize__ud2 588 BS3_PROC_BEGIN_CMN bs3CpuBasic2_jmp_jb_opsize__ud2, BS3_PBC_NEAR 589 db 66h 590 jmp short .again 591 .post_jmp: 592 times 8 int3 593 .again: ud2 594 int3 595 jmp .again 596 AssertCompile(.post_jmp - BS3_LAST_LABEL == 3) 597 BS3_PROC_END_CMN bs3CpuBasic2_jmp_jb_opsize__ud2 598 599 600 ; jmp rel8 (backwards) with opsize override. 601 BS3_CPUBAS2_UD_OFF bs3CpuBasic2_jmp_jb_opsize_back__ud2 602 BS3_PROC_BEGIN_CMN bs3CpuBasic2_jmp_jb_opsize_back__ud2, BS3_PBC_NEAR 603 jmp .start 604 .again: ud2 605 times 19 int3 606 jmp .again 607 .start: 608 db 66h 609 jmp short .again 610 .post_jmp: 611 int3 612 AssertCompile(.post_jmp - .start == 3) 613 BS3_PROC_END_CMN bs3CpuBasic2_jmp_jb_opsize_back__ud2 614 615 616 ; jmp rel16 (forwards) with opsize override. 617 BS3_CPUBAS2_UD_OFF bs3CpuBasic2_jmp_jv_opsize__ud2 618 BS3_PROC_BEGIN_CMN bs3CpuBasic2_jmp_jv_opsize__ud2, BS3_PBC_NEAR 619 db 66h, 0e9h ; o32 jmp near .again 620 %if TMPL_BITS != 32 621 dd 11 622 %else 623 dw 11 624 %endif 625 .post_jmp: 626 times 11 int3 627 .again: ud2 628 int3 629 jmp .again 630 BS3_PROC_END_CMN bs3CpuBasic2_jmp_jv_opsize__ud2 631 632 633 ; jmp rel16 (backwards) with opsize override. 634 BS3_CPUBAS2_UD_OFF bs3CpuBasic2_jmp_jv_opsize_back__ud2 635 BS3_PROC_BEGIN_CMN bs3CpuBasic2_jmp_jv_opsize_back__ud2, BS3_PBC_NEAR 636 jmp .start 637 .again: ud2 638 int3 639 jmp .again 640 .start: 641 %if TMPL_BITS != 32 642 db 66h, 0e9h ; o32 jmp near .again 643 dd -(6 + 1 + 2 + 2) 644 %else 645 db 66h, 0e9h ; o16 jmp near .again 646 dw -(4 + 1 + 2 + 2) 647 %endif 648 .post_jmp: 649 times 11 int3 650 BS3_PROC_END_CMN bs3CpuBasic2_jmp_jv_opsize_back__ud2 651 652 653 BS3_GLOBAL_NAME_EX BS3_CMN_NM(bs3CpuBasic2_jmp_opsize_end), , 1 654 int3 655 656 501 657 %endif ; BS3_INSTANTIATING_CMN 502 658 -
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-basic-2-x0.c
r96407 r97431 3620 3620 } 3621 3621 3622 3623 3624 /********************************************************************************************************************************* 3625 * JMP Tests * 3626 *********************************************************************************************************************************/ 3627 #define PROTO_ALL(a_Template) \ 3628 FNBS3FAR a_Template ## _c16, \ 3629 a_Template ## _c32, \ 3630 a_Template ## _c64 3631 PROTO_ALL(bs3CpuBasic2_jmp_jb__ud2); 3632 PROTO_ALL(bs3CpuBasic2_jmp_jb_back__ud2); 3633 PROTO_ALL(bs3CpuBasic2_jmp_jv__ud2); 3634 PROTO_ALL(bs3CpuBasic2_jmp_jv_back__ud2); 3635 3636 PROTO_ALL(bs3CpuBasic2_jmp_opsize_begin); 3637 PROTO_ALL(bs3CpuBasic2_jmp_jb_opsize__ud2); 3638 PROTO_ALL(bs3CpuBasic2_jmp_jb_opsize_back__ud2); 3639 PROTO_ALL(bs3CpuBasic2_jmp_jv_opsize__ud2); 3640 PROTO_ALL(bs3CpuBasic2_jmp_jv_opsize_back__ud2); 3641 PROTO_ALL(bs3CpuBasic2_jmp_opsize_end); 3642 #undef PROTO_ALL 3643 3644 FNBS3FAR bs3CpuBasic2_jmptext16_start; 3645 3646 FNBS3FAR bs3CpuBasic2_jmp_target_wrap_forward; 3647 FNBS3FAR bs3CpuBasic2_jmp_jb_wrap_forward__ud2; 3648 FNBS3FAR bs3CpuBasic2_jmp_jb_opsize_wrap_forward__ud2; 3649 FNBS3FAR bs3CpuBasic2_jmp_jv16_wrap_forward__ud2; 3650 FNBS3FAR bs3CpuBasic2_jmp_jv16_opsize_wrap_forward__ud2; 3651 3652 FNBS3FAR bs3CpuBasic2_jmp_target_wrap_backward; 3653 FNBS3FAR bs3CpuBasic2_jmp_jb_wrap_backward__ud2; 3654 FNBS3FAR bs3CpuBasic2_jmp_jb_opsize_wrap_backward__ud2; 3655 FNBS3FAR bs3CpuBasic2_jmp_jv16_wrap_backward__ud2; 3656 FNBS3FAR bs3CpuBasic2_jmp_jv16_opsize_wrap_backward__ud2; 3657 3658 3659 3660 /** 3661 * Entrypoint for JMP tests. 3662 * 3663 * @returns 0 or BS3TESTDOMODE_SKIPPED. 3664 * @param bMode The CPU mode we're testing. 3665 * 3666 * @note When testing v8086 code, we'll be running in v8086 mode. So, careful 3667 * with control registers and such. 3668 */ 3669 BS3_DECL_FAR(uint8_t) BS3_CMN_FAR_NM(bs3CpuBasic2_jmp)(uint8_t bMode) 3670 { 3671 BS3TRAPFRAME TrapCtx; 3672 BS3REGCTX Ctx; 3673 BS3REGCTX CtxExpected; 3674 unsigned iTest; 3675 3676 /* make sure they're allocated */ 3677 Bs3MemZero(&Ctx, sizeof(Ctx)); 3678 Bs3MemZero(&CtxExpected, sizeof(Ctx)); 3679 Bs3MemZero(&TrapCtx, sizeof(TrapCtx)); 3680 3681 bs3CpuBasic2_SetGlobals(bMode); 3682 if (bMode != BS3_MODE_LM64) return BS3TESTDOMODE_SKIPPED; // temp 3683 3684 /* 3685 * Create a context. 3686 */ 3687 Bs3RegCtxSaveEx(&Ctx, bMode, 768); 3688 Bs3MemCpy(&CtxExpected, &Ctx, sizeof(CtxExpected)); 3689 3690 /* 3691 * 16-bit tests. 3692 * 3693 * When opsize is 16-bit relative jumps will do 16-bit calculations and 3694 * modify IP. This means that it is not possible to trigger a segment 3695 * limit #GP(0) when the limit is set to 0xffff. 3696 */ 3697 if (BS3_MODE_IS_16BIT_CODE(bMode)) 3698 { 3699 static struct 3700 { 3701 int8_t iWrap; 3702 bool fOpSizePfx; 3703 FPFNBS3FAR pfnTest; 3704 } 3705 const s_aTests[] = 3706 { 3707 { 0, false, bs3CpuBasic2_jmp_jb__ud2_c16, }, 3708 { 0, false, bs3CpuBasic2_jmp_jb_back__ud2_c16, }, 3709 { 0, true, bs3CpuBasic2_jmp_jb_opsize__ud2_c16, }, 3710 { 0, true, bs3CpuBasic2_jmp_jb_opsize_back__ud2_c16, }, 3711 { 0, false, bs3CpuBasic2_jmp_jv__ud2_c16, }, 3712 { 0, false, bs3CpuBasic2_jmp_jv_back__ud2_c16, }, 3713 { 0, true, bs3CpuBasic2_jmp_jv_opsize__ud2_c16, }, 3714 { 0, true, bs3CpuBasic2_jmp_jv_opsize_back__ud2_c16, }, 3715 3716 { -1, false, bs3CpuBasic2_jmp_jb_wrap_backward__ud2, }, 3717 { +1, false, bs3CpuBasic2_jmp_jb_wrap_forward__ud2, }, 3718 { -1, true, bs3CpuBasic2_jmp_jb_opsize_wrap_backward__ud2, }, 3719 { +1, true, bs3CpuBasic2_jmp_jb_opsize_wrap_forward__ud2, }, 3720 3721 { -1, false, bs3CpuBasic2_jmp_jv16_wrap_backward__ud2, }, 3722 { +1, false, bs3CpuBasic2_jmp_jv16_wrap_forward__ud2, }, 3723 { -1, true, bs3CpuBasic2_jmp_jv16_opsize_wrap_backward__ud2, }, 3724 { +1, true, bs3CpuBasic2_jmp_jv16_opsize_wrap_forward__ud2, }, 3725 }; 3726 3727 if (!BS3_MODE_IS_RM_OR_V86(bMode)) 3728 Bs3SelSetup16BitCode(&Bs3GdteSpare03, Bs3SelLnkPtrToFlat(bs3CpuBasic2_jmptext16_start), 0); 3729 3730 for (iTest = 0; iTest < RT_ELEMENTS(s_aTests); iTest++) 3731 { 3732 if (s_aTests[iTest].iWrap == 0) 3733 { 3734 uint8_t const BS3_FAR *fpbCode; 3735 Bs3RegCtxSetRipCsFromLnkPtr(&Ctx, s_aTests[iTest].pfnTest); 3736 fpbCode = (uint8_t const BS3_FAR *)BS3_FP_MAKE(Ctx.cs, Ctx.rip.u16); 3737 CtxExpected.rip.u = Ctx.rip.u + fpbCode[-1]; 3738 } 3739 else 3740 { 3741 if (BS3_MODE_IS_RM_OR_V86(bMode)) 3742 Ctx.cs = BS3_FP_SEG(s_aTests[iTest].pfnTest); 3743 else 3744 Ctx.cs = BS3_SEL_SPARE_03; 3745 Ctx.rip.u = BS3_FP_OFF(s_aTests[iTest].pfnTest); 3746 if (s_aTests[iTest].fOpSizePfx) 3747 CtxExpected.rip.u = Ctx.rip.u; 3748 else if (s_aTests[iTest].iWrap < 0) 3749 CtxExpected.rip.u = BS3_FP_OFF(bs3CpuBasic2_jmp_target_wrap_backward); 3750 else 3751 CtxExpected.rip.u = BS3_FP_OFF(bs3CpuBasic2_jmp_target_wrap_forward); 3752 } 3753 CtxExpected.cs = Ctx.cs; 3754 Bs3TestPrintf("cs:rip=%04RX16:%04RX64\n", Ctx.cs, Ctx.rip.u); 3755 3756 Bs3TrapSetJmpAndRestore(&Ctx, &TrapCtx); 3757 3758 if (s_aTests[iTest].iWrap == 0 || !s_aTests[iTest].fOpSizePfx) 3759 bs3CpuBasic2_CompareUdCtx(&TrapCtx, &CtxExpected); 3760 else 3761 bs3CpuBasic2_CompareGpCtx(&TrapCtx, &CtxExpected, 0); 3762 3763 g_usBs3TestStep++; 3764 } 3765 3766 /* Limit the wraparound CS segment to exlcude bs3CpuBasic2_jmp_target_wrap_backward 3767 and run the backward wrapping tests. */ 3768 if (!BS3_MODE_IS_RM_OR_V86(bMode)) 3769 { 3770 Bs3GdteSpare03.Gen.u16LimitLow = BS3_FP_OFF(bs3CpuBasic2_jmp_target_wrap_backward) - 1; 3771 CtxExpected.cs = Ctx.cs = BS3_SEL_SPARE_03; 3772 for (iTest = 0; iTest < RT_ELEMENTS(s_aTests); iTest++) 3773 if (s_aTests[iTest].iWrap < 0) 3774 { 3775 CtxExpected.rip.u = Ctx.rip.u = BS3_FP_OFF(s_aTests[iTest].pfnTest); 3776 Bs3TestPrintf("cs:rip=%04RX16:%04RX64 v1\n", Ctx.cs, Ctx.rip.u); 3777 Bs3TrapSetJmpAndRestore(&Ctx, &TrapCtx); 3778 bs3CpuBasic2_CompareGpCtx(&TrapCtx, &CtxExpected, 0); 3779 g_usBs3TestStep++; 3780 } 3781 3782 /* Do another round where we put the limit in the middle of the UD2 3783 instruction we're jumping to: */ 3784 Bs3GdteSpare03.Gen.u16LimitLow = BS3_FP_OFF(bs3CpuBasic2_jmp_target_wrap_backward); 3785 for (iTest = 0; iTest < RT_ELEMENTS(s_aTests); iTest++) 3786 if (s_aTests[iTest].iWrap < 0) 3787 { 3788 Ctx.rip.u = BS3_FP_OFF(s_aTests[iTest].pfnTest); 3789 if (s_aTests[iTest].fOpSizePfx) 3790 CtxExpected.rip.u = Ctx.rip.u; 3791 else 3792 CtxExpected.rip.u = BS3_FP_OFF(bs3CpuBasic2_jmp_target_wrap_backward); 3793 Bs3TestPrintf("cs:rip=%04RX16:%04RX64 v2\n", Ctx.cs, Ctx.rip.u); 3794 Bs3TrapSetJmpAndRestore(&Ctx, &TrapCtx); 3795 bs3CpuBasic2_CompareGpCtx(&TrapCtx, &CtxExpected, 0); 3796 g_usBs3TestStep++; 3797 } 3798 } 3799 3800 } 3801 /* 3802 * 32-bit & 64-bit tests. 3803 */ 3804 else 3805 { 3806 static struct 3807 { 3808 uint8_t cBits; 3809 bool fOpSizePfx; 3810 FPFNBS3FAR pfnTest; 3811 } 3812 const s_aTests[] = 3813 { 3814 { 32, false, bs3CpuBasic2_jmp_jb__ud2_c32, }, 3815 { 32, false, bs3CpuBasic2_jmp_jb_back__ud2_c32, }, 3816 { 32, true, bs3CpuBasic2_jmp_jb_opsize__ud2_c32, }, 3817 { 32, true, bs3CpuBasic2_jmp_jb_opsize_back__ud2_c32, }, 3818 { 32, false, bs3CpuBasic2_jmp_jv__ud2_c32, }, 3819 { 32, false, bs3CpuBasic2_jmp_jv_back__ud2_c32, }, 3820 { 32, true, bs3CpuBasic2_jmp_jv_opsize__ud2_c32, }, 3821 { 32, true, bs3CpuBasic2_jmp_jv_opsize_back__ud2_c32, }, 3822 /* 64bit: */ 3823 { 64, false, bs3CpuBasic2_jmp_jb__ud2_c64, }, 3824 { 64, false, bs3CpuBasic2_jmp_jb_back__ud2_c64, }, 3825 { 64, true, bs3CpuBasic2_jmp_jb_opsize__ud2_c64, }, 3826 { 64, true, bs3CpuBasic2_jmp_jb_opsize_back__ud2_c64, }, 3827 { 64, false, bs3CpuBasic2_jmp_jv__ud2_c64, }, 3828 { 64, false, bs3CpuBasic2_jmp_jv_back__ud2_c64, }, 3829 { 64, true, bs3CpuBasic2_jmp_jv_opsize__ud2_c64, }, 3830 { 64, true, bs3CpuBasic2_jmp_jv_opsize_back__ud2_c64, }, 3831 }; 3832 uint8_t const cBits = BS3_MODE_IS_64BIT_CODE(bMode) ? 64 : 32; 3833 3834 /* Prepare a copy of the UD2 instructions in low memory for opsize prefixed tests. */ 3835 uint16_t const offLow = BS3_FP_OFF(bs3CpuBasic2_jmp_opsize_begin_c32); 3836 uint16_t const cbLow = BS3_FP_OFF(bs3CpuBasic2_jmp_opsize_end_c64) - offLow; 3837 uint8_t BS3_FAR * const pbCode16 = BS3_MAKE_PROT_R0PTR_FROM_FLAT(BS3_ADDR_BS3TEXT16); 3838 uint8_t BS3_FAR * const pbLow = BS3_FP_MAKE(BS3_SEL_TILED_R0, 0); 3839 if (offLow < 0x600 || offLow + cbLow >= BS3_ADDR_STACK_R2) 3840 Bs3TestFailedF("Opsize overriden jumps are out of place: %#x LB %#z\n", offLow, cbLow); 3841 Bs3MemSet(&pbLow[offLow], 0xcc /*int3*/, cbLow); 3842 if (cBits != 64) /** @todo wtf? Intel 10980xe doesn't clear RIP[63:16] for short jumps with o16 prefix. */ 3843 { 3844 for (iTest = 0; iTest < RT_ELEMENTS(s_aTests); iTest++) 3845 if (s_aTests[iTest].fOpSizePfx && s_aTests[iTest].cBits == cBits) 3846 { 3847 uint16_t const offFn = BS3_FP_OFF(s_aTests[iTest].pfnTest); 3848 uint16_t const offUd = offFn + pbCode16[offFn - 1]; 3849 pbCode16[offUd] = 0xf1; /* replace original ud2 with icebp */ 3850 pbCode16[offUd + 1] = 0xf1; 3851 pbLow[offUd] = 0x0f; /* plant ud2 in low memory */ 3852 pbLow[offUd + 1] = 0x0b; 3853 } 3854 } 3855 3856 /* Run the tests. */ 3857 for (iTest = 0; iTest < RT_ELEMENTS(s_aTests); iTest++) 3858 { 3859 if (s_aTests[iTest].cBits == cBits) 3860 { 3861 uint8_t const BS3_FAR *fpbCode = Bs3SelLnkPtrToCurPtr(s_aTests[iTest].pfnTest); 3862 Ctx.rip.u = Bs3SelLnkPtrToFlat(s_aTests[iTest].pfnTest); 3863 CtxExpected.rip.u = Ctx.rip.u + fpbCode[-1]; 3864 if (s_aTests[iTest].fOpSizePfx && cBits != 64) 3865 CtxExpected.rip.u &= UINT16_MAX; 3866 Bs3TestPrintf("cs:rip=%04RX16:%08RX64\n", Ctx.cs, Ctx.rip.u); 3867 3868 if (BS3_MODE_IS_16BIT_SYS(bMode)) 3869 g_uBs3TrapEipHint = s_aTests[iTest].fOpSizePfx ? 0 : Ctx.rip.u32; 3870 Bs3TrapSetJmpAndRestore(&Ctx, &TrapCtx); 3871 3872 bs3CpuBasic2_CompareUdCtx(&TrapCtx, &CtxExpected); 3873 g_usBs3TestStep++; 3874 } 3875 } 3876 3877 Bs3MemSet(&pbLow[offLow], 0xcc /*int3*/, cbLow); 3878 } 3879 3880 return 0; 3881 } 3882 -
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-basic-2.c
r97424 r97431 55 55 FNBS3TESTDOMODE bs3CpuBasic2_lgdt_f16; 56 56 FNBS3TESTDOMODE bs3CpuBasic2_iret_f16; 57 FNBS3TESTDOMODE bs3CpuBasic2_jmp_f16; 57 58 58 59 BS3_DECL_CALLBACK(void) bs3CpuBasic2_Do32BitTests_pe32(); … … 70 71 static const BS3TESTMODEBYONEENTRY g_aModeByOneTests[] = 71 72 { 73 #if 0 72 74 { "#ac", bs3CpuBasic2_RaiseXcpt11_f16, 0 }, 75 #endif 73 76 #if 1 74 { "iret", bs3CpuBasic2_iret_f16, 0 }, 77 //{ "iret", bs3CpuBasic2_iret_f16, 0 }, 78 { "jmp", bs3CpuBasic2_jmp_f16, 0 }, 79 #endif 80 #if 0 75 81 { "sidt", bs3CpuBasic2_sidt_f16, 0 }, 76 82 { "sgdt", bs3CpuBasic2_sgdt_f16, 0 }, … … 91 97 */ 92 98 NOREF(g_aModeTest); NOREF(g_aModeByOneTests); /* for when commenting out bits */ 99 #if 0 93 100 Bs3TestDoModes_rm(g_aModeTest, RT_ELEMENTS(g_aModeTest)); 101 #endif 94 102 Bs3TestDoModesByOne_rm(g_aModeByOneTests, RT_ELEMENTS(g_aModeByOneTests), 0); 95 #if 1103 #if 0 96 104 97 105 /*
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