Changeset 97522 in vbox for trunk/src/VBox/VMM

Timestamp:

Nov 13, 2022 2:45:48 AM (2 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

154546

Message:

VMM/IEM: Dynamically load DR6 in the DRx read & write helper code, we only need it when DR4 or DR5 are accessed to see if such accesses are allowed. This is not very common and there is no point in requiring it. (VT-x code wasn't importing CR4 and we hit an assertion. Adjusted the assertions.)

Location:

trunk/src/VBox/VMM/VMMAll

Files:

• IEMAll.cpp (modified) (2 diffs)
• IEMAllCImpl.cpp (modified) (4 diffs)

trunk/src/VBox/VMM/VMMAll/IEMAll.cpp

@@ -10903 +10903 @@
 {
     IEMEXEC_ASSERT_INSTR_LEN_RETURN(cbInstr, 2);
-    IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK);
+    IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK | CPUMCTX_EXTRN_DR7);
     Assert(iDrReg < 8);
     Assert(iGReg < 16);
@@ -10928 +10928 @@
 {
     IEMEXEC_ASSERT_INSTR_LEN_RETURN(cbInstr, 2);
-    IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK);
+    IEM_CTX_ASSERT(pVCpu, IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK | CPUMCTX_EXTRN_DR7);
     Assert(iDrReg < 8);
     Assert(iGReg < 16);

trunk/src/VBox/VMM/VMMAll/IEMAllCImpl.cpp

@@ -6431 +6431 @@
         return iemRaiseGeneralProtectionFault0(pVCpu);
     Assert(!pVCpu->cpum.GstCtx.eflags.Bits.u1VM);
-    IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_DR7 | CPUMCTX_EXTRN_CR0);
-
-    if (   (iDrReg == 4 || iDrReg == 5)
-        && (pVCpu->cpum.GstCtx.cr4 & X86_CR4_DE) )
-    {
-        Log(("mov r%u,dr%u: CR4.DE=1 -> #GP(0)\n", iGReg, iDrReg));
-        return iemRaiseGeneralProtectionFault0(pVCpu);
+    IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_DR7);
+
+    /** @todo \#UD in outside ring-0 too? */
+    if (iDrReg == 4 || iDrReg == 5)
+    {
+        IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_CR4);
+        if (pVCpu->cpum.GstCtx.cr4 & X86_CR4_DE)
+        {
+            Log(("mov r%u,dr%u: CR4.DE=1 -> #GP(0)\n", iGReg, iDrReg));
+            return iemRaiseGeneralProtectionFault0(pVCpu);
+        }
+        iDrReg += 2;
     }
 
@@ -6470 +6475 @@
             break;
         case 6:
-        case 4:
             IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR6);
             drX = pVCpu->cpum.GstCtx.dr[6];
@@ -6477 +6481 @@
             break;
         case 7:
-        case 5:
             IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_DR7);
             drX = pVCpu->cpum.GstCtx.dr[7];
@@ -6537 +6540 @@
         return iemRaiseGeneralProtectionFault0(pVCpu);
     Assert(!pVCpu->cpum.GstCtx.eflags.Bits.u1VM);
-    IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_DR7 | CPUMCTX_EXTRN_CR4);
+    IEM_CTX_ASSERT(pVCpu, CPUMCTX_EXTRN_DR7);
 
     if (iDrReg == 4 || iDrReg == 5)
     {
+        IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_CR4);
         if (pVCpu->cpum.GstCtx.cr4 & X86_CR4_DE)
         {