Changeset 97564 in vbox

Timestamp:

Nov 16, 2022 9:33:28 AM (2 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

154596

Message:

IEM: Save/restore XMM8-15 based on CPU mode, not operand size in FXSAVE/FXRSTOR. Recalculate FSW.ES from FSW/FCW in FXRSTOR/XRSTOR to ensure consistency.

File:

• trunk/src/VBox/VMM/VMMAll/IEMAllCImpl.cpp (modified) (8 diffs)

trunk/src/VBox/VMM/VMMAll/IEMAllCImpl.cpp

@@ -8581 +8581 @@
     }
 
-    /* XMM registers. */
+    /* XMM registers. Skipped in 64-bit CPL0 if EFER.FFXSR (AMD only) is set. */
     if (   !(pVCpu->cpum.GstCtx.msrEFER & MSR_K6_EFER_FFXSR)
         || pVCpu->iem.s.enmCpuMode != IEMMODE_64BIT
         || pVCpu->iem.s.uCpl != 0)
     {
-        uint32_t cXmmRegs = enmEffOpSize == IEMMODE_64BIT ? 16 : 8;
+        uint32_t cXmmRegs = pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT ? 16 : 8;
         for (uint32_t i = 0; i < cXmmRegs; i++)
             pDst->aXMM[i] = pSrc->aXMM[i];
@@ -8647 +8647 @@
      */
     /** @todo CPU/VM detection possible! If CR4.OSFXSR=0 MXCSR it's
-     * implementation specific whether MXCSR and XMM0-XMM7 are restored. */
+     * implementation specific whether MXCSR and XMM0-XMM7 are
+     * restored according to Intel.
+     * AMD says MXCSR and XMM registers are never loaded if
+     * CR4.OSFXSR=0.
+     */
 
     /* common for all formats */
@@ -8665 +8669 @@
 
     /* FPU IP, CS, DP and DS. */
-    if (pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT)
+    /** @todo AMD says this is only done if FSW.ES is set after loading. */
+    if (enmEffOpSize == IEMMODE_64BIT)
     {
         pDst->FPUIP  = pSrc->FPUIP;
@@ -8684 +8689 @@
     }
 
-    /* XMM registers. */
+    /* XMM registers. Skipped in 64-bit CPL0 if EFER.FFXSR (AMD only) is set.
+     * Does not affect MXCSR, only registers.
+     */
     if (   !(pVCpu->cpum.GstCtx.msrEFER & MSR_K6_EFER_FFXSR)
         || pVCpu->iem.s.enmCpuMode != IEMMODE_64BIT
         || pVCpu->iem.s.uCpl != 0)
     {
-        uint32_t cXmmRegs = enmEffOpSize == IEMMODE_64BIT ? 16 : 8;
+        uint32_t cXmmRegs = pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT ? 16 : 8;
         for (uint32_t i = 0; i < cXmmRegs; i++)
             pDst->aXMM[i] = pSrc->aXMM[i];
     }
+
+    pDst->FCW &= ~X86_FCW_ZERO_MASK;
+    iemFpuRecalcExceptionStatus(pDst);
 
     if (pDst->FSW & X86_FSW_ES)
@@ -8699 +8709 @@
 
     /*
-     * Commit the memory.
+     * Unmap the memory.
      */
     rcStrict = iemMemCommitAndUnmap(pVCpu, pvMem512, IEM_ACCESS_DATA_R);
@@ -8940 +8950 @@
 
     /*
-     * Store the X87 state.
+     * Load the X87 state.
      */
     if (fReqComponents & XSAVE_C_X87)
@@ -8956 +8966 @@
             if (enmEffOpSize == IEMMODE_64BIT)
             {
-                /* Save upper 16-bits of FPUIP (IP:CS:Rsvd1) and FPUDP (DP:DS:Rsvd2). */
+                /* Load upper 16-bits of FPUIP (IP:CS:Rsvd1) and FPUDP (DP:DS:Rsvd2). */
                 pDst->Rsrvd1 = pSrc->Rsrvd1;
                 pDst->Rsrvd2 = pSrc->Rsrvd2;
@@ -8972 +8982 @@
                 pDst->aRegs[i].au32[3] = 0;
             }
+
+            pDst->FCW &= ~X86_FCW_ZERO_MASK;
+            iemFpuRecalcExceptionStatus(pDst);
+
             if (pDst->FSW & X86_FSW_ES)
                 Log11(("xrstor: %04x:%08RX64: loading state with pending FPU exception (FSW=%#x)\n",