Changeset 97580 in vbox for trunk/src/VBox/ValidationKit/bootsectors

Timestamp:

Nov 16, 2022 11:31:13 PM (2 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

154613

Message:

ValKit/bs3-cpu-basic-2: AMD adjustments for the near return tests. bugref:9898

File:

• trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-basic-2-x0.c (modified) (4 diffs)

trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-basic-2-x0.c

@@ -4839 +4839 @@
             { 32,  true,  0, bs3CpuBasic2_retn_i0_opsize__ud2_c64, },
         };
+        BS3CPUVENDOR const enmCpuVendor = Bs3GetCpuVendor();
+        bool const         fFix64OpSize = enmCpuVendor == BS3CPUVENDOR_INTEL; /** @todo what does VIA do? */
 
         /* Prepare a copy of the UD2 instructions in low memory for opsize prefixed tests. */
@@ -4867 +4869 @@
             CtxExpected.rip.u = Ctx.rip.u + (int64_t)(int8_t)fpbCode[-1];
             CtxExpected.cs    = Ctx.cs;
-            if (!s_aTests[iTest].fOpSizePfx)
+            if (!s_aTests[iTest].fOpSizePfx || fFix64OpSize)
                 CtxExpected.rsp.u = Ctx.rsp.u + s_aTests[iTest].cbImm + 8;
             else
             {
-                CtxExpected.rsp.u  = Ctx.rsp.u + s_aTests[iTest].cbImm + 8;
+                CtxExpected.rsp.u  = Ctx.rsp.u + s_aTests[iTest].cbImm + 2;
                 CtxExpected.rip.u &= UINT16_MAX;
             }
@@ -4877 +4879 @@
             Bs3TestPrintf("cs:rip=%04RX16:%04RX64 -> %04RX16:%04RX64\n", Ctx.cs, Ctx.rip.u, CtxExpected.cs, CtxExpected.rip.u);
             //Bs3TestPrintf("ss:rsp=%04RX16:%04RX64\n", Ctx.ss, Ctx.rsp.u);
-            bs3CpuBasic2_retn_PrepStack(StkPtr, &CtxExpected, s_aTests[iTest].fOpSizePfx ? 8 : 8);
+            bs3CpuBasic2_retn_PrepStack(StkPtr, &CtxExpected, s_aTests[iTest].fOpSizePfx && !fFix64OpSize ? 2 : 8);
             Bs3TrapSetJmpAndRestore(&Ctx, &TrapCtx);
             bs3CpuBasic2_CompareUdCtx(&TrapCtx, &CtxExpected);
@@ -4887 +4889 @@
             Ctx.rflags.u16        |= X86_EFL_TF;
             CtxExpected.rflags.u16 = Ctx.rflags.u16;
-            bs3CpuBasic2_retn_PrepStack(StkPtr, &CtxExpected, s_aTests[iTest].fOpSizePfx ? 8 : 8);
+            bs3CpuBasic2_retn_PrepStack(StkPtr, &CtxExpected, s_aTests[iTest].fOpSizePfx && !fFix64OpSize ? 2 : 8);
             Bs3TrapSetJmpAndRestore(&Ctx, &TrapCtx);
             bs3CpuBasic2_CompareDbCtx(&TrapCtx, &CtxExpected, X86_DR6_BS);