Changeset 97582 in vbox

Timestamp:

Nov 16, 2022 11:54:58 PM (2 years ago)

Author:

vboxsync

Message:

ValKit/bs3-cpu-basic-2: More working on near return tests. bugref:9898

Location:

trunk/src/VBox/ValidationKit/bootsectors

Files:

• bs3-cpu-basic-2-template.mac (modified) (2 diffs)
• bs3-cpu-basic-2-x0.c (modified) (5 diffs)

trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-basic-2-template.mac

@@ -1722 +1722 @@
 BS3_PROC_END_CMN   bs3CpuBasic2_retn_i0__ud2
 
+ %if TMPL_BITS == 64
+
+BS3_CPUBAS2_UD_OFF bs3CpuBasic2_retn_rexw__ud2
+BS3_PROC_BEGIN_CMN bs3CpuBasic2_retn_rexw__ud2, BS3_PBC_NEAR
+        db      048h                        ; REX.W
+        ret
+.again: ud2
+        jmp     .again
+BS3_PROC_END_CMN   bs3CpuBasic2_retn_rexw__ud2
+
+BS3_CPUBAS2_UD_OFF bs3CpuBasic2_retn_i24_rexw__ud2
+BS3_PROC_BEGIN_CMN bs3CpuBasic2_retn_i24_rexw__ud2, BS3_PBC_NEAR
+        db      048h                        ; REX.W
+        ret     24
+.again: ud2
+        jmp     .again
+AssertCompile(.again - BS3_LAST_LABEL == 4)
+BS3_PROC_END_CMN   bs3CpuBasic2_retn_i24_rexw__ud2
+
+ %endif
+
 ; Mark the start of opsize tests as we end up below 64K in 32-bit and 64-bit when used.
 BS3_BEGIN_TEXT16 TMPL_BITS
@@ -1753 +1774 @@
 BS3_PROC_END_CMN   bs3CpuBasic2_retn_i0_opsize__ud2
 
+ %if TMPL_BITS == 64
+BS3_CPUBAS2_UD_OFF bs3CpuBasic2_retn_opsize_rexw__ud2
+BS3_PROC_BEGIN_CMN bs3CpuBasic2_retn_opsize_rexw__ud2, BS3_PBC_NEAR
+        db      66h, 048h
+        ret
+.again: ud2
+        jmp     .again
+BS3_PROC_END_CMN   bs3CpuBasic2_retn_opsize_rexw__ud2
+
+BS3_CPUBAS2_UD_OFF bs3CpuBasic2_retn_i24_opsize_rexw__ud2
+BS3_PROC_BEGIN_CMN bs3CpuBasic2_retn_i24_opsize_rexw__ud2, BS3_PBC_NEAR
+        db      66h, 048h
+        ret     24
+.again: ud2
+        jmp     .again
+AssertCompile(.again - BS3_LAST_LABEL == 5)
+BS3_PROC_END_CMN   bs3CpuBasic2_retn_i24_opsize_rexw__ud2
+ %endif
+
 ; End of opsize tests.
 BS3_GLOBAL_NAME_EX BS3_CMN_NM(bs3CpuBasic2_retn_opsize_end), , 1

trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-basic-2-x0.c

@@ -4627 +4627 @@
 PROTO_ALL(bs3CpuBasic2_retn_i0__ud2);
 PROTO_ALL(bs3CpuBasic2_retn_i0_opsize__ud2);
+FNBS3FAR  bs3CpuBasic2_retn_rexw__ud2_c64;
+FNBS3FAR  bs3CpuBasic2_retn_i24_rexw__ud2_c64;
+FNBS3FAR  bs3CpuBasic2_retn_opsize_rexw__ud2_c64;
+FNBS3FAR  bs3CpuBasic2_retn_i24_opsize_rexw__ud2_c64;
 PROTO_ALL(bs3CpuBasic2_retn_opsize_end);
 #undef PROTO_ALL
@@ -4833 +4837 @@
         {
             { 32, false,  0, bs3CpuBasic2_retn__ud2_c64, },
+            { 32, false,  0, bs3CpuBasic2_retn_rexw__ud2_c64, },
             { 32,  true,  0, bs3CpuBasic2_retn_opsize__ud2_c64, },
+            { 32,  true,  0, bs3CpuBasic2_retn_opsize_rexw__ud2_c64, },
             { 32, false, 24, bs3CpuBasic2_retn_i24__ud2_c64, },
+            { 32, false, 24, bs3CpuBasic2_retn_i24_rexw__ud2_c64, },
             { 32,  true, 24, bs3CpuBasic2_retn_i24_opsize__ud2_c64, },
+            { 32,  true, 24, bs3CpuBasic2_retn_i24_opsize_rexw__ud2_c64, },
             { 32, false,  0, bs3CpuBasic2_retn_i0__ud2_c64, },
             { 32,  true,  0, bs3CpuBasic2_retn_i0_opsize__ud2_c64, },
@@ -4842 +4850 @@
         bool const         fFix64OpSize = enmCpuVendor == BS3CPUVENDOR_INTEL; /** @todo what does VIA do? */
 
-        /* Prepare a copy of the UD2 instructions in low memory for opsize prefixed tests. */
+        /* Prepare a copy of the UD2 instructions in low memory for opsize prefixed
+           tests, unless we're on intel where the opsize prefix is ignored. Here we
+           just fill low memory with int3's so we can detect non-intel behaviour.  */
         uint16_t const          offLow   = BS3_FP_OFF(bs3CpuBasic2_retn_opsize_begin_c64);
         uint16_t const          cbLow    = BS3_FP_OFF(bs3CpuBasic2_retn_opsize_end_c64) - offLow;
@@ -4850 +4860 @@
             Bs3TestFailedF("Opsize overriden jumps/calls are out of place: %#x LB %#x\n", offLow, cbLow);
         Bs3MemSet(&pbLow[offLow], 0xcc /*int3*/, cbLow);
-        for (iTest = 0; iTest < RT_ELEMENTS(s_aTests); iTest++)
-            if (s_aTests[iTest].fOpSizePfx)
-            {
-                uint16_t const offFn = BS3_FP_OFF(s_aTests[iTest].pfnTest);
-                uint16_t const offUd = offFn + (int16_t)(int8_t)pbCode16[offFn - 1];
-                BS3_ASSERT(offUd - offLow + 1 < cbLow);
-                pbCode16[offUd]     = 0xf1; /* replace original ud2 with icebp */
-                pbCode16[offUd + 1] = 0xf1;
-                pbLow[offUd]        = 0x0f; /* plant ud2 in low memory */
-                pbLow[offUd + 1]    = 0x0b;
-            }
+        if (!fFix64OpSize)
+            for (iTest = 0; iTest < RT_ELEMENTS(s_aTests); iTest++)
+                if (s_aTests[iTest].fOpSizePfx)
+                {
+                    uint16_t const offFn = BS3_FP_OFF(s_aTests[iTest].pfnTest);
+                    uint16_t const offUd = offFn + (int16_t)(int8_t)pbCode16[offFn - 1];
+                    BS3_ASSERT(offUd - offLow + 1 < cbLow);
+                    pbCode16[offUd]     = 0xf1; /* replace original ud2 with icebp */
+                    pbCode16[offUd + 1] = 0xf1;
+                    pbLow[offUd]        = 0x0f; /* plant ud2 in low memory */
+                    pbLow[offUd + 1]    = 0x0b;
+                }
 
         for (iTest = 0; iTest < RT_ELEMENTS(s_aTests); iTest++)
@@ -4877 +4888 @@
             }
             g_uBs3TrapEipHint = CtxExpected.rip.u32;
-            Bs3TestPrintf("cs:rip=%04RX16:%04RX64 -> %04RX16:%04RX64\n", Ctx.cs, Ctx.rip.u, CtxExpected.cs, CtxExpected.rip.u);
+            //Bs3TestPrintf("cs:rip=%04RX16:%04RX64 -> %04RX16:%04RX64\n", Ctx.cs, Ctx.rip.u, CtxExpected.cs, CtxExpected.rip.u);
             //Bs3TestPrintf("ss:rsp=%04RX16:%04RX64\n", Ctx.ss, Ctx.rsp.u);
             bs3CpuBasic2_retn_PrepStack(StkPtr, &CtxExpected, s_aTests[iTest].fOpSizePfx && !fFix64OpSize ? 2 : 8);