Changeset 97585 in vbox

Timestamp:

Nov 17, 2022 12:12:23 AM (2 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

154618

Message:

ValKit/bs3-cpu-basic-2: Test both variations of rex.w and opsize prefixes since AMD cares about these and the order obviously matters. bugref:9898

Location:

trunk/src/VBox/ValidationKit/bootsectors

Files:

• bs3-cpu-basic-2-template.mac (modified) (2 diffs)
• bs3-cpu-basic-2-x0.c (modified) (2 diffs)

trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-basic-2-template.mac

@@ -1741 +1741 @@
 BS3_PROC_END_CMN   bs3CpuBasic2_retn_i24_rexw__ud2
 
+BS3_CPUBAS2_UD_OFF bs3CpuBasic2_retn_opsize_rexw__ud2
+BS3_PROC_BEGIN_CMN bs3CpuBasic2_retn_opsize_rexw__ud2, BS3_PBC_NEAR
+        db      66h, 048h
+        ret
+.again: ud2
+        jmp     .again
+BS3_PROC_END_CMN   bs3CpuBasic2_retn_opsize_rexw__ud2
+
+BS3_CPUBAS2_UD_OFF bs3CpuBasic2_retn_i24_opsize_rexw__ud2
+BS3_PROC_BEGIN_CMN bs3CpuBasic2_retn_i24_opsize_rexw__ud2, BS3_PBC_NEAR
+        db      66h, 048h
+        ret     24
+.again: ud2
+        jmp     .again
+AssertCompile(.again - BS3_LAST_LABEL == 5)
+BS3_PROC_END_CMN   bs3CpuBasic2_retn_i24_opsize_rexw__ud2
+
  %endif
 
@@ -1775 +1792 @@
 
  %if TMPL_BITS == 64
-BS3_CPUBAS2_UD_OFF bs3CpuBasic2_retn_opsize_rexw__ud2
-BS3_PROC_BEGIN_CMN bs3CpuBasic2_retn_opsize_rexw__ud2, BS3_PBC_NEAR
-        db      66h, 048h
+BS3_CPUBAS2_UD_OFF bs3CpuBasic2_retn_rexw_opsize__ud2
+BS3_PROC_BEGIN_CMN bs3CpuBasic2_retn_rexw_opsize__ud2, BS3_PBC_NEAR
+        db      048h, 66h
         ret
 .again: ud2
         jmp     .again
-BS3_PROC_END_CMN   bs3CpuBasic2_retn_opsize_rexw__ud2
-
-BS3_CPUBAS2_UD_OFF bs3CpuBasic2_retn_i24_opsize_rexw__ud2
-BS3_PROC_BEGIN_CMN bs3CpuBasic2_retn_i24_opsize_rexw__ud2, BS3_PBC_NEAR
-        db      66h, 048h
+BS3_PROC_END_CMN   bs3CpuBasic2_retn_rexw_opsize__ud2
+
+BS3_CPUBAS2_UD_OFF bs3CpuBasic2_retn_i24_rexw_opsize__ud2
+BS3_PROC_BEGIN_CMN bs3CpuBasic2_retn_i24_rexw_opsize__ud2, BS3_PBC_NEAR
+        db      048h, 66h
         ret     24
 .again: ud2
         jmp     .again
 AssertCompile(.again - BS3_LAST_LABEL == 5)
-BS3_PROC_END_CMN   bs3CpuBasic2_retn_i24_opsize_rexw__ud2
+BS3_PROC_END_CMN   bs3CpuBasic2_retn_i24_rexw_opsize__ud2
  %endif
 

trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-basic-2-x0.c

@@ -4630 +4630 @@
 FNBS3FAR  bs3CpuBasic2_retn_i24_rexw__ud2_c64;
 FNBS3FAR  bs3CpuBasic2_retn_opsize_rexw__ud2_c64;
+FNBS3FAR  bs3CpuBasic2_retn_rexw_opsize__ud2_c64;
 FNBS3FAR  bs3CpuBasic2_retn_i24_opsize_rexw__ud2_c64;
+FNBS3FAR  bs3CpuBasic2_retn_i24_rexw_opsize__ud2_c64;
 PROTO_ALL(bs3CpuBasic2_retn_opsize_end);
 #undef PROTO_ALL
@@ -4839 +4841 @@
             { 32, false,  0, bs3CpuBasic2_retn_rexw__ud2_c64, },
             { 32,  true,  0, bs3CpuBasic2_retn_opsize__ud2_c64, },
-            { 32,  true,  0, bs3CpuBasic2_retn_opsize_rexw__ud2_c64, },
+            { 32, false,  0, bs3CpuBasic2_retn_opsize_rexw__ud2_c64, },
+            { 32,  true,  0, bs3CpuBasic2_retn_rexw_opsize__ud2_c64, },
             { 32, false, 24, bs3CpuBasic2_retn_i24__ud2_c64, },
             { 32, false, 24, bs3CpuBasic2_retn_i24_rexw__ud2_c64, },
             { 32,  true, 24, bs3CpuBasic2_retn_i24_opsize__ud2_c64, },
-            { 32,  true, 24, bs3CpuBasic2_retn_i24_opsize_rexw__ud2_c64, },
+            { 32, false, 24, bs3CpuBasic2_retn_i24_opsize_rexw__ud2_c64, },
+            { 32,  true, 24, bs3CpuBasic2_retn_i24_rexw_opsize__ud2_c64, },
             { 32, false,  0, bs3CpuBasic2_retn_i0__ud2_c64, },
             { 32,  true,  0, bs3CpuBasic2_retn_i0_opsize__ud2_c64, },