Changeset 97705 in vbox for trunk/src/VBox/VMM/VMMAll

Timestamp:

Nov 29, 2022 2:11:49 PM (2 years ago)

Author:

vboxsync

Message:

VMM/IEM,DBGF,CPUM: Do debugger I/O breakpoints via the internal EFLAGS bits too. Seems we might need two bits, so had to shift the internal bits down from 24 to 22. bugref:9898

Location:

trunk/src/VBox/VMM/VMMAll

Files:

• DBGFAll.cpp (modified) (2 diffs)
• IEMAllCImpl.cpp (modified) (2 diffs)

trunk/src/VBox/VMM/VMMAll/DBGFAll.cpp

@@ -229 +229 @@
         uint32_t fMatched = 0;
         uint32_t fEnabled = 0;
-        for (unsigned iBp = 0, iBpMask = 1; iBp < 4; iBp++, iBpMask <<= 1)
+        for (unsigned iBp = 0, uBpMask = 1; iBp < 4; iBp++, uBpMask <<= 1)
             if (X86_DR7_IS_EO_CFG(fDr7, iBp))
             {
                 if (fDr7 & X86_DR7_L_G(iBp))
-                    fEnabled |= iBpMask;
+                    fEnabled |= uBpMask;
                 if (pVCpu->cpum.GstCtx.dr[iBp] == GCPtrPC)
-                    fMatched |= iBpMask;
+                    fMatched |= uBpMask;
             }
         if (!(fEnabled & fMatched))
@@ -361 +361 @@
 
 /**
+ * Checks I/O access for guest or hypervisor hardware breakpoints.
+ *
+ * Caller must make sure DR0-3 and DR7 are present in the CPU context before
+ * calling this function.
+ *
+ * @returns CPUMCTX_DBG_DBGF_BP, CPUMCTX_DBG_HIT_DRX_MASK, or 0 (no match).
+ *
+ * @param   pVM         The cross context VM structure.
+ * @param   pVCpu       The cross context virtual CPU structure of the calling EMT.
+ * @param   uIoPort     The I/O port being accessed.
+ * @param   cbValue     The size/width of the access, in bytes.
+ */
+VMM_INT_DECL(uint32_t) DBGFBpCheckIo2(PVMCC pVM, PVMCPUCC pVCpu, RTIOPORT uIoPort, uint8_t cbValue)
+{
+    uint32_t const uIoPortFirst = uIoPort;
+    uint32_t const uIoPortLast  = uIoPortFirst + cbValue - 1;
+
+    /*
+     * Check hyper breakpoints first as the VMM debugger has priority over
+     * the guest.
+     */
+    if (pVM->dbgf.s.cEnabledHwIoBreakpoints > 0)
+        for (unsigned iBp = 0; iBp < RT_ELEMENTS(pVM->dbgf.s.aHwBreakpoints); iBp++)
+        {
+            if (   pVM->dbgf.s.aHwBreakpoints[iBp].fType == X86_DR7_RW_IO
+                && pVM->dbgf.s.aHwBreakpoints[iBp].fEnabled
+                && pVM->dbgf.s.aHwBreakpoints[iBp].hBp   != NIL_DBGFBP)
+            {
+                uint8_t  cbReg      = pVM->dbgf.s.aHwBreakpoints[iBp].cb; Assert(RT_IS_POWER_OF_TWO(cbReg));
+                uint64_t uDrXFirst  = pVM->dbgf.s.aHwBreakpoints[iBp].GCPtr & ~(uint64_t)(cbReg - 1);
+                uint64_t uDrXLast   = uDrXFirst + cbReg - 1;
+                if (uDrXFirst <= uIoPortLast && uDrXLast >= uIoPortFirst)
+                {
+                    /* (See also DBGFRZTrap01Handler.) */
+                    pVCpu->dbgf.s.hBpActive = pVM->dbgf.s.aHwBreakpoints[iBp].hBp;
+                    pVCpu->dbgf.s.fSingleSteppingRaw = false;
+
+                    LogFlow(("DBGFBpCheckIo2: hit hw breakpoint %d at %04x:%RGv (iop %#x L %u)\n",
+                             iBp, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, uIoPort, cbValue));
+                    return CPUMCTX_DBG_DBGF_BP;
+                }
+            }
+        }
+
+    /*
+     * Check the guest.
+     */
+    uint32_t const fDr7 = pVCpu->cpum.GstCtx.dr[7];
+    if (   (fDr7 & X86_DR7_ENABLED_MASK)
+        && X86_DR7_ANY_RW_IO(fDr7)
+        && (pVCpu->cpum.GstCtx.cr4 & X86_CR4_DE) )
+    {
+        uint32_t fEnabled = 0;
+        uint32_t fMatched = 0;
+        for (unsigned iBp = 0, uBpMask = 1; iBp < 4; iBp++, uBpMask <<= 1)
+        {
+            if (fDr7 & X86_DR7_L_G(iBp))
+                fEnabled |= uBpMask;
+            if (X86_DR7_GET_RW(fDr7, iBp) == X86_DR7_RW_IO)
+            {
+                /* ASSUME the breakpoint and the I/O width qualifier uses the same encoding (1 2 x 4). */
+                static uint8_t const s_abInvAlign[4] = { 0, 1, 7, 3 };
+                uint8_t  const cbInvAlign = s_abInvAlign[X86_DR7_GET_LEN(fDr7, iBp)];
+                uint64_t const uDrXFirst  = pVCpu->cpum.GstCtx.dr[iBp] & ~(uint64_t)cbInvAlign;
+                uint64_t const uDrXLast   = uDrXFirst + cbInvAlign;
+                if (uDrXFirst <= uIoPortLast && uDrXLast >= uIoPortFirst)
+                    fMatched |= uBpMask;
+            }
+        }
+        if (fEnabled & fMatched)
+        {
+            LogFlow(("DBGFBpCheckIo2: hit hw breakpoint %#x at %04x:%RGv (iop %#x L %u)\n",
+                     fMatched, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.rip, uIoPort, cbValue));
+            return fMatched << CPUMCTX_DBG_HIT_DRX_SHIFT;
+        }
+    }
+
+    return 0;
+}
+
+
+/**
  * Returns the single stepping state for a virtual CPU.
  *

trunk/src/VBox/VMM/VMMAll/IEMAllCImpl.cpp

@@ -7346 +7346 @@
         if (rcStrict != VINF_SUCCESS)
             iemSetPassUpStatus(pVCpu, rcStrict);
+
+        /*
+         * Check for I/O breakpoints before we complete the instruction.
+         */
+        uint32_t const fDr7 = pVCpu->cpum.GstCtx.dr[7];
+        if (RT_UNLIKELY(   (   (   (fDr7 & X86_DR7_ENABLED_MASK)
+                                && X86_DR7_ANY_RW_IO(fDr7)
+                                && (pVCpu->cpum.GstCtx.cr4 & X86_CR4_DE))
+                            || pVM->dbgf.ro.cEnabledHwIoBreakpoints > 0)
+                        && rcStrict == VINF_SUCCESS))
+        {
+            IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR0_DR3 | CPUMCTX_EXTRN_DR6);
+            pVCpu->cpum.GstCtx.eflags.uBoth |= DBGFBpCheckIo2(pVM, pVCpu, u16Port, cbReg);
+        }
+
         rcStrict = iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
-
-        /*
-         * Check for I/O breakpoints.
-         */
-        /** @todo this should set a internal flag and be raised by
-         *        iemRegAddToRipAndFinishingClearingRF! */
-        uint32_t const uDr7 = pVCpu->cpum.GstCtx.dr[7];
-        if (RT_UNLIKELY(   (   (   (uDr7 & X86_DR7_ENABLED_MASK)
-                                && X86_DR7_ANY_RW_IO(uDr7)
-                                && (pVCpu->cpum.GstCtx.cr4 & X86_CR4_DE))
-                            || DBGFBpIsHwIoArmed(pVM))
-                        && rcStrict == VINF_SUCCESS))
-        {
-            IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR0_DR3 | CPUMCTX_EXTRN_DR6);
-            rcStrict = DBGFBpCheckIo(pVM, pVCpu, IEM_GET_CTX(pVCpu), u16Port, cbReg);
-            if (rcStrict == VINF_EM_RAW_GUEST_TRAP)
-                rcStrict = iemRaiseDebugException(pVCpu);
-        }
     }
 
@@ -7458 +7455 @@
         if (rcStrict != VINF_SUCCESS)
             iemSetPassUpStatus(pVCpu, rcStrict);
+
+        /*
+         * Check for I/O breakpoints before we complete the instruction.
+         */
+        uint32_t const fDr7 = pVCpu->cpum.GstCtx.dr[7];
+        if (RT_UNLIKELY(   (   (   (fDr7 & X86_DR7_ENABLED_MASK)
+                                && X86_DR7_ANY_RW_IO(fDr7)
+                                && (pVCpu->cpum.GstCtx.cr4 & X86_CR4_DE))
+                            || pVM->dbgf.ro.cEnabledHwIoBreakpoints > 0)
+                        && rcStrict == VINF_SUCCESS))
+        {
+            IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR0_DR3 | CPUMCTX_EXTRN_DR6);
+            pVCpu->cpum.GstCtx.eflags.uBoth |= DBGFBpCheckIo2(pVM, pVCpu, u16Port, cbReg);
+        }
+
         rcStrict = iemRegAddToRipAndFinishingClearingRF(pVCpu, cbInstr);
-
-        /*
-         * Check for I/O breakpoints.
-         */
-        /** @todo this should set a internal flag and be raised by
-         *        iemRegAddToRipAndFinishingClearingRF! */
-        uint32_t const uDr7 = pVCpu->cpum.GstCtx.dr[7];
-        if (RT_UNLIKELY(   (   (   (uDr7 & X86_DR7_ENABLED_MASK)
-                                && X86_DR7_ANY_RW_IO(uDr7)
-                                && (pVCpu->cpum.GstCtx.cr4 & X86_CR4_DE))
-                            || DBGFBpIsHwIoArmed(pVM))
-                        && rcStrict == VINF_SUCCESS))
-        {
-            IEM_CTX_IMPORT_RET(pVCpu, CPUMCTX_EXTRN_DR0_DR3 | CPUMCTX_EXTRN_DR6);
-            rcStrict = DBGFBpCheckIo(pVM, pVCpu, IEM_GET_CTX(pVCpu), u16Port, cbReg);
-            if (rcStrict == VINF_EM_RAW_GUEST_TRAP)
-                rcStrict = iemRaiseDebugException(pVCpu);
-        }
     }
     return rcStrict;