VirtualBox

Changeset 9798 in vbox


Ignore:
Timestamp:
Jun 18, 2008 3:47:24 PM (17 years ago)
Author:
vboxsync
svn:sync-xref-src-repo-rev:
32167
Message:

fs & gs base fixes

File:
1 edited

Legend:

Unmodified
Added
Removed
  • trunk/src/recompiler/VBoxRecompiler.c

    r9769 r9798  
    16971697    pVM->rem.s.Env.kernelgsbase = pCtx->msrKERNELGSBASE;
    16981698#endif
    1699     /* Note that FS_BASE & GS_BASE are already synced; QEmu keeps them in the hidden selector registers.
    1700      * So we basically assume the hidden registers are in sync with these MSRs (vt-x & amd-v). Correct??
    1701      */
    17021699
    17031700
     
    18281825        cpu_x86_load_seg_cache(&pVM->rem.s.Env, R_DS, pCtx->ds, pCtx->dsHid.u64Base, pCtx->dsHid.u32Limit, (pCtx->dsHid.Attr.u << 8) & 0xFFFFFF);
    18291826        cpu_x86_load_seg_cache(&pVM->rem.s.Env, R_ES, pCtx->es, pCtx->esHid.u64Base, pCtx->esHid.u32Limit, (pCtx->esHid.Attr.u << 8) & 0xFFFFFF);
    1830         cpu_x86_load_seg_cache(&pVM->rem.s.Env, R_FS, pCtx->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, (pCtx->fsHid.Attr.u << 8) & 0xFFFFFF);
    1831         cpu_x86_load_seg_cache(&pVM->rem.s.Env, R_GS, pCtx->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, (pCtx->gsHid.Attr.u << 8) & 0xFFFFFF);
     1827
     1828        /* FS & GS base addresses need to be loaded from the MSRs if in 64 bits mode. */
     1829        if (CPUMIsGuestIn64BitCode(pVM, CPUMCTX2CORE(pCtx)))
     1830        {
     1831            /* Note that the base values in the hidden fs & gs registers are cut to 32 bits and can't be used in this case. */
     1832            cpu_x86_load_seg_cache(&pVM->rem.s.Env, R_FS, pCtx->fs, pCtx->msrFSBASE, pCtx->fsHid.u32Limit, (pCtx->fsHid.Attr.u << 8) & 0xFFFFFF);
     1833            cpu_x86_load_seg_cache(&pVM->rem.s.Env, R_GS, pCtx->gs, pCtx->msrGSBASE, pCtx->gsHid.u32Limit, (pCtx->gsHid.Attr.u << 8) & 0xFFFFFF);
     1834        }
     1835        else
     1836        {
     1837            cpu_x86_load_seg_cache(&pVM->rem.s.Env, R_FS, pCtx->fs, pCtx->fsHid.u64Base, pCtx->fsHid.u32Limit, (pCtx->fsHid.Attr.u << 8) & 0xFFFFFF);
     1838            cpu_x86_load_seg_cache(&pVM->rem.s.Env, R_GS, pCtx->gs, pCtx->gsHid.u64Base, pCtx->gsHid.u32Limit, (pCtx->gsHid.Attr.u << 8) & 0xFFFFFF);
     1839        }
    18321840    }
    18331841    else
Note: See TracChangeset for help on using the changeset viewer.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette