Changeset 98355 in vbox
- Timestamp:
- Jan 31, 2023 9:08:28 AM (2 years ago)
- File:
-
- 1 edited
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trunk/src/VBox/VMM/VMMR3/CPUM.cpp
r98103 r98355 1531 1531 * CPU features and/or micro-architecture/generation. Why? Ask Intel. 1532 1532 */ 1533 uint64_t const uHostMsr = fIsNstGstHwExecAllowed ? pHostVmxMsrs->u64Cr0Fixed1 : VMX_V_CR0_FIXED1; 1534 pGuestVmxMsrs->u64Cr0Fixed1 = uHostMsr | pGuestVmxMsrs->u64Cr0Fixed0; /* Make sure the CR0 MB1 bits are not clear. */ 1533 pGuestVmxMsrs->u64Cr0Fixed1 = fIsNstGstHwExecAllowed ? pHostVmxMsrs->u64Cr0Fixed1 : VMX_V_CR0_FIXED1; 1534 1535 /* Make sure the CR0 MB1 bits are not clear. */ 1536 Assert((pGuestVmxMsrs->u64Cr0Fixed1 & pGuestVmxMsrs->u64Cr0Fixed0) == pGuestVmxMsrs->u64Cr0Fixed0); 1535 1537 } 1536 1538 … … 1540 1542 /* CR4 Fixed-1. */ 1541 1543 { 1542 uint64_t const uHostMsr = fIsNstGstHwExecAllowed ? pHostVmxMsrs->u64Cr4Fixed1 : CPUMGetGuestCR4ValidMask(pVM); 1543 pGuestVmxMsrs->u64Cr4Fixed1 = uHostMsr | pGuestVmxMsrs->u64Cr4Fixed0; /* Make sure the CR4 MB1 bits are not clear. */ 1544 pGuestVmxMsrs->u64Cr4Fixed1 = CPUMGetGuestCR4ValidMask(pVM) & pHostVmxMsrs->u64Cr4Fixed1; 1545 1546 /* Make sure the CR4 MB1 bits are not clear. */ 1547 Assert((pGuestVmxMsrs->u64Cr4Fixed1 & pGuestVmxMsrs->u64Cr4Fixed0) == pGuestVmxMsrs->u64Cr4Fixed0); 1548 1549 /* Make sure bits that must always be set are set. */ 1550 Assert(pGuestVmxMsrs->u64Cr4Fixed1 & X86_CR4_PAE); 1551 Assert(pGuestVmxMsrs->u64Cr4Fixed1 & X86_CR4_VMXE); 1544 1552 } 1545 1553
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