VirtualBox

Changeset 9857 in vbox for trunk/src/VBox/VMM


Ignore:
Timestamp:
Jun 20, 2008 2:34:46 PM (16 years ago)
Author:
vboxsync
Message:

Updates for amd64 paging

Location:
trunk/src/VBox/VMM/VMMAll
Files:
3 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/VMM/VMMAll/PGMAllBth.h

    r9855 r9857  
    960960# endif /* IN_RING3 */
    961961
     962# if PGM_GST_TYPE == PGM_TYPE_AMD64
     963    /* Fetch the pgm pool shadow descriptor. */
     964    PPGMPOOLPAGE pShwPdpt = pgmPoolGetPageByHCPhys(pVM, pPml4eDst->u & SHW_PDPT_MASK);
     965    Assert(pShwPdpt);
     966# endif
    962967
    963968# if PGM_GST_TYPE == PGM_TYPE_PAE || PGM_GST_TYPE == PGM_TYPE_AMD64
     969    PPGMPOOL pPool = pVM->pgm.s.CTXSUFF(pPool);
     970
    964971    /* Fetch the pgm pool shadow descriptor. */
    965     PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(pVM, pPdptDst->a[iPdPte].u & X86_PDPE_PG_MASK);
     972    PPGMPOOLPAGE pShwPde = pgmPoolGetPageByHCPhys(pVM, pPdptDst->a[iPdPte].u & SHW_PDPE_PG_MASK);
    966973    Assert(pShwPde);
    967974# endif
    … …  
    977984             * Mark not present so we can resync the PML4E when it's used.
    978985             */
    979             LogFlow(("InvalidatePage: Out-of-sync PML4E at %VGp Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
     986            LogFlow(("InvalidatePage: Out-of-sync PML4E at %VGv Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
    980987                     GCPtrPage, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
    981             pgmPoolFree(pVM, pPml4eDst->u & X86_PML4E_PG_MASK, PGMPOOL_IDX_PML4, iPml4e);
     988            pgmPoolFreeByPage(pPool, pShwPdpt, PGMPOOL_IDX_PML4, iPml4e);
    982989            pPml4eDst->u = 0;
    983990            STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDOutOfSync));
    … …  
    989996             * Mark not present so we can set the accessed bit.
    990997             */
    991             LogFlow(("InvalidatePage: Out-of-sync PML4E (A) at %VGp Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
     998            LogFlow(("InvalidatePage: Out-of-sync PML4E (A) at %VGv Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
    992999                     GCPtrPage, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
    993             pgmPoolFree(pVM, pPml4eDst->u & X86_PML4E_PG_MASK, PGMPOOL_IDX_PML4, iPml4e);
     1000            pgmPoolFreeByPage(pPool, pShwPdpt, PGMPOOL_IDX_PML4, iPml4e);
    9941001            pPml4eDst->u = 0;
    9951002            STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDNAs));
    … …  
    9991006    else
    10001007    {
    1001         LogFlow(("InvalidatePage: Out-of-sync PML4E (P) at %VGp Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
     1008        LogFlow(("InvalidatePage: Out-of-sync PML4E (P) at %VGv Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
    10021009                    GCPtrPage, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
    1003         pgmPoolFree(pVM, pPml4eDst->u & X86_PML4E_PG_MASK, PGMPOOL_IDX_PML4, iPml4e);
     1010        pgmPoolFreeByPage(pPool, pShwPdpt, PGMPOOL_IDX_PML4, iPml4e);
    10041011        pPml4eDst->u = 0;
    10051012        STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDNPs));
    … …  
    10071014        return VINF_SUCCESS;
    10081015    }
     1016    RTGCPHYS GCPhysPdpt = pPml4eSrc->u & GST_PDPT_MASK;
     1017
     1018    /* Check if the PML4 entry has changed. */
     1019    if (pShwPdpt->GCPhys != GCPhysPdpt)
     1020    {
     1021        LogFlow(("InvalidatePage: Out-of-sync PML4E (GCPhys) at %VGv %VGp vs %VGp PdpeSrc=%RX64 PdpeDst=%RX64\n",
     1022                    GCPtrPage, pShwPdpt->GCPhys, GCPhysPdpt, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
     1023        pgmPoolFreeByPage(pPool, pShwPdpt, PGMPOOL_IDX_PML4, iPml4e);
     1024        pPml4eDst->u = 0;
     1025        STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDNPs));
     1026        PGM_INVL_PG(GCPtrPage);
     1027    }
     1028
    10091029
    10101030    Assert(pPdpeDst->n.u1Present && pPdpeDst->u & SHW_PDPT_MASK);
    … …  
    10151035        {
    10161036            /*
    1017              * Mark not present so we can resync the PML4E when it's used.
     1037             * Mark not present so we can resync the PDPTE when it's used.
    10181038             */
    1019             LogFlow(("InvalidatePage: Out-of-sync PDPE at %VGp PdpeSrc=%RX64 PdpeDst=%RX64\n",
     1039            LogFlow(("InvalidatePage: Out-of-sync PDPE at %VGv PdpeSrc=%RX64 PdpeDst=%RX64\n",
    10201040                     GCPtrPage, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
    1021             pgmPoolFree(pVM, pPdpeDst->u & SHW_PDPT_MASK, PGMPOOL_IDX_PML4, iPml4e);
     1041            pgmPoolFreeByPage(pPool, pShwPde, pShwPdpt->idx, iPdPte);
    10221042            pPdpeDst->u = 0;
    10231043            STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDOutOfSync));
    … …  
    10291049             * Mark not present so we can set the accessed bit.
    10301050             */
    1031             LogFlow(("InvalidatePage: Out-of-sync PDPE (A) at %VGp PdpeSrc=%RX64 PdpeDst=%RX64\n",
     1051            LogFlow(("InvalidatePage: Out-of-sync PDPE (A) at %VGv PdpeSrc=%RX64 PdpeDst=%RX64\n",
    10321052                     GCPtrPage, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
    1033             pgmPoolFree(pVM, pPdpeDst->u & SHW_PDPT_MASK, PGMPOOL_IDX_PML4, iPml4e);
     1053            pgmPoolFreeByPage(pPool, pShwPde, pShwPdpt->idx, iPdPte);
    10341054            pPdpeDst->u = 0;
    10351055            STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDNAs));
    … …  
    10391059    else
    10401060    {
    1041         LogFlow(("InvalidatePage: Out-of-sync PDPE (P) at %VGp PdpeSrc=%RX64 PdpeDst=%RX64\n",
     1061        LogFlow(("InvalidatePage: Out-of-sync PDPE (P) at %VGv PdpeSrc=%RX64 PdpeDst=%RX64\n",
    10421062                    GCPtrPage, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
    1043         pgmPoolFree(pVM, pPdpeDst->u & SHW_PDPT_MASK, PGMPOOL_IDX_PDPT, iPDDst);
     1063        pgmPoolFreeByPage(pPool, pShwPde, pShwPdpt->idx, iPdPte);
    10441064        pPdpeDst->u = 0;
    10451065        STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDNPs));
    10461066        PGM_INVL_PG(GCPtrPage);
    10471067        return VINF_SUCCESS;
     1068    }
     1069    RTGCPHYS GCPhysPd = PdpeSrc.u & GST_PDPE_PG_MASK;
     1070
     1071    /* Check if the PDPT entry has changed. */
     1072    if (pShwPde->GCPhys != GCPhysPd)
     1073    {
     1074        LogFlow(("InvalidatePage: Out-of-sync PDPE (GCPhys) at %VGv %VGp vs %VGp PdpeSrc=%RX64 PdpeDst=%RX64\n",
     1075                    GCPtrPage, pShwPde->GCPhys, GCPhysPd, (uint64_t)PdpeSrc.u, (uint64_t)pPdpeDst->u));
     1076        pgmPoolFreeByPage(pPool, pShwPde, pShwPdpt->idx, iPdPte);
     1077        pPdpeDst->u = 0;
     1078        STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDNPs));
     1079        PGM_INVL_PG(GCPtrPage);
    10481080    }
    10491081# endif

  • trunk/src/VBox/VMM/VMMAll/PGMAllGst.h

    r9701 r9857  
    8888#  define GST_TOTAL_PD_ENTRIES      (X86_PG_PAE_ENTRIES * X86_PG_PAE_PDPE_ENTRIES)
    8989#  define GST_PDPE_ENTRIES          X86_PG_PAE_PDPE_ENTRIES
     90#  define GST_PDPE_PG_MASK          X86_PDPE_PG_MASK
    9091#  define GST_PDPT_SHIFT            X86_PDPT_SHIFT
    9192#  define GST_PDPT_MASK             X86_PDPT_MASK_PAE
    … …  
    9596#  define GST_PDPE_ENTRIES          X86_PG_AMD64_PDPE_ENTRIES
    9697#  define GST_PDPT_SHIFT            X86_PDPT_SHIFT
     98#  define GST_PDPE_PG_MASK          X86_PDPE_PG_MASK_FULL
    9799#  define GST_PDPT_MASK             X86_PDPT_MASK_AMD64
    98100#  define GST_PTE_PG_MASK           X86_PTE_PAE_PG_MASK_FULL

  • trunk/src/VBox/VMM/VMMAll/PGMAllShw.h

    r9692 r9857  
    7575# define SHW_PT_MASK            X86_PT_PAE_MASK
    7676#if PGM_SHW_TYPE == PGM_TYPE_AMD64
    77 # define SHW_PDPT_SHIFT        X86_PDPT_SHIFT
    78 # define SHW_PDPT_MASK         X86_PDPT_MASK_AMD64
     77# define SHW_PDPT_SHIFT         X86_PDPT_SHIFT
     78# define SHW_PDPT_MASK          X86_PDPT_MASK_AMD64
     79# define SHW_PDPE_PG_MASK       X86_PDPE_PG_MASK
    7980# define SHW_TOTAL_PD_ENTRIES   (X86_PG_AMD64_ENTRIES*X86_PG_AMD64_PDPE_ENTRIES)
    8081# define SHW_POOL_ROOT_IDX      PGMPOOL_IDX_PAE_PD
    8182#else /* 32 bits PAE mode */
    82 # define SHW_PDPT_SHIFT        X86_PDPT_SHIFT
    83 # define SHW_PDPT_MASK         X86_PDPT_MASK_PAE
     83# define SHW_PDPT_SHIFT         X86_PDPT_SHIFT
     84# define SHW_PDPT_MASK          X86_PDPT_MASK_PAE
     85# define SHW_PDPE_PG_MASK       X86_PDPE_PG_MASK
    8486# define SHW_TOTAL_PD_ENTRIES   (X86_PG_PAE_ENTRIES*X86_PG_PAE_PDPE_ENTRIES)
    8587# define SHW_POOL_ROOT_IDX      PGMPOOL_IDX_PAE_PD
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