Changeset 98704 in vbox
- Timestamp:
- Feb 23, 2023 3:12:48 PM (21 months ago)
- Location:
- trunk/src/VBox/ValidationKit/bootsectors
- Files:
-
- 2 edited
-
bs3-cpu-instr-3-template.mac (modified) (1 diff)
-
bs3-cpu-instr-3.c32 (modified) (9 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3-template.mac
r98103 r98704 2600 2600 2601 2601 ; 2602 ; SHA1NEXTE 2603 ; 2604 EMIT_INSTR_PLUS_ICEBP sha1nexte, XMM1, XMM2 2605 EMIT_INSTR_PLUS_ICEBP sha1nexte, XMM1, FSxBX 2606 %if TMPL_BITS == 64 2607 EMIT_INSTR_PLUS_ICEBP sha1nexte, XMM9, XMM8 2608 EMIT_INSTR_PLUS_ICEBP sha1nexte, XMM9, FSxBX 2609 %endif 2610 2611 ; 2612 ; SHA1MSG1 2613 ; 2614 EMIT_INSTR_PLUS_ICEBP sha1msg1, XMM1, XMM2 2615 EMIT_INSTR_PLUS_ICEBP sha1msg1, XMM1, FSxBX 2616 %if TMPL_BITS == 64 2617 EMIT_INSTR_PLUS_ICEBP sha1msg1, XMM9, XMM8 2618 EMIT_INSTR_PLUS_ICEBP sha1msg1, XMM9, FSxBX 2619 %endif 2620 2621 ; 2622 ; SHA1MSG2 2623 ; 2624 EMIT_INSTR_PLUS_ICEBP sha1msg2, XMM1, XMM2 2625 EMIT_INSTR_PLUS_ICEBP sha1msg2, XMM1, FSxBX 2626 %if TMPL_BITS == 64 2627 EMIT_INSTR_PLUS_ICEBP sha1msg2, XMM9, XMM8 2628 EMIT_INSTR_PLUS_ICEBP sha1msg2, XMM9, FSxBX 2629 %endif 2630 2631 ; 2632 ; SHA256MSG1 2633 ; 2634 EMIT_INSTR_PLUS_ICEBP sha256msg1, XMM1, XMM2 2635 EMIT_INSTR_PLUS_ICEBP sha256msg1, XMM1, FSxBX 2636 %if TMPL_BITS == 64 2637 EMIT_INSTR_PLUS_ICEBP sha256msg1, XMM9, XMM8 2638 EMIT_INSTR_PLUS_ICEBP sha256msg1, XMM9, FSxBX 2639 %endif 2640 2641 ; 2642 ; SHA256MSG2 2643 ; 2644 EMIT_INSTR_PLUS_ICEBP sha256msg2, XMM1, XMM2 2645 EMIT_INSTR_PLUS_ICEBP sha256msg2, XMM1, FSxBX 2646 %if TMPL_BITS == 64 2647 EMIT_INSTR_PLUS_ICEBP sha256msg2, XMM9, XMM8 2648 EMIT_INSTR_PLUS_ICEBP sha256msg2, XMM9, FSxBX 2649 %endif 2650 2651 ; 2652 ; SHA1RNDS4 2653 ; 2654 EMIT_INSTR_PLUS_ICEBP sha1rnds4, XMM1, XMM2, 000h 2655 EMIT_INSTR_PLUS_ICEBP sha1rnds4, XMM1, FSxBX, 000h 2656 EMIT_INSTR_PLUS_ICEBP sha1rnds4, XMM1, XMM2, 001h 2657 EMIT_INSTR_PLUS_ICEBP sha1rnds4, XMM1, FSxBX, 001h 2658 EMIT_INSTR_PLUS_ICEBP sha1rnds4, XMM1, XMM2, 002h 2659 EMIT_INSTR_PLUS_ICEBP sha1rnds4, XMM1, FSxBX, 002h 2660 EMIT_INSTR_PLUS_ICEBP sha1rnds4, XMM1, XMM2, 003h 2661 EMIT_INSTR_PLUS_ICEBP sha1rnds4, XMM1, FSxBX, 003h 2662 %if TMPL_BITS == 64 2663 EMIT_INSTR_PLUS_ICEBP sha1rnds4, XMM9, XMM8, 000h 2664 EMIT_INSTR_PLUS_ICEBP sha1rnds4, XMM9, FSxBX, 000h 2665 EMIT_INSTR_PLUS_ICEBP sha1rnds4, XMM9, XMM8, 001h 2666 EMIT_INSTR_PLUS_ICEBP sha1rnds4, XMM9, FSxBX, 001h 2667 EMIT_INSTR_PLUS_ICEBP sha1rnds4, XMM9, XMM8, 002h 2668 EMIT_INSTR_PLUS_ICEBP sha1rnds4, XMM9, FSxBX, 002h 2669 EMIT_INSTR_PLUS_ICEBP sha1rnds4, XMM9, XMM8, 003h 2670 EMIT_INSTR_PLUS_ICEBP sha1rnds4, XMM9, FSxBX, 003h 2671 %endif 2672 2673 ; 2674 ; SHA256RNDS2 (xmm0 is implicit) 2675 ; 2676 EMIT_INSTR_PLUS_ICEBP sha256rnds2, XMM1, XMM2, XMM0 2677 EMIT_INSTR_PLUS_ICEBP sha256rnds2, XMM1, FSxBX, XMM0 2678 %if TMPL_BITS == 64 2679 EMIT_INSTR_PLUS_ICEBP sha256rnds2, XMM8, XMM9, XMM0 2680 EMIT_INSTR_PLUS_ICEBP sha256rnds2, XMM8, FSxBX, XMM0 2681 %endif 2682 2683 ; 2602 2684 ; [V]PBLENDVB 2603 2685 ; -
trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3.c32
r98103 r98704 82 82 T_SSE4A, 83 83 T_PCLMUL, 84 T_SHA, 84 85 T_AVX_128, 85 86 T_AVX2_128, … … 141 142 * Global Variables * 142 143 *********************************************************************************************************************************/ 143 static bool g_afTypeSupports[T_MAX] = { false, false, false, false, false, false, false, false, false };144 static bool g_afTypeSupports[T_MAX] = { false, false, false, false, false, false, false, false, false, false }; 144 145 static bool g_fAmdMisalignedSse = false; 145 146 … … 731 732 Bs3ExtCtxSetYmm(pExtCtx, paTests[iTest].iRegDst, &paValues[iVal].uDstOut, cbOperand); 732 733 } 734 #if defined(DEBUG_aeichner) /** @todo Necessary kludge on a i7-1068NG7. */ 735 if ( pExtCtx->enmMethod == BS3EXTCTXMETHOD_XSAVE 736 && pExtCtx->Ctx.x.Hdr.bmXState == 0x7 737 && pExtCtxOut->Ctx.x.Hdr.bmXState == 0x3) 738 pExtCtxOut->Ctx.x.Hdr.bmXState = 0x7; 733 739 Bs3TestCheckExtCtx(pExtCtxOut, pExtCtx, 0 /*fFlags*/, pszMode, idTestStep); 740 #endif 734 741 735 742 if (TrapFrame.bXcpt != bXcptExpect) … … 7498 7505 { bs3CpuInstr3_vpclmulqdq_XMM8_XMM9_XMM10_000h_icebp_c64, 255, RM_REG, T_AVX_PCLMUL, 8, 9, 10, RT_ELEMENTS(s_aValues00), s_aValues00 }, 7499 7506 { bs3CpuInstr3_vpclmulqdq_XMM8_XMM9_FSxBX_000h_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_PCLMUL, 8, 9, 255, RT_ELEMENTS(s_aValues00), s_aValues00 }, 7507 }; 7508 static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); 7509 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); 7510 return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, 7511 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); 7512 } 7513 7514 7515 /* 7516 * SHA1NEXTE / SHA1MSG1 / SHA1MSG2 / SHA256MSG1 / SHA256MSG2 / SHA1RNDS4 7517 */ 7518 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_sha1nexte_XMM1_XMM2_icebp); 7519 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_sha1nexte_XMM1_FSxBX_icebp); 7520 extern FNBS3FAR bs3CpuInstr3_sha1nexte_XMM9_XMM8_icebp_c64; 7521 extern FNBS3FAR bs3CpuInstr3_sha1nexte_XMM9_FSxBX_icebp_c64; 7522 7523 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_sha1msg1_XMM1_XMM2_icebp); 7524 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_sha1msg1_XMM1_FSxBX_icebp); 7525 extern FNBS3FAR bs3CpuInstr3_sha1msg1_XMM9_XMM8_icebp_c64; 7526 extern FNBS3FAR bs3CpuInstr3_sha1msg1_XMM9_FSxBX_icebp_c64; 7527 7528 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_sha1msg2_XMM1_XMM2_icebp); 7529 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_sha1msg2_XMM1_FSxBX_icebp); 7530 extern FNBS3FAR bs3CpuInstr3_sha1msg2_XMM9_XMM8_icebp_c64; 7531 extern FNBS3FAR bs3CpuInstr3_sha1msg2_XMM9_FSxBX_icebp_c64; 7532 7533 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_sha256msg1_XMM1_XMM2_icebp); 7534 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_sha256msg1_XMM1_FSxBX_icebp); 7535 extern FNBS3FAR bs3CpuInstr3_sha256msg1_XMM9_XMM8_icebp_c64; 7536 extern FNBS3FAR bs3CpuInstr3_sha256msg1_XMM9_FSxBX_icebp_c64; 7537 7538 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_sha256msg2_XMM1_XMM2_icebp); 7539 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_sha256msg2_XMM1_FSxBX_icebp); 7540 extern FNBS3FAR bs3CpuInstr3_sha256msg2_XMM9_XMM8_icebp_c64; 7541 extern FNBS3FAR bs3CpuInstr3_sha256msg2_XMM9_FSxBX_icebp_c64; 7542 7543 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_sha1rnds4_XMM1_XMM2_000h_icebp); 7544 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_sha1rnds4_XMM1_FSxBX_000h_icebp); 7545 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_sha1rnds4_XMM1_XMM2_001h_icebp); 7546 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_sha1rnds4_XMM1_FSxBX_001h_icebp); 7547 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_sha1rnds4_XMM1_XMM2_002h_icebp); 7548 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_sha1rnds4_XMM1_FSxBX_002h_icebp); 7549 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_sha1rnds4_XMM1_XMM2_003h_icebp); 7550 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_sha1rnds4_XMM1_FSxBX_003h_icebp); 7551 extern FNBS3FAR bs3CpuInstr3_sha1rnds4_XMM9_XMM8_000h_icebp_c64; 7552 extern FNBS3FAR bs3CpuInstr3_sha1rnds4_XMM9_FSxBX_000h_icebp_c64; 7553 extern FNBS3FAR bs3CpuInstr3_sha1rnds4_XMM9_XMM8_001h_icebp_c64; 7554 extern FNBS3FAR bs3CpuInstr3_sha1rnds4_XMM9_FSxBX_001h_icebp_c64; 7555 extern FNBS3FAR bs3CpuInstr3_sha1rnds4_XMM9_XMM8_002h_icebp_c64; 7556 extern FNBS3FAR bs3CpuInstr3_sha1rnds4_XMM9_FSxBX_002h_icebp_c64; 7557 extern FNBS3FAR bs3CpuInstr3_sha1rnds4_XMM9_XMM8_003h_icebp_c64; 7558 extern FNBS3FAR bs3CpuInstr3_sha1rnds4_XMM9_FSxBX_003h_icebp_c64; 7559 7560 BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_sha1nexte_sha1msg1_sha1msg2_sha256msg1_sha256msg2_sha1rnds4(uint8_t bMode) 7561 { 7562 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesSha1Nexte[] = 7563 { 7564 { /*src2*/ RTUINT256_INIT_C( 0, 0, 0, 0), 7565 /*src1*/ RTUINT256_INIT_C( 0, 0, 0, 0), 7566 /* => */ RTUINT256_INIT_C( 0, 0, 0, 0) }, 7567 { /*src2*/ RTUINT256_INIT_C( 1, 2, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), 7568 /*src1*/ RTUINT256_INIT_C( 3, 4, 0x9192939495969798, 0x8182838485868788), 7569 /* => */ RTUINT256_INIT_C( 5, 6, 0xf63778b9d5d6d7d8, 0xc1c2c3c4c5c6c7c8) }, 7570 { /*src2*/ RTUINT256_INIT_C( 7, 8, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), 7571 /*src1*/ RTUINT256_INIT_C( 9, 10, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), 7572 /* => */ RTUINT256_INIT_C(11, 12, 0x962169fe564c9ba2, 0x9c5ce073930996bb) }, 7573 }; 7574 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesSha1Msg1[] = 7575 { 7576 { /*src2*/ RTUINT256_INIT_C( 0, 0, 0, 0), 7577 /*src1*/ RTUINT256_INIT_C( 0, 0, 0, 0), 7578 /* => */ RTUINT256_INIT_C( 0, 0, 0, 0) }, 7579 { /*src2*/ RTUINT256_INIT_C( 1, 2, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), 7580 /*src1*/ RTUINT256_INIT_C( 3, 4, 0x9192939495969798, 0x8182838485868788), 7581 /* => */ RTUINT256_INIT_C( 5, 6, 0x1010101010101010, 0x5050505050505050) }, 7582 { /*src2*/ RTUINT256_INIT_C( 7, 8, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), 7583 /*src1*/ RTUINT256_INIT_C( 9, 10, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), 7584 /* => */ RTUINT256_INIT_C(11, 12, 0xcbd324fb9c1dfb3e, 0xf7f2e20875c8025f) }, 7585 }; 7586 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesSha1Msg2[] = 7587 { 7588 { /*src2*/ RTUINT256_INIT_C( 0, 0, 0, 0), 7589 /*src1*/ RTUINT256_INIT_C( 0, 0, 0, 0), 7590 /* => */ RTUINT256_INIT_C( 0, 0, 0, 0) }, 7591 { /*src2*/ RTUINT256_INIT_C( 1, 2, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), 7592 /*src1*/ RTUINT256_INIT_C( 3, 4, 0x9192939495969798, 0x8182838485868788), 7593 /* => */ RTUINT256_INIT_C( 5, 6, 0x88888898a8a8a8b8, 0x888888981a1c1e20) }, 7594 { /*src2*/ RTUINT256_INIT_C( 7, 8, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), 7595 /*src1*/ RTUINT256_INIT_C( 9, 10, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), 7596 /* => */ RTUINT256_INIT_C(11, 12, 0xbc98e5f3478b0560, 0xa1b4b6373e38f81d) }, 7597 }; 7598 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesSha256Msg1[] = 7599 { 7600 { /*src2*/ RTUINT256_INIT_C( 0, 0, 0, 0), 7601 /*src1*/ RTUINT256_INIT_C( 0, 0, 0, 0), 7602 /* => */ RTUINT256_INIT_C( 0, 0, 0, 0) }, 7603 { /*src2*/ RTUINT256_INIT_C( 1, 2, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), 7604 /*src1*/ RTUINT256_INIT_C( 3, 4, 0x9192939495969798, 0x8182838485868788), 7605 /* => */ RTUINT256_INIT_C( 5, 6, 0xca53f79b358aeac9, 0x08025e3d3f58fc9f) }, 7606 { /*src2*/ RTUINT256_INIT_C( 7, 8, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), 7607 /*src1*/ RTUINT256_INIT_C( 9, 10, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), 7608 /* => */ RTUINT256_INIT_C(11, 12, 0x88eaae935be061bc, 0x0c10bf1bdf1a68d8) }, 7609 }; 7610 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesSha256Msg2[] = 7611 { 7612 { /*src2*/ RTUINT256_INIT_C( 0, 0, 0, 0), 7613 /*src1*/ RTUINT256_INIT_C( 0, 0, 0, 0), 7614 /* => */ RTUINT256_INIT_C( 0, 0, 0, 0) }, 7615 { /*src2*/ RTUINT256_INIT_C( 1, 2, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), 7616 /*src1*/ RTUINT256_INIT_C( 3, 4, 0x9192939495969798, 0x8182838485868788), 7617 /* => */ RTUINT256_INIT_C( 5, 6, 0xf7787989ecaccf3a, 0xb52709eb36a88d6c) }, 7618 { /*src2*/ RTUINT256_INIT_C( 7, 8, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), 7619 /*src1*/ RTUINT256_INIT_C( 9, 10, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), 7620 /* => */ RTUINT256_INIT_C(11, 12, 0x934e65a33794af02, 0xf5e0127f02358cc6) }, 7621 }; 7622 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesSha1Rnds4_00[] = 7623 { 7624 { /*src2*/ RTUINT256_INIT_C( 0, 0, 0, 0), 7625 /*src1*/ RTUINT256_INIT_C( 0, 0, 0, 0), 7626 /* => */ RTUINT256_INIT_C( 0, 0, 0xf4054bb3b4b8122e, 0x2ab46b3156a09e66) }, 7627 { /*src2*/ RTUINT256_INIT_C( 1, 2, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), 7628 /*src1*/ RTUINT256_INIT_C( 3, 4, 0x9192939495969798, 0x8182838485868788), 7629 /* => */ RTUINT256_INIT_C( 5, 6, 0x06d22bcd4846b4fd, 0x6f0a329ef80a90df) }, 7630 { /*src2*/ RTUINT256_INIT_C( 7, 8, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), 7631 /*src1*/ RTUINT256_INIT_C( 9, 10, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), 7632 /* => */ RTUINT256_INIT_C(11, 12, 0x9ba220d389ecd7df, 0xbabf326a8495ab9b) }, 7633 }; 7634 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesSha1Rnds4_01[] = 7635 { 7636 { /*src2*/ RTUINT256_INIT_C( 0, 0, 0, 0), 7637 /*src1*/ RTUINT256_INIT_C( 0, 0, 0, 0), 7638 /* => */ RTUINT256_INIT_C( 0, 0, 0x9475322b209fd10b, 0x9285d7f35bb67ae8) }, 7639 { /*src2*/ RTUINT256_INIT_C( 1, 2, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), 7640 /*src1*/ RTUINT256_INIT_C( 3, 4, 0x9192939495969798, 0x8182838485868788), 7641 /* => */ RTUINT256_INIT_C( 5, 6, 0x5b7c09a1f4668273, 0xe4796d15c1247166) }, 7642 { /*src2*/ RTUINT256_INIT_C( 7, 8, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), 7643 /*src1*/ RTUINT256_INIT_C( 9, 10, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), 7644 /* => */ RTUINT256_INIT_C(11, 12, 0xff4d24899413cadf, 0xda6c122200b99f56) }, 7645 }; 7646 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesSha1Rnds4_02[] = 7647 { 7648 { /*src2*/ RTUINT256_INIT_C( 0, 0, 0, 0), 7649 /*src1*/ RTUINT256_INIT_C( 0, 0, 0, 0), 7650 /* => */ RTUINT256_INIT_C( 0, 0, 0xe277565de186ca8a, 0x5ca4d61b23c6ef37) }, 7651 { /*src2*/ RTUINT256_INIT_C( 1, 2, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), 7652 /*src1*/ RTUINT256_INIT_C( 3, 4, 0x9192939495969798, 0x8182838485868788), 7653 /* => */ RTUINT256_INIT_C( 5, 6, 0x8b663a7f9465c97a, 0xe13b3e408631e2b2) }, 7654 { /*src2*/ RTUINT256_INIT_C( 7, 8, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), 7655 /*src1*/ RTUINT256_INIT_C( 9, 10, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), 7656 /* => */ RTUINT256_INIT_C(11, 12, 0x39eefe319badc2bb, 0xec8afdbd99baf875) }, 7657 }; 7658 static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesSha1Rnds4_03[] = 7659 { 7660 { /*src2*/ RTUINT256_INIT_C( 0, 0, 0, 0), 7661 /*src1*/ RTUINT256_INIT_C( 0, 0, 0, 0), 7662 /* => */ RTUINT256_INIT_C( 0, 0, 0xf328407d6c25198e, 0xc5aebf2bb298b075) }, 7663 { /*src2*/ RTUINT256_INIT_C( 1, 2, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), 7664 /*src1*/ RTUINT256_INIT_C( 3, 4, 0x9192939495969798, 0x8182838485868788), 7665 /* => */ RTUINT256_INIT_C( 5, 6, 0x1633e2343fedcafc, 0x17a2544e1806a6f4) }, 7666 { /*src2*/ RTUINT256_INIT_C( 7, 8, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb), 7667 /*src1*/ RTUINT256_INIT_C( 9, 10, 0x8800e95bbf9962c3, 0x43d3cda0238499fd), 7668 /* => */ RTUINT256_INIT_C(11, 12, 0xe4449478c8994eba, 0xcd94f95a579bd4e3) }, 7669 }; 7670 7671 static BS3CPUINSTR3_TEST1_T const s_aTests16[] = 7672 { 7673 { bs3CpuInstr3_sha1nexte_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SHA, 1, 1, 2, RT_ELEMENTS(s_aValuesSha1Nexte), s_aValuesSha1Nexte }, 7674 { bs3CpuInstr3_sha1nexte_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SHA, 1, 1, 255, RT_ELEMENTS(s_aValuesSha1Nexte), s_aValuesSha1Nexte }, 7675 7676 { bs3CpuInstr3_sha1msg1_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SHA, 1, 1, 2, RT_ELEMENTS(s_aValuesSha1Msg1), s_aValuesSha1Msg1 }, 7677 { bs3CpuInstr3_sha1msg1_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SHA, 1, 1, 255, RT_ELEMENTS(s_aValuesSha1Msg1), s_aValuesSha1Msg1 }, 7678 7679 { bs3CpuInstr3_sha1msg2_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SHA, 1, 1, 2, RT_ELEMENTS(s_aValuesSha1Msg2), s_aValuesSha1Msg2 }, 7680 { bs3CpuInstr3_sha1msg2_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SHA, 1, 1, 255, RT_ELEMENTS(s_aValuesSha1Msg2), s_aValuesSha1Msg2 }, 7681 7682 { bs3CpuInstr3_sha256msg1_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SHA, 1, 1, 2, RT_ELEMENTS(s_aValuesSha256Msg1), s_aValuesSha256Msg1 }, 7683 { bs3CpuInstr3_sha256msg1_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SHA, 1, 1, 255, RT_ELEMENTS(s_aValuesSha256Msg1), s_aValuesSha256Msg1 }, 7684 7685 { bs3CpuInstr3_sha256msg2_XMM1_XMM2_icebp_c16, 255, RM_REG, T_SHA, 1, 1, 2, RT_ELEMENTS(s_aValuesSha256Msg2), s_aValuesSha256Msg2 }, 7686 { bs3CpuInstr3_sha256msg2_XMM1_FSxBX_icebp_c16, 255, RM_MEM, T_SHA, 1, 1, 255, RT_ELEMENTS(s_aValuesSha256Msg2), s_aValuesSha256Msg2 }, 7687 7688 { bs3CpuInstr3_sha1rnds4_XMM1_XMM2_000h_icebp_c16, 255, RM_REG, T_SHA, 1, 1, 2, RT_ELEMENTS(s_aValuesSha1Rnds4_00), s_aValuesSha1Rnds4_00 }, 7689 { bs3CpuInstr3_sha1rnds4_XMM1_FSxBX_000h_icebp_c16, 255, RM_MEM, T_SHA, 1, 1, 255, RT_ELEMENTS(s_aValuesSha1Rnds4_00), s_aValuesSha1Rnds4_00 }, 7690 { bs3CpuInstr3_sha1rnds4_XMM1_XMM2_001h_icebp_c16, 255, RM_REG, T_SHA, 1, 1, 2, RT_ELEMENTS(s_aValuesSha1Rnds4_01), s_aValuesSha1Rnds4_01 }, 7691 { bs3CpuInstr3_sha1rnds4_XMM1_FSxBX_001h_icebp_c16, 255, RM_MEM, T_SHA, 1, 1, 255, RT_ELEMENTS(s_aValuesSha1Rnds4_01), s_aValuesSha1Rnds4_01 }, 7692 { bs3CpuInstr3_sha1rnds4_XMM1_XMM2_002h_icebp_c16, 255, RM_REG, T_SHA, 1, 1, 2, RT_ELEMENTS(s_aValuesSha1Rnds4_02), s_aValuesSha1Rnds4_02 }, 7693 { bs3CpuInstr3_sha1rnds4_XMM1_FSxBX_002h_icebp_c16, 255, RM_MEM, T_SHA, 1, 1, 255, RT_ELEMENTS(s_aValuesSha1Rnds4_02), s_aValuesSha1Rnds4_02 }, 7694 { bs3CpuInstr3_sha1rnds4_XMM1_XMM2_003h_icebp_c16, 255, RM_REG, T_SHA, 1, 1, 2, RT_ELEMENTS(s_aValuesSha1Rnds4_03), s_aValuesSha1Rnds4_03 }, 7695 { bs3CpuInstr3_sha1rnds4_XMM1_FSxBX_003h_icebp_c16, 255, RM_MEM, T_SHA, 1, 1, 255, RT_ELEMENTS(s_aValuesSha1Rnds4_03), s_aValuesSha1Rnds4_03 }, 7696 7697 }; 7698 static BS3CPUINSTR3_TEST1_T const s_aTests32[] = 7699 { 7700 { bs3CpuInstr3_sha1nexte_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SHA, 1, 1, 2, RT_ELEMENTS(s_aValuesSha1Nexte), s_aValuesSha1Nexte }, 7701 { bs3CpuInstr3_sha1nexte_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SHA, 1, 1, 255, RT_ELEMENTS(s_aValuesSha1Nexte), s_aValuesSha1Nexte }, 7702 7703 { bs3CpuInstr3_sha1msg1_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SHA, 1, 1, 2, RT_ELEMENTS(s_aValuesSha1Msg1), s_aValuesSha1Msg1 }, 7704 { bs3CpuInstr3_sha1msg1_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SHA, 1, 1, 255, RT_ELEMENTS(s_aValuesSha1Msg1), s_aValuesSha1Msg1 }, 7705 7706 { bs3CpuInstr3_sha1msg2_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SHA, 1, 1, 2, RT_ELEMENTS(s_aValuesSha1Msg2), s_aValuesSha1Msg2 }, 7707 { bs3CpuInstr3_sha1msg2_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SHA, 1, 1, 255, RT_ELEMENTS(s_aValuesSha1Msg2), s_aValuesSha1Msg2 }, 7708 7709 { bs3CpuInstr3_sha256msg1_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SHA, 1, 1, 2, RT_ELEMENTS(s_aValuesSha256Msg1), s_aValuesSha256Msg1 }, 7710 { bs3CpuInstr3_sha256msg1_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SHA, 1, 1, 255, RT_ELEMENTS(s_aValuesSha256Msg1), s_aValuesSha256Msg1 }, 7711 7712 { bs3CpuInstr3_sha256msg2_XMM1_XMM2_icebp_c32, 255, RM_REG, T_SHA, 1, 1, 2, RT_ELEMENTS(s_aValuesSha256Msg2), s_aValuesSha256Msg2 }, 7713 { bs3CpuInstr3_sha256msg2_XMM1_FSxBX_icebp_c32, 255, RM_MEM, T_SHA, 1, 1, 255, RT_ELEMENTS(s_aValuesSha256Msg2), s_aValuesSha256Msg2 }, 7714 7715 { bs3CpuInstr3_sha1rnds4_XMM1_XMM2_000h_icebp_c32, 255, RM_REG, T_SHA, 1, 1, 2, RT_ELEMENTS(s_aValuesSha1Rnds4_00), s_aValuesSha1Rnds4_00 }, 7716 { bs3CpuInstr3_sha1rnds4_XMM1_FSxBX_000h_icebp_c32, 255, RM_MEM, T_SHA, 1, 1, 255, RT_ELEMENTS(s_aValuesSha1Rnds4_00), s_aValuesSha1Rnds4_00 }, 7717 { bs3CpuInstr3_sha1rnds4_XMM1_XMM2_001h_icebp_c32, 255, RM_REG, T_SHA, 1, 1, 2, RT_ELEMENTS(s_aValuesSha1Rnds4_01), s_aValuesSha1Rnds4_01 }, 7718 { bs3CpuInstr3_sha1rnds4_XMM1_FSxBX_001h_icebp_c32, 255, RM_MEM, T_SHA, 1, 1, 255, RT_ELEMENTS(s_aValuesSha1Rnds4_01), s_aValuesSha1Rnds4_01 }, 7719 { bs3CpuInstr3_sha1rnds4_XMM1_XMM2_002h_icebp_c32, 255, RM_REG, T_SHA, 1, 1, 2, RT_ELEMENTS(s_aValuesSha1Rnds4_02), s_aValuesSha1Rnds4_02 }, 7720 { bs3CpuInstr3_sha1rnds4_XMM1_FSxBX_002h_icebp_c32, 255, RM_MEM, T_SHA, 1, 1, 255, RT_ELEMENTS(s_aValuesSha1Rnds4_02), s_aValuesSha1Rnds4_02 }, 7721 { bs3CpuInstr3_sha1rnds4_XMM1_XMM2_003h_icebp_c32, 255, RM_REG, T_SHA, 1, 1, 2, RT_ELEMENTS(s_aValuesSha1Rnds4_03), s_aValuesSha1Rnds4_03 }, 7722 { bs3CpuInstr3_sha1rnds4_XMM1_FSxBX_003h_icebp_c32, 255, RM_MEM, T_SHA, 1, 1, 255, RT_ELEMENTS(s_aValuesSha1Rnds4_03), s_aValuesSha1Rnds4_03 }, 7723 7724 }; 7725 static BS3CPUINSTR3_TEST1_T const s_aTests64[] = 7726 { 7727 { bs3CpuInstr3_sha1nexte_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SHA, 1, 1, 2, RT_ELEMENTS(s_aValuesSha1Nexte), s_aValuesSha1Nexte }, 7728 { bs3CpuInstr3_sha1nexte_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SHA, 1, 1, 255, RT_ELEMENTS(s_aValuesSha1Nexte), s_aValuesSha1Nexte }, 7729 { bs3CpuInstr3_sha1nexte_XMM9_XMM8_icebp_c64, 255, RM_REG, T_SHA, 9, 9, 8, RT_ELEMENTS(s_aValuesSha1Nexte), s_aValuesSha1Nexte }, 7730 { bs3CpuInstr3_sha1nexte_XMM9_FSxBX_icebp_c64, 255, RM_MEM, T_SHA, 9, 9, 255, RT_ELEMENTS(s_aValuesSha1Nexte), s_aValuesSha1Nexte }, 7731 7732 { bs3CpuInstr3_sha1msg1_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SHA, 1, 1, 2, RT_ELEMENTS(s_aValuesSha1Msg1), s_aValuesSha1Msg1 }, 7733 { bs3CpuInstr3_sha1msg1_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SHA, 1, 1, 255, RT_ELEMENTS(s_aValuesSha1Msg1), s_aValuesSha1Msg1 }, 7734 { bs3CpuInstr3_sha1msg1_XMM9_XMM8_icebp_c64, 255, RM_REG, T_SHA, 9, 9, 8, RT_ELEMENTS(s_aValuesSha1Msg1), s_aValuesSha1Msg1 }, 7735 { bs3CpuInstr3_sha1msg1_XMM9_FSxBX_icebp_c64, 255, RM_MEM, T_SHA, 9, 9, 255, RT_ELEMENTS(s_aValuesSha1Msg1), s_aValuesSha1Msg1 }, 7736 7737 { bs3CpuInstr3_sha1msg2_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SHA, 1, 1, 2, RT_ELEMENTS(s_aValuesSha1Msg2), s_aValuesSha1Msg2 }, 7738 { bs3CpuInstr3_sha1msg2_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SHA, 1, 1, 255, RT_ELEMENTS(s_aValuesSha1Msg2), s_aValuesSha1Msg2 }, 7739 { bs3CpuInstr3_sha1msg2_XMM9_XMM8_icebp_c64, 255, RM_REG, T_SHA, 9, 9, 8, RT_ELEMENTS(s_aValuesSha1Msg2), s_aValuesSha1Msg2 }, 7740 { bs3CpuInstr3_sha1msg2_XMM9_FSxBX_icebp_c64, 255, RM_MEM, T_SHA, 9, 9, 255, RT_ELEMENTS(s_aValuesSha1Msg2), s_aValuesSha1Msg2 }, 7741 7742 { bs3CpuInstr3_sha256msg1_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SHA, 1, 1, 2, RT_ELEMENTS(s_aValuesSha256Msg1), s_aValuesSha256Msg1 }, 7743 { bs3CpuInstr3_sha256msg1_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SHA, 1, 1, 255, RT_ELEMENTS(s_aValuesSha256Msg1), s_aValuesSha256Msg1 }, 7744 { bs3CpuInstr3_sha256msg1_XMM9_XMM8_icebp_c64, 255, RM_REG, T_SHA, 9, 9, 8, RT_ELEMENTS(s_aValuesSha256Msg1), s_aValuesSha256Msg1 }, 7745 { bs3CpuInstr3_sha256msg1_XMM9_FSxBX_icebp_c64, 255, RM_MEM, T_SHA, 9, 9, 255, RT_ELEMENTS(s_aValuesSha256Msg1), s_aValuesSha256Msg1 }, 7746 7747 { bs3CpuInstr3_sha256msg2_XMM1_XMM2_icebp_c64, 255, RM_REG, T_SHA, 1, 1, 2, RT_ELEMENTS(s_aValuesSha256Msg2), s_aValuesSha256Msg2 }, 7748 { bs3CpuInstr3_sha256msg2_XMM1_FSxBX_icebp_c64, 255, RM_MEM, T_SHA, 1, 1, 255, RT_ELEMENTS(s_aValuesSha256Msg2), s_aValuesSha256Msg2 }, 7749 { bs3CpuInstr3_sha256msg2_XMM9_XMM8_icebp_c64, 255, RM_REG, T_SHA, 9, 9, 8, RT_ELEMENTS(s_aValuesSha256Msg2), s_aValuesSha256Msg2 }, 7750 { bs3CpuInstr3_sha256msg2_XMM9_FSxBX_icebp_c64, 255, RM_MEM, T_SHA, 9, 9, 255, RT_ELEMENTS(s_aValuesSha256Msg2), s_aValuesSha256Msg2 }, 7751 7752 { bs3CpuInstr3_sha1rnds4_XMM1_XMM2_000h_icebp_c64, 255, RM_REG, T_SHA, 1, 1, 2, RT_ELEMENTS(s_aValuesSha1Rnds4_00), s_aValuesSha1Rnds4_00 }, 7753 { bs3CpuInstr3_sha1rnds4_XMM1_FSxBX_000h_icebp_c64, 255, RM_MEM, T_SHA, 1, 1, 255, RT_ELEMENTS(s_aValuesSha1Rnds4_00), s_aValuesSha1Rnds4_00 }, 7754 { bs3CpuInstr3_sha1rnds4_XMM1_XMM2_001h_icebp_c64, 255, RM_REG, T_SHA, 1, 1, 2, RT_ELEMENTS(s_aValuesSha1Rnds4_01), s_aValuesSha1Rnds4_01 }, 7755 { bs3CpuInstr3_sha1rnds4_XMM1_FSxBX_001h_icebp_c64, 255, RM_MEM, T_SHA, 1, 1, 255, RT_ELEMENTS(s_aValuesSha1Rnds4_01), s_aValuesSha1Rnds4_01 }, 7756 { bs3CpuInstr3_sha1rnds4_XMM1_XMM2_002h_icebp_c64, 255, RM_REG, T_SHA, 1, 1, 2, RT_ELEMENTS(s_aValuesSha1Rnds4_02), s_aValuesSha1Rnds4_02 }, 7757 { bs3CpuInstr3_sha1rnds4_XMM1_FSxBX_002h_icebp_c64, 255, RM_MEM, T_SHA, 1, 1, 255, RT_ELEMENTS(s_aValuesSha1Rnds4_02), s_aValuesSha1Rnds4_02 }, 7758 { bs3CpuInstr3_sha1rnds4_XMM1_XMM2_003h_icebp_c64, 255, RM_REG, T_SHA, 1, 1, 2, RT_ELEMENTS(s_aValuesSha1Rnds4_03), s_aValuesSha1Rnds4_03 }, 7759 { bs3CpuInstr3_sha1rnds4_XMM1_FSxBX_003h_icebp_c64, 255, RM_MEM, T_SHA, 1, 1, 255, RT_ELEMENTS(s_aValuesSha1Rnds4_03), s_aValuesSha1Rnds4_03 }, 7760 7500 7761 }; 7501 7762 static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); … … 11090 11351 * Test type #5 - three source MM/XMM/YMM operands. 11091 11352 * 11092 * Probably only used by the [P]BLEND instruction.11353 * Probably only used by the [P]BLEND and SHA256RNDS2 instructions. 11093 11354 */ 11094 11355 … … 11314 11575 Bs3ExtCtxSetYmm(pExtCtx, paTests[iTest].iRegDst, &paValues[iVal].uDstOut, cbOperand); 11315 11576 } 11577 #if defined(DEBUG_aeichner) /** @todo Necessary kludge on a i7-1068NG7. */ 11578 if ( pExtCtx->enmMethod == BS3EXTCTXMETHOD_XSAVE 11579 && pExtCtx->Ctx.x.Hdr.bmXState == 0x7 11580 && pExtCtxOut->Ctx.x.Hdr.bmXState == 0x3) 11581 pExtCtxOut->Ctx.x.Hdr.bmXState = 0x7; 11316 11582 Bs3TestCheckExtCtx(pExtCtxOut, pExtCtx, 0 /*fFlags*/, pszMode, idTestStep); 11583 #endif 11317 11584 11318 11585 if (TrapFrame.bXcpt != bXcptExpect) … … 11621 11888 { bs3CpuInstr3_vblendvpd_YMM8_YMM9_YMM10_YMM11_icebp_c64, 255, RM_REG, T_AVX_256, 8, 9, 10, 11, RT_ELEMENTS(s_aValues), s_aValues }, 11622 11889 { bs3CpuInstr3_vblendvpd_YMM8_YMM9_FSxBX_YMM11_icebp_c64, X86_XCPT_DB, RM_MEM, T_AVX_256, 8, 9, 255, 11, RT_ELEMENTS(s_aValues), s_aValues }, 11890 }; 11891 static BS3CPUINSTR3_TEST5_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST5_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); 11892 unsigned const iTest = BS3CPUINSTR3_TEST_MODES_INDEX(bMode); 11893 return bs3CpuInstr3_WorkerTestType5(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests, 11894 g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4)); 11895 } 11896 11897 11898 /* 11899 * SHA256RNDS2 11900 */ 11901 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_sha256rnds2_XMM1_XMM2_XMM0_icebp); 11902 BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_sha256rnds2_XMM1_FSxBX_XMM0_icebp); 11903 extern FNBS3FAR bs3CpuInstr3_sha256rnds2_XMM8_XMM9_XMM0_icebp_c64; 11904 extern FNBS3FAR bs3CpuInstr3_sha256rnds2_XMM8_FSxBX_XMM0_icebp_c64; 11905 11906 BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_sha256rnds2(uint8_t bMode) 11907 { 11908 static BS3CPUINSTR3_TEST5_VALUES_T const s_aValues[] = 11909 { 11910 { /*mask*/ RTUINT256_INIT_C(0, 0, 0, 0), 11911 /*src2*/ RTUINT256_INIT_C(0, 0, 0, 0), 11912 /*src1*/ RTUINT256_INIT_C(0, 0, 0, 0), 11913 /* => */ RTUINT256_INIT_C(1, 2, 0, 0) }, 11914 { /*mask*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), 11915 /*src2*/ RTUINT256_INIT_C(0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff, 0xffffffffffffffff), 11916 /*src1*/ RTUINT256_INIT_C( 0, 0, 0, 0), 11917 /* => */ RTUINT256_INIT_C( 5, 6, 0xf79feefafffffffb, 0xf7bffefdfffffffd) }, 11918 { /*mask*/ RTUINT256_INIT_C(0x0000008000000000, 0x0000091000007f00, 0, 0x8080808080808080), 11919 /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), 11920 /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), 11921 /* => */ RTUINT256_INIT_C( 9, 10, 0x6db0b4070638d9f7, 0x3c1e9824e85f3497) }, 11922 { /*mask*/ RTUINT256_INIT_C(0x8080808080808080, 0x8080808080808080, 0x8080808080808080, 0x8080808080808080), 11923 /*src2*/ RTUINT256_INIT_C(0xf1f2f3f4f5f6f7f8, 0xe1e2e3e4e5e6e7e8, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8), 11924 /*src1*/ RTUINT256_INIT_C(0xb1b2b3b4b5b6b7b8, 0xa1a2a3a4a5a6a7a8, 0x9192939495969798, 0x8182838485868788), 11925 /* => */ RTUINT256_INIT_C( 13, 14, 0x6db0b4070638d9f7, 0x3c1e9824e85f3497) }, 11926 { /*mask*/ RTUINT256_INIT_C(0x1234567890abcdef, 0xfedcba0987654321, 0xfedcba0987654321, 0x1234567890abcdef), 11927 /*src2*/ RTUINT256_INIT_C(0x5555666677778888, 0x1111222233334444, 0x1111222233334444, 0x5555666677778888), 11928 /*src1*/ RTUINT256_INIT_C(0xddddeeeeffff0000, 0x9999aaaabbbbcccc, 0x9999aaaabbbbcccc, 0xddddeeeeffff0000), 11929 /* => */ RTUINT256_INIT_C( 17, 18, 0xef25e0d150a28cfd, 0xbd9ab3ae2970ef62) }, 11930 }; 11931 11932 static BS3CPUINSTR3_TEST5_T const s_aTests16[] = 11933 { 11934 { bs3CpuInstr3_sha256rnds2_XMM1_XMM2_XMM0_icebp_c16, 255, RM_REG, T_SHA, 1, 1, 2, 0, RT_ELEMENTS(s_aValues), s_aValues }, 11935 { bs3CpuInstr3_sha256rnds2_XMM1_FSxBX_XMM0_icebp_c16, 255, RM_MEM, T_SHA, 1, 1, 255, 0, RT_ELEMENTS(s_aValues), s_aValues }, 11936 }; 11937 static BS3CPUINSTR3_TEST5_T const s_aTests32[] = 11938 { 11939 { bs3CpuInstr3_sha256rnds2_XMM1_XMM2_XMM0_icebp_c32, 255, RM_REG, T_SHA, 1, 1, 2, 0, RT_ELEMENTS(s_aValues), s_aValues }, 11940 { bs3CpuInstr3_sha256rnds2_XMM1_FSxBX_XMM0_icebp_c32, 255, RM_MEM, T_SHA, 1, 1, 255, 0, RT_ELEMENTS(s_aValues), s_aValues }, 11941 }; 11942 static BS3CPUINSTR3_TEST5_T const s_aTests64[] = 11943 { 11944 { bs3CpuInstr3_sha256rnds2_XMM1_XMM2_XMM0_icebp_c64, 255, RM_REG, T_SHA, 1, 1, 2, 0, RT_ELEMENTS(s_aValues), s_aValues }, 11945 { bs3CpuInstr3_sha256rnds2_XMM1_FSxBX_XMM0_icebp_c64, 255, RM_MEM, T_SHA, 1, 1, 255, 0, RT_ELEMENTS(s_aValues), s_aValues }, 11946 { bs3CpuInstr3_sha256rnds2_XMM8_XMM9_XMM0_icebp_c64, 255, RM_REG, T_SHA, 8, 8, 9, 0, RT_ELEMENTS(s_aValues), s_aValues }, 11947 { bs3CpuInstr3_sha256rnds2_XMM8_FSxBX_XMM0_icebp_c64, 255, RM_MEM, T_SHA, 8, 8, 255, 0, RT_ELEMENTS(s_aValues), s_aValues }, 11623 11948 }; 11624 11949 static BS3CPUINSTR3_TEST5_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST5_MODES_INIT(s_aTests16, s_aTests32, s_aTests64); … … 12148 12473 12149 12474 #endif 12475 #if defined(ALL_TESTS) 12476 { "sha1nexte/sha1msg1/sha1msg2/sha256msg1/sha256msg2/sha1rnds4", bs3CpuInstr3_v_sha1nexte_sha1msg1_sha1msg2_sha256msg1_sha256msg2_sha1rnds4, 0 }, 12477 { "sha256rnds2", bs3CpuInstr3_v_sha256rnds2, 0 } 12478 #endif 12150 12479 }; 12151 12480 Bs3TestInit("bs3-cpu-instr-3"); … … 12179 12508 g_afTypeSupports[T_AVX2_128] = RT_BOOL(fEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX2); 12180 12509 g_afTypeSupports[T_AVX2_256] = RT_BOOL(fEbx & X86_CPUID_STEXT_FEATURE_EBX_AVX2); 12510 g_afTypeSupports[T_SHA] = RT_BOOL(fEbx & X86_CPUID_STEXT_FEATURE_EBX_SHA); 12181 12511 } 12182 12512
Note:
See TracChangeset
for help on using the changeset viewer.
