Changeset 98888 in vbox

Timestamp:

Mar 9, 2023 11:19:18 AM (2 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

156222

Message:

ValidationKit/bootsectors: Implement instruction testcase for mpsadbw, bugref:9898

Location:

trunk/src/VBox/ValidationKit/bootsectors

Files:

• bs3-cpu-instr-3-template.mac (modified) (1 diff)
• bs3-cpu-instr-3.c32 (modified) (2 diffs)

trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3-template.mac

@@ -3040 +3040 @@
  %endif
 
+;
+; MPSADBW
+;
+EMIT_INSTR_PLUS_ICEBP   mpsadbw,  XMM1, XMM2,  0FFh
+EMIT_INSTR_PLUS_ICEBP   mpsadbw,  XMM1, FSxBX, 0FFh
+EMIT_INSTR_PLUS_ICEBP   mpsadbw,  XMM1, XMM2,  000h
+EMIT_INSTR_PLUS_ICEBP   mpsadbw,  XMM1, FSxBX, 000h
+
+ %if TMPL_BITS == 64
+EMIT_INSTR_PLUS_ICEBP   mpsadbw,  XMM8, XMM9,  0FFh
+EMIT_INSTR_PLUS_ICEBP   mpsadbw,  XMM8, FSxBX, 0FFh
+EMIT_INSTR_PLUS_ICEBP   mpsadbw,  XMM8, XMM9,  000h
+EMIT_INSTR_PLUS_ICEBP   mpsadbw,  XMM8, FSxBX, 000h
+ %endif
+
 
 %endif ; BS3_INSTANTIATING_CMN

trunk/src/VBox/ValidationKit/bootsectors/bs3-cpu-instr-3.c32

@@ -7759 +7759 @@
         {  bs3CpuInstr3_sha1rnds4_XMM1_FSxBX_003h_icebp_c64,      255, RM_MEM, T_SHA,       1, 1, 255, RT_ELEMENTS(s_aValuesSha1Rnds4_03), s_aValuesSha1Rnds4_03 },
 
+    };
+    static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
+    unsigned const                         iTest       = BS3CPUINSTR3_TEST_MODES_INDEX(bMode);
+    return bs3CpuInstr3_WorkerTestType1(bMode, s_aTests[iTest].paTests, s_aTests[iTest].cTests,
+                                        g_aXcptConfig4, RT_ELEMENTS(g_aXcptConfig4));
+}
+
+
+/*
+ * [V]MPSADBW - Compute Multiple Packed Sums of Absolute Differences.
+ */
+BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_mpsadbw_XMM1_XMM2_0FFh_icebp);
+BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_mpsadbw_XMM1_FSxBX_0FFh_icebp);
+BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_mpsadbw_XMM1_XMM2_000h_icebp);
+BS3_FNBS3FAR_PROTOTYPES_CMN(bs3CpuInstr3_mpsadbw_XMM1_FSxBX_000h_icebp);
+extern FNBS3FAR             bs3CpuInstr3_mpsadbw_XMM8_XMM9_0FFh_icebp_c64;
+extern FNBS3FAR             bs3CpuInstr3_mpsadbw_XMM8_FSxBX_0FFh_icebp_c64;
+extern FNBS3FAR             bs3CpuInstr3_mpsadbw_XMM8_XMM9_000h_icebp_c64;
+extern FNBS3FAR             bs3CpuInstr3_mpsadbw_XMM8_FSxBX_000h_icebp_c64;
+
+BS3_DECL_FAR(uint8_t) bs3CpuInstr3_v_mpsadbw(uint8_t bMode)
+{
+    static BS3CPUINSTR3_TEST1_VALUES_T const s_aValuesFF[] =
+    {
+        {   /*src2*/ RTUINT256_INIT_C(  0, 0, 0, 0),
+            /*src1*/ RTUINT256_INIT_C(  0, 0, 0, 0),
+            /* => */ RTUINT256_INIT_C(  0, 0, 0, 0) },
+        {   /*src2*/ RTUINT256_INIT_C(  0, 1, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
+            /*src1*/ RTUINT256_INIT_C(  2, 3, 0x9192939495969798, 0x8182838485868788),
+            /* => */ RTUINT256_INIT_C(  4, 5, 0x00fc00f800f400f0, 0x01040118012c0140) },
+        {   /*src2*/ RTUINT256_INIT_C(  6, 7, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
+            /*src1*/ RTUINT256_INIT_C(  8, 9, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
+            /* => */ RTUINT256_INIT_C(10, 11, 0x01bf010e01a700d1, 0x0155013300fa01c9) },
+    };
+    static BS3CPUINSTR3_TEST1_VALUES_T const s_aValues00[] =
+    {
+        {   /*src2*/ RTUINT256_INIT_C(0,   0, 0, 0),
+            /*src1*/ RTUINT256_INIT_C(0,   0, 0, 0),
+            /* => */ RTUINT256_INIT_C(0,   0, 0, 0) },
+        {   /*src2*/ RTUINT256_INIT_C(0,   1, 0xd1d2d3d4d5d6d7d8, 0xc1c2c3c4c5c6c7c8),
+            /*src1*/ RTUINT256_INIT_C(2,   3, 0x9192939495969798, 0x8182838485868788),
+            /* => */ RTUINT256_INIT_C(4,   5, 0x00d400e800fc0110, 0x010c010801040100) },
+        {   /*src2*/ RTUINT256_INIT_C(6,   7, 0xb4212fa8564c9ba2, 0x9c5ce073930996bb),
+            /*src1*/ RTUINT256_INIT_C(8,   9, 0x8800e95bbf9962c3, 0x43d3cda0238499fd),
+            /* => */ RTUINT256_INIT_C(10, 11, 0x0104015600b9016c, 0x01a6017b005b0130) },
+    };
+
+    static BS3CPUINSTR3_TEST1_T const s_aTests16[] =
+    {
+        {  bs3CpuInstr3_mpsadbw_XMM1_XMM2_0FFh_icebp_c16,          255,         RM_REG, T_SSE4_1,     1, 1,   2, RT_ELEMENTS(s_aValuesFF),  s_aValuesFF },
+        {  bs3CpuInstr3_mpsadbw_XMM1_FSxBX_0FFh_icebp_c16,         255,         RM_MEM, T_SSE4_1,     1, 1, 255, RT_ELEMENTS(s_aValuesFF),  s_aValuesFF },
+        {  bs3CpuInstr3_mpsadbw_XMM1_XMM2_000h_icebp_c16,          255,         RM_REG, T_SSE4_1,     1, 1,   2, RT_ELEMENTS(s_aValues00),  s_aValues00 },
+        {  bs3CpuInstr3_mpsadbw_XMM1_FSxBX_000h_icebp_c16,         255,         RM_MEM, T_SSE4_1,     1, 1, 255, RT_ELEMENTS(s_aValues00),  s_aValues00 },
+    };
+    static BS3CPUINSTR3_TEST1_T const s_aTests32[] =
+    {
+        {  bs3CpuInstr3_mpsadbw_XMM1_XMM2_0FFh_icebp_c32,          255,         RM_REG, T_SSE4_1,     1, 1,   2, RT_ELEMENTS(s_aValuesFF),  s_aValuesFF },
+        {  bs3CpuInstr3_mpsadbw_XMM1_FSxBX_0FFh_icebp_c32,         255,         RM_MEM, T_SSE4_1,     1, 1, 255, RT_ELEMENTS(s_aValuesFF),  s_aValuesFF },
+        {  bs3CpuInstr3_mpsadbw_XMM1_XMM2_000h_icebp_c32,          255,         RM_REG, T_SSE4_1,     1, 1,   2, RT_ELEMENTS(s_aValues00),  s_aValues00 },
+        {  bs3CpuInstr3_mpsadbw_XMM1_FSxBX_000h_icebp_c32,         255,         RM_MEM, T_SSE4_1,     1, 1, 255, RT_ELEMENTS(s_aValues00),  s_aValues00 },
+    };
+    static BS3CPUINSTR3_TEST1_T const s_aTests64[] =
+    {
+        {  bs3CpuInstr3_mpsadbw_XMM1_XMM2_0FFh_icebp_c64,          255,         RM_REG, T_SSE4_1,     1, 1,   2, RT_ELEMENTS(s_aValuesFF),  s_aValuesFF },
+        {  bs3CpuInstr3_mpsadbw_XMM1_FSxBX_0FFh_icebp_c64,         255,         RM_MEM, T_SSE4_1,     1, 1, 255, RT_ELEMENTS(s_aValuesFF),  s_aValuesFF },
+        {  bs3CpuInstr3_mpsadbw_XMM8_XMM9_0FFh_icebp_c64,          255,         RM_REG, T_SSE4_1,     8, 8,   9, RT_ELEMENTS(s_aValuesFF),  s_aValuesFF },
+        {  bs3CpuInstr3_mpsadbw_XMM8_FSxBX_0FFh_icebp_c64,         255,         RM_MEM, T_SSE4_1,     8, 8, 255, RT_ELEMENTS(s_aValuesFF),  s_aValuesFF },
+
+        {  bs3CpuInstr3_mpsadbw_XMM1_XMM2_000h_icebp_c64,          255,         RM_REG, T_SSE4_1,     1, 1,   2, RT_ELEMENTS(s_aValues00),  s_aValues00 },
+        {  bs3CpuInstr3_mpsadbw_XMM1_FSxBX_000h_icebp_c64,         255,         RM_MEM, T_SSE4_1,     1, 1, 255, RT_ELEMENTS(s_aValues00),  s_aValues00 },
+        {  bs3CpuInstr3_mpsadbw_XMM8_XMM9_000h_icebp_c64,          255,         RM_REG, T_SSE4_1,     8, 8,   9, RT_ELEMENTS(s_aValues00),  s_aValues00 },
+        {  bs3CpuInstr3_mpsadbw_XMM8_FSxBX_000h_icebp_c64,         255,         RM_MEM, T_SSE4_1,     8, 8, 255, RT_ELEMENTS(s_aValues00),  s_aValues00 },
     };
     static BS3CPUINSTR3_TEST1_MODE_T const s_aTests[3] = BS3CPUINSTR3_TEST1_MODES_INIT(s_aTests16, s_aTests32, s_aTests64);
@@ -12475 +12547 @@
 #if defined(ALL_TESTS)
         { "sha1nexte/sha1msg1/sha1msg2/sha256msg1/sha256msg2/sha1rnds4",  bs3CpuInstr3_v_sha1nexte_sha1msg1_sha1msg2_sha256msg1_sha256msg2_sha1rnds4, 0 },
-        { "sha256rnds2",                                                  bs3CpuInstr3_v_sha256rnds2, 0 }
+        { "sha256rnds2",                                                  bs3CpuInstr3_v_sha256rnds2, 0 },
+#endif
+#if defined (ALL_TESTS)
+        { "mpsadbw",                                        bs3CpuInstr3_v_mpsadbw, 0 }
+
 #endif
     };