VirtualBox

Changeset 9890 in vbox


Ignore:
Timestamp:
Jun 24, 2008 8:26:36 AM (17 years ago)
Author:
vboxsync
Message:

amd64 paging updates

Location:
trunk/src/VBox/VMM
Files:
7 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/VMM/PGM.cpp

    r9669 r9890  
    12641264    AssertRelease((uintptr_t)pVM->pgm.s.apHCPaePDs[2] + PAGE_SIZE == (uintptr_t)pVM->pgm.s.apHCPaePDs[3]);
    12651265    pVM->pgm.s.pHCPaePDPT    = (PX86PDPT)MMR3PageAllocLow(pVM);
    1266     pVM->pgm.s.pHCPaePML4    = (PX86PML4)MMR3PageAllocLow(pVM);
    12671266    if (    !pVM->pgm.s.pHC32BitPD
    12681267        ||  !pVM->pgm.s.apHCPaePDs[0]
    … …  
    12701269        ||  !pVM->pgm.s.apHCPaePDs[2]
    12711270        ||  !pVM->pgm.s.apHCPaePDs[3]
    1272         ||  !pVM->pgm.s.pHCPaePDPT
    1273         ||  !pVM->pgm.s.pHCPaePML4)
     1271        ||  !pVM->pgm.s.pHCPaePDPT)
    12741272    {
    12751273        AssertMsgFailed(("Failed to allocate pages for the intermediate context!\n"));
    … …  
    12851283    pVM->pgm.s.aHCPhysPaePDs[3] = MMPage2Phys(pVM, pVM->pgm.s.apHCPaePDs[3]);
    12861284    pVM->pgm.s.HCPhysPaePDPT    = MMPage2Phys(pVM, pVM->pgm.s.pHCPaePDPT);
    1287     pVM->pgm.s.HCPhysPaePML4    = MMPage2Phys(pVM, pVM->pgm.s.pHCPaePML4);
    12881285
    12891286    /*
    … …  
    12991296        /* The flags will be corrected when entering and leaving long mode. */
    13001297    }
    1301 
    1302     ASMMemZero32(pVM->pgm.s.pHCPaePML4, PAGE_SIZE);
    13031298
    13041299    CPUMSetHyperCR3(pVM, (uint32_t)pVM->pgm.s.HCPhys32BitPD);

  • trunk/src/VBox/VMM/PGMInternal.h

    r9888 r9890  
    12891289/** Page Directory Pointer Table (PAE root, not currently used). */
    12901290#define PGMPOOL_IDX_PDPT        7
    1291 /** Page Map Level-4 (64-bit root). */
    1292 #define PGMPOOL_IDX_PML4        8
    1293 /** AMD64 cr3 level. */
    1294 #define PGMPOOL_IDX_AMD64_CR3   9
     1291/** AMD64 CR3 level index.*/
     1292#define PGMPOOL_IDX_AMD64_CR3   8
    12951293/** The first normal index. */
    1296 #define PGMPOOL_IDX_FIRST       10
     1294#define PGMPOOL_IDX_FIRST       9
    12971295/** The last valid index. (inclusive, 14 bits) */
    12981296#define PGMPOOL_IDX_LAST        0x3fff
    … …  
    13741372    PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD,
    13751373
     1374    /** Shw: 64-bit PML4;   Gst: 64-bit PML4. */
     1375    PGMPOOLKIND_64BIT_PML4_FOR_64BIT_PML4,
     1376
    13761377    /** Shw: Root 32-bit page directory. */
    13771378    PGMPOOLKIND_ROOT_32BIT_PD,
    … …  
    13801381    /** Shw: Root PAE page directory pointer table (legacy, 4 entries). */
    13811382    PGMPOOLKIND_ROOT_PDPT,
    1382     /** Shw: Root page map level-4 table. */
    1383     PGMPOOLKIND_ROOT_PML4,
    13841383
    13851384    /** The last valid entry. */
    1386     PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_PML4
     1385    PGMPOOLKIND_LAST = PGMPOOLKIND_ROOT_PDPT
    13871386} PGMPOOLKIND;
    13881387

  • trunk/src/VBox/VMM/PGMPool.cpp

    r9881 r9890  
    267267    pPool->aPages[PGMPOOL_IDX_PDPT].idx       = PGMPOOL_IDX_PDPT;
    268268
    269     /* The Shadow Page Map Level-4. */
    270     pPool->aPages[PGMPOOL_IDX_PML4].Core.Key  = NIL_RTHCPHYS;
    271     pPool->aPages[PGMPOOL_IDX_PML4].GCPhys    = NIL_RTGCPHYS;
    272     pPool->aPages[PGMPOOL_IDX_PML4].pvPageHC  = pVM->pgm.s.pHCPaePML4;
    273     pPool->aPages[PGMPOOL_IDX_PML4].enmKind   = PGMPOOLKIND_ROOT_PML4;
    274     pPool->aPages[PGMPOOL_IDX_PML4].idx       = PGMPOOL_IDX_PML4;
     269    /* The Shadow AMD64 CR3. */
     270    pPool->aPages[PGMPOOL_IDX_AMD64_CR3].Core.Key  = NIL_RTHCPHYS;
     271    pPool->aPages[PGMPOOL_IDX_AMD64_CR3].GCPhys    = NIL_RTGCPHYS;
     272    pPool->aPages[PGMPOOL_IDX_AMD64_CR3].pvPageHC  = 0;
     273    pPool->aPages[PGMPOOL_IDX_AMD64_CR3].enmKind   = PGMPOOLKIND_64BIT_PML4_FOR_64BIT_PML4;
     274    pPool->aPages[PGMPOOL_IDX_AMD64_CR3].idx       = PGMPOOL_IDX_AMD64_CR3;
    275275
    276276    /*

  • trunk/src/VBox/VMM/VMMAll/PGMAll.cpp

    r9888 r9890  
    825825
    826826    Assert(!HWACCMIsNestedPagingActive(pVM));
    827     Assert(pVM->pgm.s.pShwAmd64CR3);
    828 
     827    AssertReturn(pVM->pgm.s.pHCPaePML4, VERR_INTERNAL_ERROR);
     828
     829    Assert(pVM->pgm.s.pHCPaePML4);
    829830    /* Allocate page directory pointer table if not present. */
    830831    pPml4e = &pPGM->pHCPaePML4->a[iPml4e];
    … …  
    902903
    903904    Assert(!HWACCMIsNestedPagingActive(pVM));
     905    AssertReturn(pVM->pgm.s.pHCPaePML4, VERR_INTERNAL_ERROR);
    904906
    905907    pPml4e = &pPGM->pHCPaePML4->a[iPml4e];

  • trunk/src/VBox/VMM/VMMAll/PGMAllBth.h

    r9881 r9890  
    880880# else /* AMD64 */
    881881    /* PML4 */
     882    AssertReturn(pVM->pgm.s.pHCPaePML4, VERR_INTERNAL_ERROR);
     883
    882884    const unsigned  iPml4e    = (GCPtrPage >> X86_PML4_SHIFT) & X86_PML4_MASK;
    883885    const unsigned  iPdPte    = (GCPtrPage >> X86_PDPT_SHIFT) & X86_PDPT_MASK_AMD64;
    … …  
    986988            LogFlow(("InvalidatePage: Out-of-sync PML4E at %VGv Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
    987989                     GCPtrPage, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
    988             pgmPoolFreeByPage(pPool, pShwPdpt, PGMPOOL_IDX_PML4, iPml4e);
     990            pgmPoolFreeByPage(pPool, pShwPdpt, pVM->pgm.s.pShwAmd64CR3->idx, iPml4e);
    989991            pPml4eDst->u = 0;
    990992            STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDOutOfSync));
    … …  
    9981000            LogFlow(("InvalidatePage: Out-of-sync PML4E (A) at %VGv Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
    9991001                     GCPtrPage, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
    1000             pgmPoolFreeByPage(pPool, pShwPdpt, PGMPOOL_IDX_PML4, iPml4e);
     1002            pgmPoolFreeByPage(pPool, pShwPdpt, pVM->pgm.s.pShwAmd64CR3->idx, iPml4e);
    10011003            pPml4eDst->u = 0;
    10021004            STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDNAs));
    … …  
    10081010        LogFlow(("InvalidatePage: Out-of-sync PML4E (P) at %VGv Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
    10091011                    GCPtrPage, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
    1010         pgmPoolFreeByPage(pPool, pShwPdpt, PGMPOOL_IDX_PML4, iPml4e);
     1012        pgmPoolFreeByPage(pPool, pShwPdpt, pVM->pgm.s.pShwAmd64CR3->idx, iPml4e);
    10111013        pPml4eDst->u = 0;
    10121014        STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDNPs));
    … …  
    10211023        LogFlow(("InvalidatePage: Out-of-sync PML4E (GCPhys) at %VGv %VGp vs %VGp Pml4eSrc=%RX64 Pml4eDst=%RX64\n",
    10221024                    GCPtrPage, pShwPdpt->GCPhys, GCPhysPdpt, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
    1023         pgmPoolFreeByPage(pPool, pShwPdpt, PGMPOOL_IDX_PML4, iPml4e);
     1025        pgmPoolFreeByPage(pPool, pShwPdpt, pVM->pgm.s.pShwAmd64CR3->idx, iPml4e);
    10241026        pPml4eDst->u = 0;
    10251027        STAM_COUNTER_INC(&pVM->pgm.s.CTXMID(Stat,InvalidatePagePDNPs));
    … …  
    30993101            LogFlow(("SyncCR3: Out-of-sync PML4E (GCPhys) GCPtr=%VGv %VGp vs %VGp PdpeSrc=%RX64 PdpeDst=%RX64\n",
    31003102                     (uint64_t)iPml4e << X86_PML4_SHIFT, pShwPdpt->GCPhys, GCPhysPdptSrc, (uint64_t)pPml4eSrc->u, (uint64_t)pPml4eDst->u));
    3101             pgmPoolFreeByPage(pPool, pShwPdpt, PGMPOOL_IDX_PML4, iPml4e);
     3103            pgmPoolFreeByPage(pPool, pShwPdpt, pVM->pgm.s.pShwAmd64CR3->idx, iPml4e);
    31023104            pPml4eDst->u = 0;
    31033105            continue;

  • trunk/src/VBox/VMM/VMMAll/PGMAllGst.h

    r9888 r9890  
    475475
    476476            Assert(!(GCPhysCR3 >> (PAGE_SHIFT + 32)));
    477             rc = pgmPoolAlloc(pVM, GCPhysCR3, PGMPOOLKIND_ROOT_PML4, PGMPOOL_IDX_AMD64_CR3, GCPhysCR3 >> PAGE_SHIFT, &pVM->pgm.s.pShwAmd64CR3);
     477            rc = pgmPoolAlloc(pVM, GCPhysCR3, PGMPOOLKIND_64BIT_PML4_FOR_64BIT_PML4, PGMPOOL_IDX_AMD64_CR3, GCPhysCR3 >> PAGE_SHIFT, &pVM->pgm.s.pShwAmd64CR3);
    478478            if (rc == VERR_PGM_POOL_FLUSHED)
    479479            {
    … …  
    481481                return VINF_PGM_SYNC_CR3;
    482482            }
     483            pVM->pgm.s.pHCPaePML4 = (PX86PML4)PGMPOOL_PAGE_2_PTR(pPool->CTXSUFF(pVM), pVM->pgm.s.pShwAmd64CR3);
    483484# endif
    484485        }
    … …  
    524525#elif PGM_GST_TYPE == PGM_TYPE_AMD64
    525526    pVM->pgm.s.pGstPaePML4HC = 0;
     527    pVM->pgm.s.pHCPaePML4    = 0;
    526528    if (pVM->pgm.s.pShwAmd64CR3)
    527529    {

  • trunk/src/VBox/VMM/VMMAll/PGMAllPool.cpp

    r9881 r9890  
    262262            PX86PDPAE   pPDPae;
    263263            PX86PDPT    pPDPT;
     264            PX86PML4    pPML4;
    264265        } uShw;
    265266        uShw.pv = PGMPOOL_PAGE_2_PTR(pPool->CTXSUFF(pVM), pPage);
    … …  
    507508            }
    508509
     510            case PGMPOOLKIND_64BIT_PML4_FOR_64BIT_PML4:
     511            {
     512                /* Hopefully this doesn't happen very often:
     513                 * - messing with the bits of pd pointers without changing the physical address
     514                 */
     515                if (!VM_FF_ISSET(pPool->CTXSUFF(pVM), VM_FF_PGM_SYNC_CR3))
     516                {
     517                    const unsigned iShw = off / sizeof(X86PDPE);
     518                    if (uShw.pPML4->a[iShw].n.u1Present)
     519                    {
     520                        LogFlow(("pgmPoolMonitorChainChanging: pml4 iShw=%#x: %RX64 -> freeing it!\n", iShw, uShw.pPML4->a[iShw].u));
     521                        pgmPoolFree(pPool->CTXSUFF(pVM), uShw.pPML4->a[iShw].u & X86_PML4E_PG_MASK, pPage->idx, iShw);
     522                        uShw.pPML4->a[iShw].u = 0;
     523                    }
     524                    /* paranoia / a bit assumptive. */
     525                    if (   pCpu
     526                        && (off & 7)
     527                        && (off & 7) + pgmPoolDisasWriteSize(pCpu) > sizeof(X86PDPE))
     528                    {
     529                        const unsigned iShw2 = (off + pgmPoolDisasWriteSize(pCpu) - 1) / sizeof(X86PML4E);
     530                        if (uShw.pPML4->a[iShw2].n.u1Present)
     531                        {
     532                            LogFlow(("pgmPoolMonitorChainChanging: pml4 iShw2=%#x: %RX64 -> freeing it!\n", iShw2, uShw.pPML4->a[iShw2].u));
     533                            pgmPoolFree(pPool->CTXSUFF(pVM), uShw.pPML4->a[iShw2].u & X86_PML4E_PG_MASK, pPage->idx, iShw2);
     534                            uShw.pPML4->a[iShw2].u = 0;
     535                        }
     536                    }
     537                }
     538                break;
     539            }
     540
    509541            default:
    510542                AssertFatalMsgFailed(("enmKind=%d\n", pPage->enmKind));
    … …  
    10071039                case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
    10081040                case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
     1041                case PGMPOOLKIND_64BIT_PML4_FOR_64BIT_PML4:
    10091042                case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
    10101043                case PGMPOOLKIND_32BIT_PT_FOR_PHYS:
    … …  
    10221055        case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
    10231056        case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
     1057        case PGMPOOLKIND_64BIT_PML4_FOR_64BIT_PML4:
    10241058        case PGMPOOLKIND_PAE_PT_FOR_PAE_2MB:
    10251059            switch (enmKind2)
    … …  
    10431077        case PGMPOOLKIND_ROOT_PAE_PD:
    10441078        case PGMPOOLKIND_ROOT_PDPT:
    1045         case PGMPOOLKIND_ROOT_PML4:
    10461079            return false;
    10471080
    … …  
    12341267                case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
    12351268                case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
     1269                case PGMPOOLKIND_64BIT_PML4_FOR_64BIT_PML4:
    12361270                case PGMPOOLKIND_ROOT_32BIT_PD:
    12371271                case PGMPOOLKIND_ROOT_PAE_PD:
    12381272                case PGMPOOLKIND_ROOT_PDPT:
    1239                 case PGMPOOLKIND_ROOT_PML4:
    12401273                {
    12411274                    /* find the head */
    … …  
    12911324        case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
    12921325        case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
     1326        case PGMPOOLKIND_64BIT_PML4_FOR_64BIT_PML4:
    12931327        case PGMPOOLKIND_ROOT_PDPT:
    12941328            break;
    … …  
    13041338        case PGMPOOLKIND_ROOT_32BIT_PD:
    13051339        case PGMPOOLKIND_ROOT_PAE_PD:
    1306         case PGMPOOLKIND_ROOT_PML4:
    13071340#ifdef PGMPOOL_WITH_MIXED_PT_CR3
    13081341            break;
    … …  
    13731406        case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
    13741407        case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
     1408        case PGMPOOLKIND_64BIT_PML4_FOR_64BIT_PML4:
    13751409        case PGMPOOLKIND_ROOT_PDPT:
    13761410            break;
    … …  
    13861420        case PGMPOOLKIND_ROOT_32BIT_PD:
    13871421        case PGMPOOLKIND_ROOT_PAE_PD:
    1388         case PGMPOOLKIND_ROOT_PML4:
    13891422#ifdef PGMPOOL_WITH_MIXED_PT_CR3
    13901423            break;
    … …  
    20672100        case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
    20682101        case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
     2102        case PGMPOOLKIND_64BIT_PML4_FOR_64BIT_PML4:
    20692103        case PGMPOOLKIND_ROOT_PAE_PD:
    20702104        case PGMPOOLKIND_ROOT_PDPT:
    2071         case PGMPOOLKIND_ROOT_PML4:
    20722105            return 8;
    20732106
    … …  
    21042137        case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
    21052138        case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
     2139        case PGMPOOLKIND_64BIT_PML4_FOR_64BIT_PML4:
    21062140        case PGMPOOLKIND_ROOT_PAE_PD:
    21072141        case PGMPOOLKIND_ROOT_PDPT:
    2108         case PGMPOOLKIND_ROOT_PML4:
    21092142            return 8;
    21102143
    … …  
    24242457            Assert(pUser->iUserTable < X86_PG_PAE_ENTRIES);
    24252458            break;
    2426         case PGMPOOLKIND_ROOT_PML4:
     2459        case PGMPOOLKIND_64BIT_PML4_FOR_64BIT_PML4:
    24272460            Assert(!(u.pau64[pUser->iUserTable] & PGM_PLXFLAGS_PERMANENT));
    2428             Assert(pUser->iUserTable < X86_PG_PAE_ENTRIES);
     2461            /* GCPhys >> PAGE_SHIFT is the index here */
    24292462            break;
    24302463        default:
    … …  
    24512484        case PGMPOOLKIND_64BIT_PD_FOR_64BIT_PD:
    24522485        case PGMPOOLKIND_64BIT_PDPT_FOR_64BIT_PDPT:
    2453         case PGMPOOLKIND_ROOT_PML4:
     2486        case PGMPOOLKIND_64BIT_PML4_FOR_64BIT_PML4:
    24542487            u.pau64[pUser->iUserTable] = 0;
    24552488            break;
    … …  
    31353168                break;
    31363169
    3137             case PGMPOOLKIND_ROOT_PML4:
    3138                 for (unsigned iPage = 0; iPage < X86_PG_PAE_ENTRIES; iPage++)
    3139                     if ((u.pau64[iPage] & (PGM_PLXFLAGS_PERMANENT | X86_PML4E_P)) == X86_PML4E_P)
    3140                         u.pau64[iPage] = 0;
    3141                 break;
    3142 
    31433170            case PGMPOOLKIND_ROOT_PDPT:
    31443171                /* Not root of shadowed pages currently, ignore it. */
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