VirtualBox

Changeset 98972 in vbox


Ignore:
Timestamp:
Mar 15, 2023 9:39:29 AM (2 years ago)
Author:
vboxsync
svn:sync-xref-src-repo-rev:
156321
Message:

VMM: More ARMv8 x86/amd64 separation work, get past DBGF, bugref:10385

Location:
trunk
Files:
8 edited

Legend:

Unmodified
Added
Removed

  • trunk/include/VBox/types.h

    r98103 r98972  
    11901190    /** The usual invalid zero entry. */
    11911191    CPUMMODE_INVALID = 0,
    1192     /** Real mode. */
     1192    /** Real mode - x86/amd64. */
    11931193    CPUMMODE_REAL,
    1194     /** Protected mode (32-bit). */
     1194    /** Protected mode (32-bit) - x86/amd64. */
    11951195    CPUMMODE_PROTECTED,
    1196     /** Long mode (64-bit). */
    1197     CPUMMODE_LONG
     1196    /** Long mode (64-bit) - x86/amd64. */
     1197    CPUMMODE_LONG,
     1198    /** ARMv8 - AARCH64 mode. */
     1199    CPUMMODE_ARMV8_AARCH64,
     1200    /** ARMv8 - AARCH32 mode. */
     1201    CPUMMODE_ARMV8_AARCH32,
     1202    /** hack forcing the size of the enum to 32-bits. */
     1203    CPUMMODE_32BIT_HACK = 0x7fffffff
    11981204} CPUMMODE;
    11991205

  • trunk/include/VBox/vmm/cpum-x86-amd64.h

    r98970 r98972  
    29892989/** @} */
    29902990
    2991 VMMDECL(PCPUMCTX)       CPUMQueryGuestCtxPtr(PVMCPU pVCpu);
    29922991#ifdef VBOX_INCLUDED_vmm_cpumctx_h
    29932992VMM_INT_DECL(PCPUMCTXMSRS) CPUMQueryGuestCtxMsrsPtr(PVMCPU pVCpu);
    … …  
    30403039VMMDECL(bool)           CPUMIsHyperDebugStateActive(PVMCPU pVCpu);
    30413040VMMDECL(uint32_t)       CPUMGetGuestCPL(PVMCPU pVCpu);
    3042 VMMDECL(CPUMMODE)       CPUMGetGuestMode(PVMCPU pVCpu);
    30433041VMMDECL(uint32_t)       CPUMGetGuestCodeBits(PVMCPU pVCpu);
    30443042VMMDECL(DISCPUMODE)     CPUMGetGuestDisMode(PVMCPU pVCpu);

  • trunk/include/VBox/vmm/cpum.h

    r98970 r98972  
    6161#ifndef VBOX_FOR_DTRACE_LIB
    6262
     63VMMDECL(PCPUMCTX)       CPUMQueryGuestCtxPtr(PVMCPU pVCpu);
     64VMMDECL(CPUMMODE)       CPUMGetGuestMode(PVMCPU pVCpu);
     65
    6366/** @name Guest Register Getters.
    6467 * @{ */

  • trunk/include/VBox/vmm/cpumctx-armv8.h

    r98970 r98972  
    186186/** The SP register values are kept externally. */
    187187#define CPUMCTX_EXTRN_SP                        UINT64_C(0x0000000000000020)
     188/** The PSTATE value is kept externally. */
     189#define CPUMCTX_EXTRN_PSTATE                    UINT64_C(0x0000000000000040)
     190/** @todo RSVD. */
     191#define CPUMCTX_EXTRN_RSVD                      UINT64_C(0x0000000000000080)
    188192
    189193/** The X0 register value is kept externally. */
    190 #define CPUMCTX_EXTRN_X0                        UINT64_C(0x0000000000000040)
    191 /** The X0 register value is kept externally. */
    192 #define CPUMCTX_EXTRN_X1                        UINT64_C(0x0000000000000080)
    193 /** The X0 register value is kept externally. */
    194 #define CPUMCTX_EXTRN_X2                        UINT64_C(0x0000000000000100)
    195 /** The X0 register value is kept externally. */
    196 #define CPUMCTX_EXTRN_X3                        UINT64_C(0x0000000000000200)
     194#define CPUMCTX_EXTRN_X0                        UINT64_C(0x0000000000000100)
     195/** The X1 register value is kept externally. */
     196#define CPUMCTX_EXTRN_X1                        UINT64_C(0x0000000000000200)
     197/** The X2 register value is kept externally. */
     198#define CPUMCTX_EXTRN_X2                        UINT64_C(0x0000000000000400)
     199/** The X3 register value is kept externally. */
     200#define CPUMCTX_EXTRN_X3                        UINT64_C(0x0000000000000800)
    197201/** The LR (X30) register value is kept externally. */
    198 #define CPUMCTX_EXTRN_LR                        UINT64_C(0x0000000000000400)
     202#define CPUMCTX_EXTRN_LR                        UINT64_C(0x0000000000001000)
    199203/** The FP (X29) register value is kept externally. */
    200 #define CPUMCTX_EXTRN_FP                        UINT64_C(0x0000000000000800)
     204#define CPUMCTX_EXTRN_FP                        UINT64_C(0x0000000000002000)
    201205/** The X4 through X28 register values are kept externally. */
    202 #define CPUMCTX_EXTRN_X4_X28                    UINT64_C(0x0000000000001000)
     206#define CPUMCTX_EXTRN_X4_X28                    UINT64_C(0x0000000000004000)
    203207/** General purpose registers mask. */
    204 #define CPUMCTX_EXTRN_GPRS_MASK                 UINT64_C(0x0000000000001fc0)
     208#define CPUMCTX_EXTRN_GPRS_MASK                 UINT64_C(0x0000000000007f00)
    205209
    206210/** The NEON SIMD & FP registers V0 through V31 are kept externally. */

  • trunk/src/VBox/VMM/VMMR3/DBGFCpu.cpp

    r98103 r98972  
    5555    Assert(idCpu == VMMGetCpuId(pVM));
    5656    PVMCPU pVCpu = VMMGetCpuById(pVM, idCpu);
     57#if defined(VBOX_VMM_TARGET_ARMV8)
     58    CPUM_IMPORT_EXTRN_RET(pVCpu, CPUMCTX_EXTRN_PSTATE);
     59#else
    5760    CPUM_IMPORT_EXTRN_RET(pVCpu, CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_EFER);
     61#endif
    5862    *penmMode = CPUMGetGuestMode(pVCpu);
    5963    return VINF_SUCCESS;
    … …  
    9498    Assert(idCpu == VMMGetCpuId(pVM));
    9599    PVMCPU pVCpu = VMMGetCpuById(pVM, idCpu);
     100#if defined(VBOX_VMM_TARGET_ARMV8)
     101    CPUM_IMPORT_EXTRN_RET(pVCpu, CPUMCTX_EXTRN_PSTATE);
     102#else
    96103    CPUM_IMPORT_EXTRN_RET(pVCpu, CPUMCTX_EXTRN_CS | CPUMCTX_EXTRN_EFER);
     104#endif
    97105    *pfIn64BitCode = CPUMIsGuestIn64BitCode(pVCpu);
    98106    return VINF_SUCCESS;
    … …  
    121129
    122130
     131#if !defined(VBOX_VMM_TARGET_ARMV8)
    123132/**
    124133 * Wrapper around CPUMIsGuestInV86Code.
    … …  
    137146    return VINF_SUCCESS;
    138147}
     148#endif
    139149
    140150
    … …  
    152162    AssertReturn(idCpu < pUVM->pVM->cCpus, false);
    153163
     164#if defined(VBOX_VMM_TARGET_ARMV8)
     165    /* This is a public visible API, so we need to fill in a stub. */
     166    return false;
     167#else
    154168    bool fInV86Code;
    155169    int rc = VMR3ReqPriorityCallWaitU(pUVM, idCpu, (PFNRT)dbgfR3CpuInV86Code, 3, pUVM->pVM, idCpu, &fInV86Code);
    … …  
    157171        return false;
    158172    return fInV86Code;
     173#endif
    159174}
    160175

  • trunk/src/VBox/VMM/VMMR3/DBGFDisas.cpp

    r98103 r98972  
    9494*   Internal Functions                                                                                                           *
    9595*********************************************************************************************************************************/
     96#if !defined(VBOX_VMM_TARGET_ARMV8)
    9697static FNDISREADBYTES dbgfR3DisasInstrRead;
    9798
    … …  
    352353    return rc;
    353354}
     355#endif /* VBOX_VMM_TARGET_ARMV8 */
    354356
    355357
    … …  
    380382    int     rc;
    381383
     384#if defined(VBOX_VMM_TARGET_ARMV8)
     385    RT_NOREF(pVM, Sel, GCPtr, rc, fFlags, pszOutput, cbOutput, pcbInstr, pDisState);
     386    AssertReleaseFailed(); /** @todo */
     387    return VERR_NOT_IMPLEMENTED;
     388#else
    382389    /*
    383390     * Get the Sel and GCPtr if fFlags requests that.
    … …  
    610617    dbgfR3DisasInstrDone(&State);
    611618    return VINF_SUCCESS;
     619#endif /* !VBOX_VMM_TARGET_ARMV8*/
    612620}
    613621

  • trunk/src/VBox/VMM/VMMR3/DBGFMem.cpp

    r98103 r98972  
    586586        else
    587587        {
     588#if defined(VBOX_VMM_TARGET_ARMV8)
     589            AssertReleaseFailed();
     590#else
    588591            if (fFlags & DBGFPGDMP_FLAGS_CURRENT_CR3)
    589592                cr3 = CPUMGetGuestCR3(pVCpu);
    … …  
    595598                fFlags |= CPUMGetGuestEFER(pVCpu) & (MSR_K6_EFER_LME | MSR_K6_EFER_NXE);
    596599            }
     600#endif
    597601        }
    598602    }

  • trunk/src/VBox/VMM/VMMR3/DBGFStack.cpp

    r98103 r98972  
    8282        if (pInitialCtx)
    8383        {
     84#if defined(VBOX_VMM_TARGET_ARMV8)
     85            AssertReleaseFailed();
     86#else
    8487            m_State.u.x86.auRegs[X86_GREG_xAX] = pInitialCtx->rax;
    8588            m_State.u.x86.auRegs[X86_GREG_xCX] = pInitialCtx->rcx;
    … …  
    107110            m_State.u.x86.auSegs[X86_SREG_FS]  = pInitialCtx->fs.Sel;
    108111            m_State.u.x86.fRealOrV86           = CPUMIsGuestInRealOrV86ModeEx(pInitialCtx);
     112#endif
    109113        }
    110114        else if (hAs == DBGF_AS_R0)
    … …  
    816820
    817821    int rc = VINF_SUCCESS;
     822#if defined(VBOX_VMM_TARGET_ARMV8)
     823    if (pAddrPC)
     824        pCur->AddrPC = *pAddrPC;
     825    else
     826        DBGFR3AddrFromFlat(pUVM, &pCur->AddrPC, pCtx->Pc.u64);
     827#else
    818828    if (pAddrPC)
    819829        pCur->AddrPC = *pAddrPC;
    … …  
    822832    else
    823833        rc = DBGFR3AddrFromSelOff(pUVM, idCpu, &pCur->AddrPC, pCtx->cs.Sel, pCtx->rip);
     834#endif
    824835    if (RT_SUCCESS(rc))
    825836    {
    … …  
    875886
    876887
     888#if defined(VBOX_VMM_TARGET_ARMV8)
     889        RT_NOREF(pAddrFrame, pAddrStack);
     890        AssertReleaseFailed();
     891        rc = VERR_NOT_IMPLEMENTED;
     892#else
    877893        if (pAddrStack)
    878894            pCur->AddrStack = *pAddrStack;
    … …  
    889905        else if (RT_SUCCESS(rc))
    890906            rc = DBGFR3AddrFromSelOff(pUVM, idCpu, &pCur->AddrFrame, pCtx->ss.Sel, pCtx->rbp & fAddrMask);
     907#endif
    891908
    892909        /*
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