Changeset 98972 in vbox for trunk/include

Timestamp:

Mar 15, 2023 9:39:29 AM (21 months ago)

Author:

vboxsync

Message:

VMM: More ARMv8 x86/amd64 separation work, get past DBGF, bugref:10385

Location:

trunk/include/VBox

Files:

• types.h (modified) (1 diff)
• vmm/cpum-x86-amd64.h (modified) (2 diffs)
• vmm/cpum.h (modified) (1 diff)
• vmm/cpumctx-armv8.h (modified) (1 diff)

trunk/include/VBox/types.h

@@ -1190 +1190 @@
     /** The usual invalid zero entry. */
     CPUMMODE_INVALID = 0,
-    /** Real mode. */
+    /** Real mode - x86/amd64. */
     CPUMMODE_REAL,
-    /** Protected mode (32-bit). */
+    /** Protected mode (32-bit) - x86/amd64. */
     CPUMMODE_PROTECTED,
-    /** Long mode (64-bit). */
-    CPUMMODE_LONG
+    /** Long mode (64-bit) - x86/amd64. */
+    CPUMMODE_LONG,
+    /** ARMv8 - AARCH64 mode. */
+    CPUMMODE_ARMV8_AARCH64,
+    /** ARMv8 - AARCH32 mode. */
+    CPUMMODE_ARMV8_AARCH32,
+    /** hack forcing the size of the enum to 32-bits. */
+    CPUMMODE_32BIT_HACK = 0x7fffffff
 } CPUMMODE;
 

trunk/include/VBox/vmm/cpum-x86-amd64.h

@@ -2989 +2989 @@
 /** @} */
 
-VMMDECL(PCPUMCTX)       CPUMQueryGuestCtxPtr(PVMCPU pVCpu);
 #ifdef VBOX_INCLUDED_vmm_cpumctx_h
 VMM_INT_DECL(PCPUMCTXMSRS) CPUMQueryGuestCtxMsrsPtr(PVMCPU pVCpu);
@@ -3040 +3039 @@
 VMMDECL(bool)           CPUMIsHyperDebugStateActive(PVMCPU pVCpu);
 VMMDECL(uint32_t)       CPUMGetGuestCPL(PVMCPU pVCpu);
-VMMDECL(CPUMMODE)       CPUMGetGuestMode(PVMCPU pVCpu);
 VMMDECL(uint32_t)       CPUMGetGuestCodeBits(PVMCPU pVCpu);
 VMMDECL(DISCPUMODE)     CPUMGetGuestDisMode(PVMCPU pVCpu);

trunk/include/VBox/vmm/cpum.h

@@ -61 +61 @@
 #ifndef VBOX_FOR_DTRACE_LIB
 
+VMMDECL(PCPUMCTX)       CPUMQueryGuestCtxPtr(PVMCPU pVCpu);
+VMMDECL(CPUMMODE)       CPUMGetGuestMode(PVMCPU pVCpu);
+
 /** @name Guest Register Getters.
  * @{ */

trunk/include/VBox/vmm/cpumctx-armv8.h

@@ -186 +186 @@
 /** The SP register values are kept externally. */
 #define CPUMCTX_EXTRN_SP                        UINT64_C(0x0000000000000020)
+/** The PSTATE value is kept externally. */
+#define CPUMCTX_EXTRN_PSTATE                    UINT64_C(0x0000000000000040)
+/** @todo RSVD. */
+#define CPUMCTX_EXTRN_RSVD                      UINT64_C(0x0000000000000080)
 
 /** The X0 register value is kept externally. */
-#define CPUMCTX_EXTRN_X0                        UINT64_C(0x0000000000000040)
-/** The X0 register value is kept externally. */
-#define CPUMCTX_EXTRN_X1                        UINT64_C(0x0000000000000080)
-/** The X0 register value is kept externally. */
-#define CPUMCTX_EXTRN_X2                        UINT64_C(0x0000000000000100)
-/** The X0 register value is kept externally. */
-#define CPUMCTX_EXTRN_X3                        UINT64_C(0x0000000000000200)
+#define CPUMCTX_EXTRN_X0                        UINT64_C(0x0000000000000100)
+/** The X1 register value is kept externally. */
+#define CPUMCTX_EXTRN_X1                        UINT64_C(0x0000000000000200)
+/** The X2 register value is kept externally. */
+#define CPUMCTX_EXTRN_X2                        UINT64_C(0x0000000000000400)
+/** The X3 register value is kept externally. */
+#define CPUMCTX_EXTRN_X3                        UINT64_C(0x0000000000000800)
 /** The LR (X30) register value is kept externally. */
-#define CPUMCTX_EXTRN_LR                        UINT64_C(0x0000000000000400)
+#define CPUMCTX_EXTRN_LR                        UINT64_C(0x0000000000001000)
 /** The FP (X29) register value is kept externally. */
-#define CPUMCTX_EXTRN_FP                        UINT64_C(0x0000000000000800)
+#define CPUMCTX_EXTRN_FP                        UINT64_C(0x0000000000002000)
 /** The X4 through X28 register values are kept externally. */
-#define CPUMCTX_EXTRN_X4_X28                    UINT64_C(0x0000000000001000)
+#define CPUMCTX_EXTRN_X4_X28                    UINT64_C(0x0000000000004000)
 /** General purpose registers mask. */
-#define CPUMCTX_EXTRN_GPRS_MASK                 UINT64_C(0x0000000000001fc0)
+#define CPUMCTX_EXTRN_GPRS_MASK                 UINT64_C(0x0000000000007f00)
 
 /** The NEON SIMD & FP registers V0 through V31 are kept externally. */