Changeset 98980 in vbox for trunk/include
- Timestamp:
- Mar 15, 2023 11:46:48 AM (2 years ago)
- svn:sync-xref-src-repo-rev:
- 156329
- Location:
- trunk/include/VBox/vmm
- Files:
-
- 1 added
- 2 edited
- 1 copied
-
gim.h (modified) (1 diff)
-
iem-armv8.h (added)
-
iem-x86-amd64.h (copied) (copied from trunk/include/VBox/vmm/iem.h ) (5 diffs)
-
iem.h (modified) (4 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/include/VBox/vmm/gim.h
r98103 r98980 207 207 VMM_INT_DECL(VBOXSTRICTRC) GIMXcptUD(PVMCPUCC pVCpu, PCPUMCTX pCtx, PDISCPUSTATE pDis, uint8_t *pcbInstr); 208 208 VMM_INT_DECL(bool) GIMShouldTrapXcptUD(PVMCPUCC pVCpu); 209 #if !defined(VBOX_VMM_TARGET_ARMV8) 209 210 VMM_INT_DECL(VBOXSTRICTRC) GIMReadMsr(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t *puValue); 210 211 VMM_INT_DECL(VBOXSTRICTRC) GIMWriteMsr(PVMCPUCC pVCpu, uint32_t idMsr, PCCPUMMSRRANGE pRange, uint64_t uValue, uint64_t uRawValue); 212 #endif 211 213 VMM_INT_DECL(int) GIMQueryHypercallOpcodeBytes(PVM pVM, void *pvBuf, size_t cbBuf, 212 214 size_t *pcbWritten, uint16_t *puDisOpcode); -
trunk/include/VBox/vmm/iem-x86-amd64.h
r98959 r98980 34 34 */ 35 35 36 #ifndef VBOX_INCLUDED_vmm_iem_ h37 #define VBOX_INCLUDED_vmm_iem_ h36 #ifndef VBOX_INCLUDED_vmm_iem_x86_amd64_h 37 #define VBOX_INCLUDED_vmm_iem_x86_amd64_h 38 38 #ifndef RT_WITHOUT_PRAGMA_ONCE 39 39 # pragma once 40 40 #endif 41 41 42 #include <VBox/types.h>43 #include <VBox/vmm/trpm.h>44 42 #ifdef VBOX_WITH_NESTED_HWVIRT_VMX 45 43 # include <VBox/vmm/hm_vmx.h> 46 44 #endif 47 #include <iprt/assert.h>48 45 49 46 50 47 RT_C_DECLS_BEGIN 51 48 52 /** @defgroup grp_iem The Interpreted Execution Manager API. 53 * @ingroup grp_vmm 54 * @{ 55 */ 56 57 /** @name IEMXCPTRAISEINFO_XXX - Extra info. on a recursive exception situation. 58 * 59 * This is primarily used by HM for working around a PGM limitation (see 60 * @bugref{6607}) and special NMI/IRET handling. In the future, this may be 61 * used for diagnostics. 62 * 63 * @{ 64 */ 65 typedef uint32_t IEMXCPTRAISEINFO; 66 /** Pointer to a IEMXCPTINFO type. */ 67 typedef IEMXCPTRAISEINFO *PIEMXCPTRAISEINFO; 68 /** No addition info. available. */ 69 #define IEMXCPTRAISEINFO_NONE RT_BIT_32(0) 70 /** Delivery of a \#AC caused another \#AC. */ 71 #define IEMXCPTRAISEINFO_AC_AC RT_BIT_32(1) 72 /** Delivery of a \#PF caused another \#PF. */ 73 #define IEMXCPTRAISEINFO_PF_PF RT_BIT_32(2) 74 /** Delivery of a \#PF caused some contributory exception. */ 75 #define IEMXCPTRAISEINFO_PF_CONTRIBUTORY_XCPT RT_BIT_32(3) 76 /** Delivery of an external interrupt caused an exception. */ 77 #define IEMXCPTRAISEINFO_EXT_INT_XCPT RT_BIT_32(4) 78 /** Delivery of an external interrupt caused an \#PF. */ 79 #define IEMXCPTRAISEINFO_EXT_INT_PF RT_BIT_32(5) 80 /** Delivery of a software interrupt caused an exception. */ 81 #define IEMXCPTRAISEINFO_SOFT_INT_XCPT RT_BIT_32(6) 82 /** Delivery of an NMI caused an exception. */ 83 #define IEMXCPTRAISEINFO_NMI_XCPT RT_BIT_32(7) 84 /** Delivery of an NMI caused a \#PF. */ 85 #define IEMXCPTRAISEINFO_NMI_PF RT_BIT_32(8) 86 /** Can re-execute the instruction at CS:RIP. */ 87 #define IEMXCPTRAISEINFO_CAN_REEXEC_INSTR RT_BIT_32(9) 88 /** @} */ 89 90 91 /** @name IEMXCPTRAISE_XXX - Ways to handle a recursive exception condition. 49 /** @addtogroup grp_iem 92 50 * @{ */ 93 typedef enum IEMXCPTRAISE94 {95 /** Raise the current (second) exception. */96 IEMXCPTRAISE_CURRENT_XCPT = 0,97 /** Re-raise the previous (first) event (for HM, unused by IEM). */98 IEMXCPTRAISE_PREV_EVENT,99 /** Re-execute instruction at CS:RIP (for HM, unused by IEM). */100 IEMXCPTRAISE_REEXEC_INSTR,101 /** Raise a \#DF exception. */102 IEMXCPTRAISE_DOUBLE_FAULT,103 /** Raise a triple fault. */104 IEMXCPTRAISE_TRIPLE_FAULT,105 /** Cause a CPU hang. */106 IEMXCPTRAISE_CPU_HANG,107 /** Invalid sequence of events. */108 IEMXCPTRAISE_INVALID = 0x7fffffff109 } IEMXCPTRAISE;110 /** Pointer to a IEMXCPTRAISE type. */111 typedef IEMXCPTRAISE *PIEMXCPTRAISE;112 /** @} */113 114 115 /** @name Operand or addressing mode.116 * @{ */117 typedef uint8_t IEMMODE;118 #define IEMMODE_16BIT 0119 #define IEMMODE_32BIT 1120 #define IEMMODE_64BIT 2121 /** @} */122 123 124 /** @name IEM_XCPT_FLAGS_XXX - flags for iemRaiseXcptOrInt.125 * @{ */126 /** CPU exception. */127 #define IEM_XCPT_FLAGS_T_CPU_XCPT RT_BIT_32(0)128 /** External interrupt (from PIC, APIC, whatever). */129 #define IEM_XCPT_FLAGS_T_EXT_INT RT_BIT_32(1)130 /** Software interrupt (int or into, not bound).131 * Returns to the following instruction */132 #define IEM_XCPT_FLAGS_T_SOFT_INT RT_BIT_32(2)133 /** Takes an error code. */134 #define IEM_XCPT_FLAGS_ERR RT_BIT_32(3)135 /** Takes a CR2. */136 #define IEM_XCPT_FLAGS_CR2 RT_BIT_32(4)137 /** Generated by the breakpoint instruction. */138 #define IEM_XCPT_FLAGS_BP_INSTR RT_BIT_32(5)139 /** Generated by a DRx instruction breakpoint and RF should be cleared. */140 #define IEM_XCPT_FLAGS_DRx_INSTR_BP RT_BIT_32(6)141 /** Generated by the icebp instruction. */142 #define IEM_XCPT_FLAGS_ICEBP_INSTR RT_BIT_32(7)143 /** Generated by the overflow instruction. */144 #define IEM_XCPT_FLAGS_OF_INSTR RT_BIT_32(8)145 /** @} */146 51 147 52 … … 180 85 * dicates the behaviour here. */ 181 86 #define IEMTARGETCPU_CURRENT UINT32_C(9) 182 /** @} */183 184 185 /** @name IEM status codes.186 *187 * Not quite sure how this will play out in the end, just aliasing safe status188 * codes for now.189 *190 * @{ */191 #define VINF_IEM_RAISED_XCPT VINF_EM_RESCHEDULE192 87 /** @} */ 193 88 … … 288 183 #endif 289 184 290 VMMDECL(VBOXSTRICTRC) IEMExecOne(PVMCPUCC pVCpu);291 VMMDECL(VBOXSTRICTRC) IEMExecOneEx(PVMCPUCC pVCpu, uint32_t *pcbWritten);292 VMMDECL(VBOXSTRICTRC) IEMExecOneWithPrefetchedByPC(PVMCPUCC pVCpu, uint64_t OpcodeBytesPC,293 const void *pvOpcodeBytes, size_t cbOpcodeBytes);294 VMMDECL(VBOXSTRICTRC) IEMExecOneBypassEx(PVMCPUCC pVCpu, uint32_t *pcbWritten);295 VMMDECL(VBOXSTRICTRC) IEMExecOneBypassWithPrefetchedByPC(PVMCPUCC pVCpu, uint64_t OpcodeBytesPC,296 const void *pvOpcodeBytes, size_t cbOpcodeBytes);297 VMMDECL(VBOXSTRICTRC) IEMExecOneIgnoreLock(PVMCPUCC pVCpu);298 VMMDECL(VBOXSTRICTRC) IEMExecLots(PVMCPUCC pVCpu, uint32_t cMaxInstructions, uint32_t cPollRate, uint32_t *pcInstructions);299 /** Statistics returned by IEMExecForExits. */300 typedef struct IEMEXECFOREXITSTATS301 {302 uint32_t cInstructions;303 uint32_t cExits;304 uint32_t cMaxExitDistance;305 uint32_t cReserved;306 } IEMEXECFOREXITSTATS;307 /** Pointer to statistics returned by IEMExecForExits. */308 typedef IEMEXECFOREXITSTATS *PIEMEXECFOREXITSTATS;309 VMMDECL(VBOXSTRICTRC) IEMExecForExits(PVMCPUCC pVCpu, uint32_t fWillExit, uint32_t cMinInstructions, uint32_t cMaxInstructions,310 uint32_t cMaxInstructionsWithoutExits, PIEMEXECFOREXITSTATS pStats);311 VMMDECL(VBOXSTRICTRC) IEMInjectTrpmEvent(PVMCPUCC pVCpu);312 VMM_INT_DECL(VBOXSTRICTRC) IEMInjectTrap(PVMCPUCC pVCpu, uint8_t u8TrapNo, TRPMEVENT enmType, uint16_t uErrCode, RTGCPTR uCr2,313 uint8_t cbInstr);314 315 VMM_INT_DECL(int) IEMBreakpointSet(PVM pVM, RTGCPTR GCPtrBp);316 VMM_INT_DECL(int) IEMBreakpointClear(PVM pVM, RTGCPTR GCPtrBp);317 318 VMM_INT_DECL(void) IEMTlbInvalidateAll(PVMCPUCC pVCpu);319 VMM_INT_DECL(void) IEMTlbInvalidatePage(PVMCPUCC pVCpu, RTGCPTR GCPtr);320 VMM_INT_DECL(void) IEMTlbInvalidateAllPhysical(PVMCPUCC pVCpu);321 VMM_INT_DECL(void) IEMTlbInvalidateAllPhysicalAllCpus(PVMCC pVM, VMCPUID idCpuCaller);322 VMM_INT_DECL(bool) IEMGetCurrentXcpt(PVMCPUCC pVCpu, uint8_t *puVector, uint32_t *pfFlags, uint32_t *puErr,323 uint64_t *puCr2);324 VMM_INT_DECL(IEMXCPTRAISE) IEMEvaluateRecursiveXcpt(PVMCPUCC pVCpu, uint32_t fPrevFlags, uint8_t uPrevVector, uint32_t fCurFlags,325 uint8_t uCurVector, PIEMXCPTRAISEINFO pXcptRaiseInfo);326 327 185 /** @name Given Instruction Interpreters 328 186 * @{ */ … … 399 257 /** @} */ 400 258 401 /** @defgroup grp_iem_r 3 The IEM Host Context Ring-3API.259 /** @defgroup grp_iem_r0 The IEM Host Context Ring-0 API. 402 260 * @{ 403 261 */ … … 405 263 /** @} */ 406 264 407 408 /** @defgroup grp_iem_r3 The IEM Host Context Ring-3 API.409 * @{410 */411 VMMR3DECL(int) IEMR3Init(PVM pVM);412 VMMR3DECL(int) IEMR3Term(PVM pVM);413 VMMR3DECL(void) IEMR3Relocate(PVM pVM);414 VMMR3_INT_DECL(VBOXSTRICTRC) IEMR3ProcessForceFlag(PVM pVM, PVMCPUCC pVCpu, VBOXSTRICTRC rcStrict);415 265 /** @} */ 416 266 417 /** @} */418 419 267 RT_C_DECLS_END 420 268 421 #endif /* !VBOX_INCLUDED_vmm_iem_ h */422 269 #endif /* !VBOX_INCLUDED_vmm_iem_x86_amd64_h */ 270 -
trunk/include/VBox/vmm/iem.h
r98103 r98980 42 42 #include <VBox/types.h> 43 43 #include <VBox/vmm/trpm.h> 44 #ifdef VBOX_WITH_NESTED_HWVIRT_VMX 45 # include <VBox/vmm/hm_vmx.h> 44 #include <iprt/assert.h> 45 46 #ifdef VBOX_VMM_TARGET_ARMV8 47 # include <VBox/vmm/iem-armv8.h> 48 #else 49 # include <VBox/vmm/iem-x86-amd64.h> 46 50 #endif 47 #include <iprt/assert.h>48 51 49 52 … … 146 149 147 150 148 /** @name IEMTARGETCPU_XXX - IEM target CPU specification.149 *150 * This is a gross simpliciation of CPUMMICROARCH for dealing with really old151 * CPUs which didn't have much in the way of hinting at supported instructions152 * and features. This slowly changes with the introduction of CPUID with the153 * Intel Pentium.154 *155 * @{156 */157 /** The dynamic target CPU mode is for getting thru the BIOS and then use158 * the debugger or modifying instruction behaviour (e.g. HLT) to switch to a159 * different target CPU. */160 #define IEMTARGETCPU_DYNAMIC UINT32_C(0)161 /** Intel 8086/8088. */162 #define IEMTARGETCPU_8086 UINT32_C(1)163 /** NEC V20/V30.164 * @remarks must be between 8086 and 80186. */165 #define IEMTARGETCPU_V20 UINT32_C(2)166 /** Intel 80186/80188. */167 #define IEMTARGETCPU_186 UINT32_C(3)168 /** Intel 80286. */169 #define IEMTARGETCPU_286 UINT32_C(4)170 /** Intel 80386. */171 #define IEMTARGETCPU_386 UINT32_C(5)172 /** Intel 80486. */173 #define IEMTARGETCPU_486 UINT32_C(6)174 /** Intel Pentium . */175 #define IEMTARGETCPU_PENTIUM UINT32_C(7)176 /** Intel PentiumPro. */177 #define IEMTARGETCPU_PPRO UINT32_C(8)178 /** A reasonably current CPU, probably newer than the pentium pro when it comes179 * to the feature set and behaviour. Generally the CPUID info and CPU vendor180 * dicates the behaviour here. */181 #define IEMTARGETCPU_CURRENT UINT32_C(9)182 /** @} */183 184 185 151 /** @name IEM status codes. 186 152 * … … 192 158 /** @} */ 193 159 194 195 /** The CPUMCTX_EXTRN_XXX mask required to be cleared when interpreting anything.196 * IEM will ASSUME the caller of IEM APIs has ensured these are already present. */197 #define IEM_CPUMCTX_EXTRN_MUST_MASK ( CPUMCTX_EXTRN_GPRS_MASK \198 | CPUMCTX_EXTRN_RIP \199 | CPUMCTX_EXTRN_RFLAGS \200 | CPUMCTX_EXTRN_SS \201 | CPUMCTX_EXTRN_CS \202 | CPUMCTX_EXTRN_CR0 \203 | CPUMCTX_EXTRN_CR3 \204 | CPUMCTX_EXTRN_CR4 \205 | CPUMCTX_EXTRN_APIC_TPR \206 | CPUMCTX_EXTRN_EFER \207 | CPUMCTX_EXTRN_DR7 )208 /** The CPUMCTX_EXTRN_XXX mask needed when injecting an exception/interrupt.209 * IEM will import missing bits, callers are encouraged to make these registers210 * available prior to injection calls if fetching state anyway. */211 #define IEM_CPUMCTX_EXTRN_XCPT_MASK ( IEM_CPUMCTX_EXTRN_MUST_MASK \212 | CPUMCTX_EXTRN_CR2 \213 | CPUMCTX_EXTRN_SREG_MASK \214 | CPUMCTX_EXTRN_TABLE_MASK )215 /** The CPUMCTX_EXTRN_XXX mask required to be cleared when calling any216 * IEMExecDecoded API not using memory. IEM will ASSUME the caller of IEM217 * APIs has ensured these are already present.218 * @note ASSUMES execution engine has checked for instruction breakpoints219 * during decoding. */220 #define IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK ( CPUMCTX_EXTRN_RIP \221 | CPUMCTX_EXTRN_RFLAGS \222 | CPUMCTX_EXTRN_SS /* for CPL */ \223 | CPUMCTX_EXTRN_CS /* for mode */ \224 | CPUMCTX_EXTRN_CR0 /* for mode */ \225 | CPUMCTX_EXTRN_EFER /* for mode */ )226 /** The CPUMCTX_EXTRN_XXX mask required to be cleared when calling any227 * IEMExecDecoded API using memory. IEM will ASSUME the caller of IEM228 * APIs has ensured these are already present.229 * @note ASSUMES execution engine has checked for instruction breakpoints230 * during decoding. */231 #define IEM_CPUMCTX_EXTRN_EXEC_DECODED_MEM_MASK ( IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \232 | CPUMCTX_EXTRN_CR3 /* for page tables */ \233 | CPUMCTX_EXTRN_CR4 /* for mode paging mode */ \234 | CPUMCTX_EXTRN_DR7 /* for memory breakpoints */ )235 236 #ifdef VBOX_WITH_NESTED_HWVIRT_VMX237 /** The CPUMCTX_EXTRN_XXX mask needed when calling IEMExecDecodedVmlaunchVmresume().238 * IEM will ASSUME the caller has ensured these are already present. */239 # define IEM_CPUMCTX_EXTRN_VMX_VMENTRY_MASK ( IEM_CPUMCTX_EXTRN_EXEC_DECODED_NO_MEM_MASK \240 | CPUMCTX_EXTRN_CR2 \241 | CPUMCTX_EXTRN_HWVIRT )242 243 /** The CPUMCTX_EXTRN_XXX mask that the IEM VM-exit code will import on-demand when244 * needed, primarily because there are several IEM VM-exit interface functions and245 * some of which may not cause a VM-exit at all.246 *247 * This is currently unused, but keeping it here in case we can get away a bit more248 * fine-grained state handling.249 *250 * @note Update HM_CHANGED_VMX_VMEXIT_MASK if something here changes. */251 # define IEM_CPUMCTX_EXTRN_VMX_VMEXIT_MASK ( CPUMCTX_EXTRN_CR0 | CPUMCTX_EXTRN_CR3 | CPUMCTX_EXTRN_CR4 \252 | CPUMCTX_EXTRN_DR7 | CPUMCTX_EXTRN_DR6 \253 | CPUMCTX_EXTRN_EFER \254 | CPUMCTX_EXTRN_SYSENTER_MSRS \255 | CPUMCTX_EXTRN_OTHER_MSRS /* for PAT MSR */ \256 | CPUMCTX_EXTRN_RIP | CPUMCTX_EXTRN_RSP | CPUMCTX_EXTRN_RFLAGS \257 | CPUMCTX_EXTRN_SREG_MASK \258 | CPUMCTX_EXTRN_TR \259 | CPUMCTX_EXTRN_LDTR | CPUMCTX_EXTRN_GDTR | CPUMCTX_EXTRN_IDTR \260 | CPUMCTX_EXTRN_HWVIRT )261 #endif262 263 #ifdef VBOX_WITH_NESTED_HWVIRT_SVM264 /** The CPUMCTX_EXTRN_XXX mask needed when calling IEMExecSvmVmexit().265 * IEM will ASSUME the caller has ensured these are already present. */266 # define IEM_CPUMCTX_EXTRN_SVM_VMEXIT_MASK ( CPUMCTX_EXTRN_RSP \267 | CPUMCTX_EXTRN_RAX \268 | CPUMCTX_EXTRN_RIP \269 | CPUMCTX_EXTRN_RFLAGS \270 | CPUMCTX_EXTRN_CS \271 | CPUMCTX_EXTRN_SS \272 | CPUMCTX_EXTRN_DS \273 | CPUMCTX_EXTRN_ES \274 | CPUMCTX_EXTRN_GDTR \275 | CPUMCTX_EXTRN_IDTR \276 | CPUMCTX_EXTRN_CR_MASK \277 | CPUMCTX_EXTRN_EFER \278 | CPUMCTX_EXTRN_DR6 \279 | CPUMCTX_EXTRN_DR7 \280 | CPUMCTX_EXTRN_OTHER_MSRS \281 | CPUMCTX_EXTRN_HWVIRT \282 | CPUMCTX_EXTRN_APIC_TPR \283 | CPUMCTX_EXTRN_HM_SVM_HWVIRT_VIRQ)284 285 /** The CPUMCTX_EXTRN_XXX mask needed when calling IEMExecDecodedVmrun().286 * IEM will ASSUME the caller has ensured these are already present. */287 # define IEM_CPUMCTX_EXTRN_SVM_VMRUN_MASK IEM_CPUMCTX_EXTRN_SVM_VMEXIT_MASK288 #endif289 160 290 161 VMMDECL(VBOXSTRICTRC) IEMExecOne(PVMCPUCC pVCpu); … … 325 196 uint8_t uCurVector, PIEMXCPTRAISEINFO pXcptRaiseInfo); 326 197 327 /** @name Given Instruction Interpreters328 * @{ */329 VMM_INT_DECL(VBOXSTRICTRC) IEMExecStringIoWrite(PVMCPUCC pVCpu, uint8_t cbValue, IEMMODE enmAddrMode,330 bool fRepPrefix, uint8_t cbInstr, uint8_t iEffSeg, bool fIoChecked);331 VMM_INT_DECL(VBOXSTRICTRC) IEMExecStringIoRead(PVMCPUCC pVCpu, uint8_t cbValue, IEMMODE enmAddrMode,332 bool fRepPrefix, uint8_t cbInstr, bool fIoChecked);333 VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedOut(PVMCPUCC pVCpu, uint8_t cbInstr, uint16_t u16Port, bool fImm, uint8_t cbReg);334 VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedIn(PVMCPUCC pVCpu, uint8_t cbInstr, uint16_t u16Port, bool fImm, uint8_t cbReg);335 VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedMovCRxWrite(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iCrReg, uint8_t iGReg);336 VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedMovCRxRead(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iGReg, uint8_t iCrReg);337 VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedMovDRxWrite(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iDrReg, uint8_t iGReg);338 VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedMovDRxRead(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iGReg, uint8_t iDrReg);339 VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedClts(PVMCPUCC pVCpu, uint8_t cbInstr);340 VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedLmsw(PVMCPUCC pVCpu, uint8_t cbInstr, uint16_t uValue, RTGCPTR GCPtrEffDst);341 VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedXsetbv(PVMCPUCC pVCpu, uint8_t cbInstr);342 VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedWbinvd(PVMCPUCC pVCpu, uint8_t cbInstr);343 VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedInvd(PVMCPUCC pVCpu, uint8_t cbInstr);344 VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedInvlpg(PVMCPUCC pVCpu, uint8_t cbInstr, RTGCPTR GCPtrPage);345 VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedInvpcid(PVMCPUCC pVCpu, uint8_t cbInstr, uint8_t iEffSeg, RTGCPTR GCPtrDesc,346 uint64_t uType);347 VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedCpuid(PVMCPUCC pVCpu, uint8_t cbInstr);348 VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedRdpmc(PVMCPUCC pVCpu, uint8_t cbInstr);349 VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedRdtsc(PVMCPUCC pVCpu, uint8_t cbInstr);350 VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedRdtscp(PVMCPUCC pVCpu, uint8_t cbInstr);351 VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedRdmsr(PVMCPUCC pVCpu, uint8_t cbInstr);352 VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedWrmsr(PVMCPUCC pVCpu, uint8_t cbInstr);353 VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedMonitor(PVMCPUCC pVCpu, uint8_t cbInstr);354 VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedMwait(PVMCPUCC pVCpu, uint8_t cbInstr);355 VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedHlt(PVMCPUCC pVCpu, uint8_t cbInstr);356 357 #ifdef VBOX_WITH_NESTED_HWVIRT_SVM358 VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedClgi(PVMCPUCC pVCpu, uint8_t cbInstr);359 VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedStgi(PVMCPUCC pVCpu, uint8_t cbInstr);360 VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmload(PVMCPUCC pVCpu, uint8_t cbInstr);361 VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmsave(PVMCPUCC pVCpu, uint8_t cbInstr);362 VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedInvlpga(PVMCPUCC pVCpu, uint8_t cbInstr);363 VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmrun(PVMCPUCC pVCpu, uint8_t cbInstr);364 VMM_INT_DECL(VBOXSTRICTRC) IEMExecSvmVmexit(PVMCPUCC pVCpu, uint64_t uExitCode, uint64_t uExitInfo1, uint64_t uExitInfo2);365 #endif366 367 #ifdef VBOX_WITH_NESTED_HWVIRT_VMX368 VMM_INT_DECL(void) IEMReadVmxVmcsField(PCVMXVVMCS pVmcs, uint64_t u64VmcsField, uint64_t *pu64Dst);369 VMM_INT_DECL(void) IEMWriteVmxVmcsField(PVMXVVMCS pVmcs, uint64_t u64VmcsField, uint64_t u64Val);370 VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVirtApicAccessMsr(PVMCPUCC pVCpu, uint32_t idMsr, uint64_t *pu64Val, bool fWrite);371 VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitApicWrite(PVMCPUCC pVCpu);372 VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitPreemptTimer(PVMCPUCC pVCpu);373 VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitExtInt(PVMCPUCC pVCpu, uint8_t uVector, bool fIntPending);374 VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitXcpt(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo, PCVMXVEXITEVENTINFO pExitEventInfo);375 VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitXcptNmi(PVMCPUCC pVCpu);376 VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitTripleFault(PVMCPUCC pVCpu);377 VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitStartupIpi(PVMCPUCC pVCpu, uint8_t uVector);378 VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitInstrWithInfo(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo);379 VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitInstr(PVMCPUCC pVCpu, uint32_t uExitReason, uint8_t cbInstr);380 VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitTrapLike(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo);381 VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitTaskSwitch(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo, PCVMXVEXITEVENTINFO pExitEventInfo);382 VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitApicAccess(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo, PCVMXVEXITEVENTINFO pExitEventInfo);383 VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexit(PVMCPUCC pVCpu, uint32_t uExitReason, uint64_t uExitQual);384 VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmread(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo);385 VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmwrite(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo);386 VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmptrld(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo);387 VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmptrst(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo);388 VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmclear(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo);389 VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmlaunchVmresume(PVMCPUCC pVCpu, uint8_t cbInstr, VMXINSTRID uInstrId);390 VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmxon(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo);391 VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedVmxoff(PVMCPUCC pVCpu, uint8_t cbInstr);392 VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedInvvpid(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo);393 # ifdef VBOX_WITH_NESTED_HWVIRT_VMX_EPT394 VMM_INT_DECL(VBOXSTRICTRC) IEMExecDecodedInvept(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo);395 VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitEptViolation(PVMCPUCC pVCpu, PCVMXVEXITINFO pExitInfo, PCVMXVEXITEVENTINFO pExitEventInfo);396 VMM_INT_DECL(VBOXSTRICTRC) IEMExecVmxVmexitEptMisconfig(PVMCPUCC pVCpu, RTGCPHYS GCPhysAddr, PCVMXVEXITEVENTINFO pExitEventInfo);397 # endif398 #endif399 /** @} */400 401 /** @defgroup grp_iem_r3 The IEM Host Context Ring-3 API.402 * @{403 */404 VMMR0_INT_DECL(int) IEMR0InitVM(PGVM pGVM);405 /** @} */406 407 408 198 /** @defgroup grp_iem_r3 The IEM Host Context Ring-3 API. 409 199 * @{
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