VirtualBox

Changeset 99051 in vbox for trunk/src/VBox/VMM/VMMAll


Ignore:
Timestamp:
Mar 19, 2023 4:40:06 PM (2 years ago)
Author:
vboxsync
svn:sync-xref-src-repo-rev:
156416
Message:

VMM: More ARMv8 x86/amd64 separation work, VBoxVMMArm compiles and links now, bugref:10385

Location:
trunk/src/VBox/VMM/VMMAll
Files:
2 added
7 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/VMM/VMMAll/DBGFAll.cpp

    r98103 r99051  
    5353
    5454
     55#if !defined(VBOX_VMM_TARGET_ARMV8)
    5556/**
    5657 * Gets the hardware breakpoint configuration as DR7.
    … …  
    444445    return 0;
    445446}
     447#endif /* VBOX_VMM_TARGET_ARMV8 */
    446448
    447449
    … …  
    524526         * Any events on the stack. Should the incoming event be ignored?
    525527         */
     528#if defined(VBOX_VMM_TARGET_ARMV8)
     529        uint64_t const rip = CPUMGetGuestFlatPC(pVCpu); /* rip is a misnomer but saves us #ifdef's later on. */
     530#else
    526531        uint64_t const rip = CPUMGetGuestRIP(pVCpu);
     532#endif
    527533        uint32_t i = pVCpu->dbgf.s.cEvents;
    528534        if (i > 0)

  • trunk/src/VBox/VMM/VMMAll/EMAll.cpp

    r98103 r99051  
    110110
    111111
     112#if !defined(VBOX_VMM_TARGET_ARMV8)
    112113/**
    113114 * Prepare an MWAIT - essentials of the MONITOR instruction.
    … …  
    251252    return false;
    252253}
     254#endif
    253255
    254256
    … …  
    876878        if (RT_FAILURE(rc))
    877879        {
     880#if defined(VBOX_VMM_TARGET_ARMV8)
     881            AssertReleaseFailed();
     882#else
    878883            /*
    879884             * If we fail to find the page via the guest's page tables
    … …  
    887892                    HMInvalidatePage(pVCpu, uSrcAddr + cbToRead - 1);
    888893            }
     894#endif
    889895        }
    890896    }
    … …  
    907913VMM_INT_DECL(int) EMInterpretDisasCurrent(PVMCPUCC pVCpu, PDISCPUSTATE pDis, unsigned *pcbInstr)
    908914{
     915#if defined(VBOX_VMM_TARGET_ARMV8)
     916    return EMInterpretDisasOneEx(pVCpu, (RTGCUINTPTR)CPUMGetGuestFlatPC(pVCpu), pDis, pcbInstr);
     917#else
    909918    PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
    910919    RTGCPTR  GCPtrInstr;
    911 #if 0
     920
     921# if 0
    912922    int rc = SELMToFlatEx(pVCpu, DISSELREG_CS, pCtx, pCtx->rip, 0, &GCPtrInstr);
    913 #else
     923# else
    914924/** @todo Get the CPU mode as well while we're at it! */
    915925    int rc = SELMValidateAndConvertCSAddr(pVCpu, pCtx->eflags.u, pCtx->ss.Sel, pCtx->cs.Sel, &pCtx->cs, pCtx->rip, &GCPtrInstr);
    916 #endif
     926# endif
    917927    if (RT_SUCCESS(rc))
    918928        return EMInterpretDisasOneEx(pVCpu, (RTGCUINTPTR)GCPtrInstr, pDis, pcbInstr);
    … …  
    921931         pCtx->cs.Sel, (RTGCPTR)pCtx->rip, pCtx->ss.Sel & X86_SEL_RPL, rc));
    922932    return rc;
     933#endif
    923934}
    924935
    … …  
    965976VMM_INT_DECL(VBOXSTRICTRC) EMInterpretInstruction(PVMCPUCC pVCpu)
    966977{
     978#if defined(VBOX_VMM_TARGET_ARMV8)
     979    LogFlow(("EMInterpretInstruction %RGv\n", (RTGCPTR)CPUMGetGuestFlatPC(pVCpu)));
     980#else
    967981    LogFlow(("EMInterpretInstruction %RGv\n", (RTGCPTR)CPUMGetGuestRIP(pVCpu)));
     982#endif
    968983
    969984    VBOXSTRICTRC rc = IEMExecOneBypassEx(pVCpu, NULL /*pcbWritten*/);

  • trunk/src/VBox/VMM/VMMAll/GIMAll.cpp

    r98103 r99051  
    9191    switch (pVM->gim.s.enmProviderId)
    9292    {
     93#if !defined(VBOX_VMM_TARGET_ARMV8)
    9394        case GIMPROVIDERID_HYPERV:
    9495            return gimHvGetMmio2Regions(pVM, pcRegions);
    95 
     96#endif
    9697        default:
    9798            break;
    … …  
    116117    switch (pVM->gim.s.enmProviderId)
    117118    {
     119#if !defined(VBOX_VMM_TARGET_ARMV8)
    118120        case GIMPROVIDERID_HYPERV:
    119121            return gimHvAreHypercallsEnabled(pVM);
    … …  
    121123        case GIMPROVIDERID_KVM:
    122124            return gimKvmAreHypercallsEnabled(pVCpu);
    123 
     125#endif
    124126        default:
    125127            return false;
    … …  
    161163    switch (pVM->gim.s.enmProviderId)
    162164    {
     165#if !defined(VBOX_VMM_TARGET_ARMV8)
    163166        case GIMPROVIDERID_HYPERV:
    164167            return gimHvHypercall(pVCpu, pCtx);
    … …  
    166169        case GIMPROVIDERID_KVM:
    167170            return gimKvmHypercall(pVCpu, pCtx);
    168 
     171#endif
    169172        default:
    170173            AssertMsgFailed(("GIMHypercall: for provider %u not available/implemented\n", pVM->gim.s.enmProviderId));
    … …  
    212215    switch (pVM->gim.s.enmProviderId)
    213216    {
     217#if !defined(VBOX_VMM_TARGET_ARMV8)
    214218        case GIMPROVIDERID_HYPERV:
    215219            return gimHvHypercallEx(pVCpu, pCtx, uDisOpcode, cbInstr);
    … …  
    217221        case GIMPROVIDERID_KVM:
    218222            return gimKvmHypercallEx(pVCpu, pCtx, uDisOpcode, cbInstr);
    219 
     223#endif
    220224        default:
    221225            AssertMsgFailedReturn(("enmProviderId=%u\n", pVM->gim.s.enmProviderId), VERR_GIM_HYPERCALLS_NOT_AVAILABLE);
    … …  
    254258        switch (pVM->gim.s.enmProviderId)
    255259        {
     260#if !defined(VBOX_VMM_TARGET_ARMV8)
    256261            case GIMPROVIDERID_HYPERV:
    257262                return gimHvHypercallEx(pVCpu, pCtx, Dis.pCurInstr->uOpcode, Dis.cbInstr);
    … …  
    259264            case GIMPROVIDERID_KVM:
    260265                return gimKvmHypercallEx(pVCpu, pCtx, Dis.pCurInstr->uOpcode, Dis.cbInstr);
    261 
     266#endif
    262267            default:
    263268                AssertMsgFailed(("GIMExecHypercallInstr: for provider %u not available/implemented\n", pVM->gim.s.enmProviderId));
    … …  
    266271    }
    267272
     273#if !defined(VBOX_VMM_TARGET_ARMV8)
    268274    Log(("GIM: GIMExecHypercallInstr: Failed to disassemble CS:RIP=%04x:%08RX64. rc=%Rrc\n", pCtx->cs.Sel, pCtx->rip, rc));
     275#endif
    269276    return rc;
    270277}
    … …  
    285292    switch (pVM->gim.s.enmProviderId)
    286293    {
     294#if !defined(VBOX_VMM_TARGET_ARMV8)
    287295        case GIMPROVIDERID_HYPERV:
    288296            return gimHvIsParavirtTscEnabled(pVM);
    … …  
    290298        case GIMPROVIDERID_KVM:
    291299            return gimKvmIsParavirtTscEnabled(pVM);
    292 
     300#endif
    293301        default:
    294302            break;
    … …  
    318326    switch (pVM->gim.s.enmProviderId)
    319327    {
     328#if !defined(VBOX_VMM_TARGET_ARMV8)
    320329        case GIMPROVIDERID_KVM:
    321330            return gimKvmShouldTrapXcptUD(pVM);
    … …  
    323332        case GIMPROVIDERID_HYPERV:
    324333            return gimHvShouldTrapXcptUD(pVCpu);
    325 
     334#endif
    326335        default:
    327336            return false;
    … …  
    362371    switch (pVM->gim.s.enmProviderId)
    363372    {
     373#if !defined(VBOX_VMM_TARGET_ARMV8)
    364374        case GIMPROVIDERID_KVM:
    365375            return gimKvmXcptUD(pVM, pVCpu, pCtx, pDis, pcbInstr);
    … …  
    367377        case GIMPROVIDERID_HYPERV:
    368378            return gimHvXcptUD(pVCpu, pCtx, pDis, pcbInstr);
    369 
     379#endif
    370380        default:
    371381            return VERR_GIM_OPERATION_FAILED;
    … …  
    374384
    375385
     386#if !defined(VBOX_VMM_TARGET_ARMV8)
    376387/**
    377388 * Invokes the read-MSR handler for the GIM provider configured for the VM.
    … …  
    504515    return VERR_BUFFER_OVERFLOW;
    505516}
    506 
     517#endif
     518

  • trunk/src/VBox/VMM/VMMAll/IOMAllMmioNew.cpp

    r98103 r99051  
    10881088    AssertReturn(pDevIns, VERR_INVALID_POINTER);
    10891089
     1090#if defined(VBOX_VMM_TARGET_ARMV8)
     1091    /** @todo NEM: MMIO page aliasing. */
     1092    return VINF_SUCCESS;    /* ignore */ /** @todo return some indicator if we fail here */
     1093#else
    10901094/** @todo Why is this restricted to protected mode???  Try it in all modes! */
    10911095    PVMCPUCC pVCpu = VMMGetCpu(pVM);
    … …  
    11021106     */
    11031107    AssertReturn(hRegion < RT_MIN(pVM->iom.s.cMmioRegs, pVM->iom.s.cMmioAlloc), VERR_IOM_INVALID_MMIO_HANDLE);
    1104 #ifdef IN_RING0
     1108# ifdef IN_RING0
    11051109    AssertReturn(hRegion < pVM->iomr0.s.cMmioAlloc, VERR_IOM_INVALID_MMIO_HANDLE);
    11061110    PIOMMMIOENTRYR3 const pRegEntry = &pVM->iomr0.s.paMmioRing3Regs[hRegion];
    … …  
    11101114                 || (   pVM->iomr0.s.paMmioRegs[hRegion].pDevIns == NULL
    11111115                     && pRegEntry->pDevIns == pDevIns->pDevInsForR3), VERR_ACCESS_DENIED);
    1112 #else
     1116# else
    11131117    PIOMMMIOENTRYR3 const pRegEntry = &pVM->iom.s.paMmioRegs[hRegion];
    11141118    AssertReturn(pRegEntry->cbRegion > 0, VERR_IOM_INVALID_MMIO_HANDLE);
    11151119    AssertReturn(pRegEntry->pDevIns == pDevIns, VERR_ACCESS_DENIED);
    1116 #endif
     1120# endif
    11171121    AssertReturn(offRegion < pRegEntry->cbRegion, VERR_OUT_OF_RANGE);
    11181122    Assert((pRegEntry->cbRegion & GUEST_PAGE_OFFSET_MASK) == 0);
    … …  
    11441148/** @todo either ditch this or replace it with something that works in the
    11451149 *        nested case, since we really only care about nested paging! */
    1146 #if 0
     1150# if 0
    11471151    /*
    11481152     * Modify the shadow page table. Since it's an MMIO page it won't be present and we
    … …  
    11511155     * Note: This is a NOP in the EPT case; we'll just let it fault again to resync the page.
    11521156     */
    1153 # if 0 /* The assertion is wrong for the PGM_SYNC_CLEAR_PGM_POOL and VINF_PGM_HANDLER_ALREADY_ALIASED cases. */
    1154 #  ifdef VBOX_STRICT
     1157#  if 0 /* The assertion is wrong for the PGM_SYNC_CLEAR_PGM_POOL and VINF_PGM_HANDLER_ALREADY_ALIASED cases. */
     1158#   ifdef VBOX_STRICT
    11551159    uint64_t fFlags;
    11561160    RTHCPHYS HCPhys;
    11571161    rc = PGMShwGetPage(pVCpu, (RTGCPTR)GCPhys, &fFlags, &HCPhys);
    11581162    Assert(rc == VERR_PAGE_NOT_PRESENT || rc == VERR_PAGE_TABLE_NOT_PRESENT);
     1163#   endif
    11591164#  endif
    1160 # endif
    11611165    rc = PGMPrefetchPage(pVCpu, (RTGCPTR)GCPhys);
    11621166    Assert(rc == VINF_SUCCESS || rc == VERR_PAGE_NOT_PRESENT || rc == VERR_PAGE_TABLE_NOT_PRESENT);
    1163 #endif
     1167# endif
    11641168    return rc;
     1169#endif
    11651170}
    11661171
    … …  
    12531258    AssertReturn(pDevIns, VERR_INVALID_POINTER);
    12541259
     1260#if defined(VBOX_VMM_TARGET_ARMV8)
     1261    /** @todo NEM: MMIO page aliasing. */
     1262    return VINF_SUCCESS;    /* ignore */ /** @todo return some indicator if we fail here */
     1263#else
    12551264/** @todo Get rid of this this real/protected or nested paging restriction,
    12561265 *        it probably shouldn't be here and would be nasty when the CPU
    … …  
    12701279     */
    12711280    AssertReturn(hRegion < RT_MIN(pVM->iom.s.cMmioRegs, pVM->iom.s.cMmioAlloc), VERR_IOM_INVALID_MMIO_HANDLE);
    1272 #ifdef IN_RING0
     1281# ifdef IN_RING0
    12731282    AssertReturn(hRegion < pVM->iomr0.s.cMmioAlloc, VERR_IOM_INVALID_MMIO_HANDLE);
    12741283    PIOMMMIOENTRYR3 const pRegEntry = &pVM->iomr0.s.paMmioRing3Regs[hRegion];
    … …  
    12771286                 || (   pVM->iomr0.s.paMmioRegs[hRegion].pDevIns == NULL
    12781287                     && pRegEntry->pDevIns == pDevIns->pDevInsForR3), VERR_ACCESS_DENIED);
    1279 #else
     1288# else
    12801289    PIOMMMIOENTRYR3 const pRegEntry = &pVM->iom.s.paMmioRegs[hRegion];
    12811290    AssertReturn(pRegEntry->cbRegion > 0, VERR_IOM_INVALID_MMIO_HANDLE);
    12821291    AssertReturn(pRegEntry->pDevIns == pDevIns, VERR_ACCESS_DENIED);
    1283 #endif
     1292# endif
    12841293    Assert((pRegEntry->cbRegion & GUEST_PAGE_OFFSET_MASK) == 0);
    12851294
    … …  
    13171326# endif
    13181327    return rc;
    1319 }
    1320 
     1328#endif
     1329}
     1330

  • trunk/src/VBox/VMM/VMMAll/PDMAll.cpp

    r98103 r99051  
    7070    {
    7171        VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_APIC);
     72#if defined(VBOX_VMM_TARGET_ARMV8)
     73        AssertReleaseFailed();
     74#else
    7275        uint32_t uTagSrc;
    7376        rc = APICGetInterrupt(pVCpu, pu8Interrupt, &uTagSrc);
    … …  
    8083        /* else if it's masked by TPR/PPR/whatever, go ahead checking the PIC. Such masked
    8184           interrupts shouldn't prevent ExtINT from being delivered. */
     85#endif
    8286    }
    8387

  • trunk/src/VBox/VMM/VMMAll/PGMAllHandler.cpp

    r98103 r99051  
    757757    int rc = pgmPoolTrackUpdateGCPhys(pVM, GCPhysPage, pPage, true /*fFlushPTEs*/, &fFlushTLBs);
    758758    AssertLogRelRCReturnVoid(rc);
     759#if defined(VBOX_VMM_TARGET_ARMV8)
     760    AssertReleaseFailed();
     761#else
    759762    HMFlushTlbOnAllVCpus(pVM);
     763#endif
    760764
    761765    /*

  • trunk/src/VBox/VMM/VMMAll/PGMAllPool.cpp

    r98103 r99051  
    51805180    if (pgmPoolIsPageLocked(pPage))
    51815181    {
     5182#if !defined(VBOX_VMM_TARGET_ARMV8)
    51825183        AssertMsg(   pPage->enmKind == PGMPOOLKIND_64BIT_PML4
    51835184                  || pPage->enmKind == PGMPOOLKIND_PAE_PDPT
    … …  
    51915192                  || pPage->enmKind == PGMPOOLKIND_ROOT_NESTED,
    51925193                  ("Can't free the shadow CR3! (%RHp vs %RHp kind=%d\n", PGMGetHyperCR3(VMMGetCpu(pVM)), pPage->Core.Key, pPage->enmKind));
     5194#endif
    51935195        Log(("pgmPoolFlushPage: current active shadow CR3, rejected. enmKind=%s idx=%d\n", pgmPoolPoolKindToStr(pPage->enmKind), pPage->idx));
    51945196        PGM_UNLOCK(pVM);
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