- Timestamp:
- Mar 20, 2023 2:58:57 PM (21 months ago)
- Location:
- trunk
- Files:
-
- 1 added
- 6 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/include/VBox/vmm/dbgf.h
r98103 r99070 2038 2038 DBGFREG_IDTR, 2039 2039 2040 /** The end of the x86 registers. */ 2041 DBGFREG_X86_END = DBGFREG_IDTR, 2042 2043 /** @name ARMv8 register identifiers. 2044 * @{ */ 2045 DBGFREG_ARMV8_FIRST, 2046 /** General purpose registers. */ 2047 DBGFREG_ARMV8_GREG_X0, 2048 DBGFREG_ARMV8_GREG_W0 = DBGFREG_ARMV8_GREG_X0, 2049 DBGFREG_ARMV8_GREG_X1, 2050 DBGFREG_ARMV8_GREG_W1 = DBGFREG_ARMV8_GREG_X1, 2051 DBGFREG_ARMV8_GREG_X2, 2052 DBGFREG_ARMV8_GREG_W2 = DBGFREG_ARMV8_GREG_X2, 2053 DBGFREG_ARMV8_GREG_X3, 2054 DBGFREG_ARMV8_GREG_W3 = DBGFREG_ARMV8_GREG_X3, 2055 DBGFREG_ARMV8_GREG_X4, 2056 DBGFREG_ARMV8_GREG_W4 = DBGFREG_ARMV8_GREG_X4, 2057 DBGFREG_ARMV8_GREG_X5, 2058 DBGFREG_ARMV8_GREG_W5 = DBGFREG_ARMV8_GREG_X5, 2059 DBGFREG_ARMV8_GREG_X6, 2060 DBGFREG_ARMV8_GREG_W6 = DBGFREG_ARMV8_GREG_X6, 2061 DBGFREG_ARMV8_GREG_X7, 2062 DBGFREG_ARMV8_GREG_W7 = DBGFREG_ARMV8_GREG_X7, 2063 DBGFREG_ARMV8_GREG_X8, 2064 DBGFREG_ARMV8_GREG_W8 = DBGFREG_ARMV8_GREG_X8, 2065 DBGFREG_ARMV8_GREG_X9, 2066 DBGFREG_ARMV8_GREG_W9 = DBGFREG_ARMV8_GREG_X9, 2067 DBGFREG_ARMV8_GREG_X10, 2068 DBGFREG_ARMV8_GREG_W10 = DBGFREG_ARMV8_GREG_X10, 2069 DBGFREG_ARMV8_GREG_X11, 2070 DBGFREG_ARMV8_GREG_W11 = DBGFREG_ARMV8_GREG_X11, 2071 DBGFREG_ARMV8_GREG_X12, 2072 DBGFREG_ARMV8_GREG_W12 = DBGFREG_ARMV8_GREG_X12, 2073 DBGFREG_ARMV8_GREG_X13, 2074 DBGFREG_ARMV8_GREG_W13 = DBGFREG_ARMV8_GREG_X13, 2075 DBGFREG_ARMV8_GREG_X14, 2076 DBGFREG_ARMV8_GREG_W14 = DBGFREG_ARMV8_GREG_X14, 2077 DBGFREG_ARMV8_GREG_X15, 2078 DBGFREG_ARMV8_GREG_W15 = DBGFREG_ARMV8_GREG_X15, 2079 DBGFREG_ARMV8_GREG_X16, 2080 DBGFREG_ARMV8_GREG_W16 = DBGFREG_ARMV8_GREG_X16, 2081 DBGFREG_ARMV8_GREG_X17, 2082 DBGFREG_ARMV8_GREG_W17 = DBGFREG_ARMV8_GREG_X17, 2083 DBGFREG_ARMV8_GREG_X18, 2084 DBGFREG_ARMV8_GREG_W18 = DBGFREG_ARMV8_GREG_X18, 2085 DBGFREG_ARMV8_GREG_X19, 2086 DBGFREG_ARMV8_GREG_W19 = DBGFREG_ARMV8_GREG_X19, 2087 DBGFREG_ARMV8_GREG_X20, 2088 DBGFREG_ARMV8_GREG_W20 = DBGFREG_ARMV8_GREG_X20, 2089 DBGFREG_ARMV8_GREG_X21, 2090 DBGFREG_ARMV8_GREG_W21 = DBGFREG_ARMV8_GREG_X21, 2091 DBGFREG_ARMV8_GREG_X22, 2092 DBGFREG_ARMV8_GREG_W22 = DBGFREG_ARMV8_GREG_X22, 2093 DBGFREG_ARMV8_GREG_X23, 2094 DBGFREG_ARMV8_GREG_W23 = DBGFREG_ARMV8_GREG_X23, 2095 DBGFREG_ARMV8_GREG_X24, 2096 DBGFREG_ARMV8_GREG_W24 = DBGFREG_ARMV8_GREG_X24, 2097 DBGFREG_ARMV8_GREG_X25, 2098 DBGFREG_ARMV8_GREG_W25 = DBGFREG_ARMV8_GREG_X25, 2099 DBGFREG_ARMV8_GREG_X26, 2100 DBGFREG_ARMV8_GREG_W26 = DBGFREG_ARMV8_GREG_X26, 2101 DBGFREG_ARMV8_GREG_X27, 2102 DBGFREG_ARMV8_GREG_W27 = DBGFREG_ARMV8_GREG_X27, 2103 DBGFREG_ARMV8_GREG_X28, 2104 DBGFREG_ARMV8_GREG_W28 = DBGFREG_ARMV8_GREG_X28, 2105 2106 DBGFREG_ARMV8_GREG_X29, 2107 DBGFREG_ARMV8_GREG_W29 = DBGFREG_ARMV8_GREG_X29, 2108 DBGFREG_ARMV8_GREG_FP = DBGFREG_ARMV8_GREG_X29, 2109 2110 DBGFREG_ARMV8_GREG_X30, 2111 DBGFREG_ARMV8_GREG_W30 = DBGFREG_ARMV8_GREG_X30, 2112 DBGFREG_ARMV8_GREG_LR = DBGFREG_ARMV8_GREG_X30, 2113 2114 DBGFREG_ARMV8_PC, 2115 2116 DBGFREG_ARMV8_VREG_V0, 2117 DBGFREG_ARMV8_VREG_V1, 2118 DBGFREG_ARMV8_VREG_V2, 2119 DBGFREG_ARMV8_VREG_V3, 2120 DBGFREG_ARMV8_VREG_V4, 2121 DBGFREG_ARMV8_VREG_V5, 2122 DBGFREG_ARMV8_VREG_V6, 2123 DBGFREG_ARMV8_VREG_V7, 2124 DBGFREG_ARMV8_VREG_V8, 2125 DBGFREG_ARMV8_VREG_V9, 2126 DBGFREG_ARMV8_VREG_V10, 2127 DBGFREG_ARMV8_VREG_V11, 2128 DBGFREG_ARMV8_VREG_V12, 2129 DBGFREG_ARMV8_VREG_V13, 2130 DBGFREG_ARMV8_VREG_V14, 2131 DBGFREG_ARMV8_VREG_V15, 2132 DBGFREG_ARMV8_VREG_V16, 2133 DBGFREG_ARMV8_VREG_V17, 2134 DBGFREG_ARMV8_VREG_V18, 2135 DBGFREG_ARMV8_VREG_V19, 2136 DBGFREG_ARMV8_VREG_V20, 2137 DBGFREG_ARMV8_VREG_V21, 2138 DBGFREG_ARMV8_VREG_V22, 2139 DBGFREG_ARMV8_VREG_V23, 2140 DBGFREG_ARMV8_VREG_V24, 2141 DBGFREG_ARMV8_VREG_V25, 2142 DBGFREG_ARMV8_VREG_V26, 2143 DBGFREG_ARMV8_VREG_V27, 2144 DBGFREG_ARMV8_VREG_V28, 2145 DBGFREG_ARMV8_VREG_V29, 2146 DBGFREG_ARMV8_VREG_V30, 2147 DBGFREG_ARMV8_VREG_V31, 2148 2149 DBGFREG_ARMV8_FPCR, 2150 DBGFREG_ARMV8_FPSR, 2151 2152 /** System registers: */ 2153 DBGFREG_ARMV8_SP_EL0, 2154 DBGFREG_ARMV8_SP_EL1, 2155 DBGFREG_ARMV8_SPSR_EL1, 2156 DBGFREG_ARMV8_SPSR_EL2, 2157 DBGFREG_ARMV8_PSTATE = DBGFREG_ARMV8_SPSR_EL2, 2158 DBGFREG_ARMV8_ELR_EL1, 2159 2160 DBGFREG_ARMV8_LAST = DBGFREG_ARMV8_ELR_EL1, 2161 /** @} */ 2162 2040 2163 /** The end of the registers. */ 2041 2164 DBGFREG_END, -
trunk/src/VBox/VMM/Makefile.kmk
r99051 r99070 349 349 VMMR3/CFGM.cpp \ 350 350 VMMR3/CPUM-armv8.cpp \ 351 VMMR3/CPUMDbg-armv8.cpp \ 351 352 VMMR3/DBGF.cpp \ 352 353 VMMR3/DBGFAddr.cpp \ -
trunk/src/VBox/VMM/VMMR3/CPUM-armv8.cpp
r99051 r99070 185 185 186 186 /** 187 * Initializes the debug aids of CPUM.188 *189 * @returns VBox status code.190 * @param pVM The cross context VM structure.191 */192 static int cpumR3DbgInit(PVM pVM)193 {194 RT_NOREF(pVM);195 /** @todo */196 return VINF_SUCCESS;197 }198 199 200 /**201 187 * Initializes the CPUM. 202 188 * -
trunk/src/VBox/VMM/VMMR3/DBGFReg.cpp
r98103 r99070 305 305 306 306 if (enmType == DBGFREGSETTYPE_CPU) 307 #if defined(VBOX_VMM_TARGET_ARMV8) 308 /** @todo This needs a general solution to avoid architecture dependent stuff here. */ 309 AssertMsgReturn(iDesc < (unsigned)DBGFREG_END, 310 ("%d iDesc=%d\n", paRegisters[iDesc].enmReg, iDesc), 311 VERR_INVALID_PARAMETER); 312 #else 307 313 AssertMsgReturn(iDesc < (unsigned)DBGFREG_END && (unsigned)paRegisters[iDesc].enmReg == iDesc, 308 314 ("%d iDesc=%d\n", paRegisters[iDesc].enmReg, iDesc), 309 315 VERR_INVALID_PARAMETER); 316 #endif 310 317 else 311 318 AssertReturn(paRegisters[iDesc].enmReg == DBGFREG_END, VERR_INVALID_PARAMETER); -
trunk/src/VBox/VMM/VMMR3/NEMR3Native-darwin-armv8.cpp
r99054 r99070 338 338 if (LogIs3Enabled()) 339 339 { 340 #if 0341 340 char szRegs[4096]; 342 341 DBGFR3RegPrintf(pVM->pUVM, pVCpu->idCpu, &szRegs[0], sizeof(szRegs), 343 "rax=%016VR{rax} rbx=%016VR{rbx} rcx=%016VR{rcx} rdx=%016VR{rdx}\n" 344 "rsi=%016VR{rsi} rdi=%016VR{rdi} r8 =%016VR{r8} r9 =%016VR{r9}\n" 345 "r10=%016VR{r10} r11=%016VR{r11} r12=%016VR{r12} r13=%016VR{r13}\n" 346 "r14=%016VR{r14} r15=%016VR{r15} %VRF{rflags}\n" 347 "rip=%016VR{rip} rsp=%016VR{rsp} rbp=%016VR{rbp}\n" 348 "cs={%04VR{cs} base=%016VR{cs_base} limit=%08VR{cs_lim} flags=%04VR{cs_attr}} cr0=%016VR{cr0}\n" 349 "ds={%04VR{ds} base=%016VR{ds_base} limit=%08VR{ds_lim} flags=%04VR{ds_attr}} cr2=%016VR{cr2}\n" 350 "es={%04VR{es} base=%016VR{es_base} limit=%08VR{es_lim} flags=%04VR{es_attr}} cr3=%016VR{cr3}\n" 351 "fs={%04VR{fs} base=%016VR{fs_base} limit=%08VR{fs_lim} flags=%04VR{fs_attr}} cr4=%016VR{cr4}\n" 352 "gs={%04VR{gs} base=%016VR{gs_base} limit=%08VR{gs_lim} flags=%04VR{gs_attr}} cr8=%016VR{cr8}\n" 353 "ss={%04VR{ss} base=%016VR{ss_base} limit=%08VR{ss_lim} flags=%04VR{ss_attr}}\n" 354 "dr0=%016VR{dr0} dr1=%016VR{dr1} dr2=%016VR{dr2} dr3=%016VR{dr3}\n" 355 "dr6=%016VR{dr6} dr7=%016VR{dr7}\n" 356 "gdtr=%016VR{gdtr_base}:%04VR{gdtr_lim} idtr=%016VR{idtr_base}:%04VR{idtr_lim} rflags=%08VR{rflags}\n" 357 "ldtr={%04VR{ldtr} base=%016VR{ldtr_base} limit=%08VR{ldtr_lim} flags=%08VR{ldtr_attr}}\n" 358 "tr ={%04VR{tr} base=%016VR{tr_base} limit=%08VR{tr_lim} flags=%08VR{tr_attr}}\n" 359 " sysenter={cs=%04VR{sysenter_cs} eip=%08VR{sysenter_eip} esp=%08VR{sysenter_esp}}\n" 360 " efer=%016VR{efer}\n" 361 " pat=%016VR{pat}\n" 362 " sf_mask=%016VR{sf_mask}\n" 363 "krnl_gs_base=%016VR{krnl_gs_base}\n" 364 " lstar=%016VR{lstar}\n" 365 " star=%016VR{star} cstar=%016VR{cstar}\n" 366 "fcw=%04VR{fcw} fsw=%04VR{fsw} ftw=%04VR{ftw} mxcsr=%04VR{mxcsr} mxcsr_mask=%04VR{mxcsr_mask}\n" 342 "x0=%016VR{x0} x1=%016VR{x1} x2=%016VR{x2} x3=%016VR{x3}\n" 343 "x4=%016VR{x4} x5=%016VR{x5} x6=%016VR{x6} x7=%016VR{x7}\n" 344 "x8=%016VR{x8} x9=%016VR{x9} x10=%016VR{x10} x11=%016VR{x11}\n" 345 "x12=%016VR{x12} x13=%016VR{x13} x14=%016VR{x14} x15=%016VR{x15}\n" 346 "x16=%016VR{x16} x17=%016VR{x17} x18=%016VR{x18} x19=%016VR{x19}\n" 347 "x20=%016VR{x20} x21=%016VR{x21} x22=%016VR{x22} x23=%016VR{x23}\n" 348 "x24=%016VR{x24} x25=%016VR{x25} x26=%016VR{x26} x27=%016VR{x27}\n" 349 "x28=%016VR{x28} x29=%016VR{x29} x30=%016VR{x30}\n" 350 "pc=%016VR{pc} pstate=%016VR{pstate}\n" 351 "sp_el0=%016VR{sp_el0} sp_el1=%016VR{sp_el1} elr_el1=%016VR{elr_el1}\n" 367 352 ); 368 369 char szInstr[256]; 353 char szInstr[256]; RT_ZERO(szInstr); 354 #if 0 370 355 DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, 0, 0, 371 356 DBGF_DISAS_FLAGS_CURRENT_GUEST | DBGF_DISAS_FLAGS_DEFAULT_MODE, 372 357 szInstr, sizeof(szInstr), NULL); 358 #endif 373 359 Log3(("%s%s\n", szRegs, szInstr)); 374 #else375 RT_NOREF(pVM, pVCpu);376 #endif377 360 } 378 361 } … … 832 815 return rc; 833 816 817 #ifdef LOG_ENABLED 818 if (LogIs3Enabled()) 819 nemR3DarwinLogState(pVM, pVCpu); 820 #endif 821 834 822 hv_vcpu_exit_t *pExit = pVCpu->nem.s.pHvExit; 835 823 switch (pExit->reason) -
trunk/src/VBox/VMM/include/CPUMInternal-armv8.h
r98970 r99070 123 123 RT_C_DECLS_BEGIN 124 124 125 # ifdef IN_RING3 126 DECLHIDDEN(int) cpumR3DbgInit(PVM pVM); 127 # endif 128 125 129 RT_C_DECLS_END 126 130 #endif /* !VBOX_FOR_DTRACE_LIB */
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