Changeset 99303 in vbox for trunk/src/VBox/VMM
- Timestamp:
- Apr 6, 2023 1:10:43 AM (22 months ago)
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
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trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsOneByte.cpp.h
r99298 r99303 1548 1548 1549 1549 /** 1550 * Common 'inc/dec/not/neg register' helper. 1551 */ 1552 FNIEMOP_DEF_2(iemOpCommonUnaryGReg, PCIEMOPUNARYSIZES, pImpl, uint8_t, iReg) 1553 { 1554 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 1555 switch (pVCpu->iem.s.enmEffOpSize) 1556 { 1557 case IEMMODE_16BIT: 1558 IEM_MC_BEGIN(2, 0); 1559 IEM_MC_ARG(uint16_t *, pu16Dst, 0); 1560 IEM_MC_ARG(uint32_t *, pEFlags, 1); 1561 IEM_MC_REF_GREG_U16(pu16Dst, iReg); 1562 IEM_MC_REF_EFLAGS(pEFlags); 1563 IEM_MC_CALL_VOID_AIMPL_2(pImpl->pfnNormalU16, pu16Dst, pEFlags); 1564 IEM_MC_ADVANCE_RIP_AND_FINISH(); 1565 IEM_MC_END(); 1566 break; 1567 1568 case IEMMODE_32BIT: 1569 IEM_MC_BEGIN(2, 0); 1570 IEM_MC_ARG(uint32_t *, pu32Dst, 0); 1571 IEM_MC_ARG(uint32_t *, pEFlags, 1); 1572 IEM_MC_REF_GREG_U32(pu32Dst, iReg); 1573 IEM_MC_REF_EFLAGS(pEFlags); 1574 IEM_MC_CALL_VOID_AIMPL_2(pImpl->pfnNormalU32, pu32Dst, pEFlags); 1575 IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pu32Dst); 1576 IEM_MC_ADVANCE_RIP_AND_FINISH(); 1577 IEM_MC_END(); 1578 break; 1579 1580 case IEMMODE_64BIT: 1581 IEM_MC_BEGIN(2, 0); 1582 IEM_MC_ARG(uint64_t *, pu64Dst, 0); 1583 IEM_MC_ARG(uint32_t *, pEFlags, 1); 1584 IEM_MC_REF_GREG_U64(pu64Dst, iReg); 1585 IEM_MC_REF_EFLAGS(pEFlags); 1586 IEM_MC_CALL_VOID_AIMPL_2(pImpl->pfnNormalU64, pu64Dst, pEFlags); 1587 IEM_MC_ADVANCE_RIP_AND_FINISH(); 1588 IEM_MC_END(); 1589 break; 1590 1591 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 1592 } 1593 } 1594 1550 * Common 'inc/dec register' helper. 1551 * 1552 * Not for 64-bit code, only for what became the rex prefixes. 1553 */ 1554 #define IEMOP_BODY_UNARY_GReg(a_fnNormalU16, a_fnNormalU32, a_iReg) \ 1555 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \ 1556 switch (pVCpu->iem.s.enmEffOpSize) \ 1557 { \ 1558 case IEMMODE_16BIT: \ 1559 IEM_MC_BEGIN(2, 0); \ 1560 IEM_MC_ARG(uint16_t *, pu16Dst, 0); \ 1561 IEM_MC_ARG(uint32_t *, pEFlags, 1); \ 1562 IEM_MC_REF_GREG_U16(pu16Dst, a_iReg); \ 1563 IEM_MC_REF_EFLAGS(pEFlags); \ 1564 IEM_MC_CALL_VOID_AIMPL_2(a_fnNormalU16, pu16Dst, pEFlags); \ 1565 IEM_MC_ADVANCE_RIP_AND_FINISH(); \ 1566 IEM_MC_END(); \ 1567 break; \ 1568 \ 1569 case IEMMODE_32BIT: \ 1570 IEM_MC_BEGIN(2, 0); \ 1571 IEM_MC_ARG(uint32_t *, pu32Dst, 0); \ 1572 IEM_MC_ARG(uint32_t *, pEFlags, 1); \ 1573 IEM_MC_REF_GREG_U32(pu32Dst, a_iReg); \ 1574 IEM_MC_REF_EFLAGS(pEFlags); \ 1575 IEM_MC_CALL_VOID_AIMPL_2(a_fnNormalU32, pu32Dst, pEFlags); \ 1576 IEM_MC_CLEAR_HIGH_GREG_U64_BY_REF(pu32Dst); \ 1577 IEM_MC_ADVANCE_RIP_AND_FINISH(); \ 1578 IEM_MC_END(); \ 1579 break; \ 1580 IEM_NOT_REACHED_DEFAULT_CASE_RET(); \ 1581 } \ 1582 (void)0 1595 1583 1596 1584 /** … … 1612 1600 1613 1601 IEMOP_MNEMONIC(inc_eAX, "inc eAX"); 1614 return FNIEMOP_CALL_2(iemOpCommonUnaryGReg, &g_iemAImpl_inc, X86_GREG_xAX);1602 IEMOP_BODY_UNARY_GReg(iemAImpl_inc_u16, iemAImpl_inc_u32, X86_GREG_xAX); 1615 1603 } 1616 1604 … … 1635 1623 1636 1624 IEMOP_MNEMONIC(inc_eCX, "inc eCX"); 1637 return FNIEMOP_CALL_2(iemOpCommonUnaryGReg, &g_iemAImpl_inc, X86_GREG_xCX);1625 IEMOP_BODY_UNARY_GReg(iemAImpl_inc_u16, iemAImpl_inc_u32, X86_GREG_xCX); 1638 1626 } 1639 1627 … … 1658 1646 1659 1647 IEMOP_MNEMONIC(inc_eDX, "inc eDX"); 1660 return FNIEMOP_CALL_2(iemOpCommonUnaryGReg, &g_iemAImpl_inc, X86_GREG_xDX);1648 IEMOP_BODY_UNARY_GReg(iemAImpl_inc_u16, iemAImpl_inc_u32, X86_GREG_xDX); 1661 1649 } 1662 1650 … … 1683 1671 1684 1672 IEMOP_MNEMONIC(inc_eBX, "inc eBX"); 1685 return FNIEMOP_CALL_2(iemOpCommonUnaryGReg, &g_iemAImpl_inc, X86_GREG_xBX);1673 IEMOP_BODY_UNARY_GReg(iemAImpl_inc_u16, iemAImpl_inc_u32, X86_GREG_xBX); 1686 1674 } 1687 1675 … … 1706 1694 1707 1695 IEMOP_MNEMONIC(inc_eSP, "inc eSP"); 1708 return FNIEMOP_CALL_2(iemOpCommonUnaryGReg, &g_iemAImpl_inc, X86_GREG_xSP);1696 IEMOP_BODY_UNARY_GReg(iemAImpl_inc_u16, iemAImpl_inc_u32, X86_GREG_xSP); 1709 1697 } 1710 1698 … … 1730 1718 1731 1719 IEMOP_MNEMONIC(inc_eBP, "inc eBP"); 1732 return FNIEMOP_CALL_2(iemOpCommonUnaryGReg, &g_iemAImpl_inc, X86_GREG_xBP);1720 IEMOP_BODY_UNARY_GReg(iemAImpl_inc_u16, iemAImpl_inc_u32, X86_GREG_xBP); 1733 1721 } 1734 1722 … … 1754 1742 1755 1743 IEMOP_MNEMONIC(inc_eSI, "inc eSI"); 1756 return FNIEMOP_CALL_2(iemOpCommonUnaryGReg, &g_iemAImpl_inc, X86_GREG_xSI);1744 IEMOP_BODY_UNARY_GReg(iemAImpl_inc_u16, iemAImpl_inc_u32, X86_GREG_xSI); 1757 1745 } 1758 1746 … … 1779 1767 1780 1768 IEMOP_MNEMONIC(inc_eDI, "inc eDI"); 1781 return FNIEMOP_CALL_2(iemOpCommonUnaryGReg, &g_iemAImpl_inc, X86_GREG_xDI);1769 IEMOP_BODY_UNARY_GReg(iemAImpl_inc_u16, iemAImpl_inc_u32, X86_GREG_xDI); 1782 1770 } 1783 1771 … … 1802 1790 1803 1791 IEMOP_MNEMONIC(dec_eAX, "dec eAX"); 1804 return FNIEMOP_CALL_2(iemOpCommonUnaryGReg, &g_iemAImpl_dec, X86_GREG_xAX);1792 IEMOP_BODY_UNARY_GReg(iemAImpl_dec_u16, iemAImpl_dec_u32, X86_GREG_xAX); 1805 1793 } 1806 1794 … … 1826 1814 1827 1815 IEMOP_MNEMONIC(dec_eCX, "dec eCX"); 1828 return FNIEMOP_CALL_2(iemOpCommonUnaryGReg, &g_iemAImpl_dec, X86_GREG_xCX);1816 IEMOP_BODY_UNARY_GReg(iemAImpl_dec_u16, iemAImpl_dec_u32, X86_GREG_xCX); 1829 1817 } 1830 1818 … … 1850 1838 1851 1839 IEMOP_MNEMONIC(dec_eDX, "dec eDX"); 1852 return FNIEMOP_CALL_2(iemOpCommonUnaryGReg, &g_iemAImpl_dec, X86_GREG_xDX);1840 IEMOP_BODY_UNARY_GReg(iemAImpl_dec_u16, iemAImpl_dec_u32, X86_GREG_xDX); 1853 1841 } 1854 1842 … … 1875 1863 1876 1864 IEMOP_MNEMONIC(dec_eBX, "dec eBX"); 1877 return FNIEMOP_CALL_2(iemOpCommonUnaryGReg, &g_iemAImpl_dec, X86_GREG_xBX);1865 IEMOP_BODY_UNARY_GReg(iemAImpl_dec_u16, iemAImpl_dec_u32, X86_GREG_xBX); 1878 1866 } 1879 1867 … … 1899 1887 1900 1888 IEMOP_MNEMONIC(dec_eSP, "dec eSP"); 1901 return FNIEMOP_CALL_2(iemOpCommonUnaryGReg, &g_iemAImpl_dec, X86_GREG_xSP);1889 IEMOP_BODY_UNARY_GReg(iemAImpl_dec_u16, iemAImpl_dec_u32, X86_GREG_xSP); 1902 1890 } 1903 1891 … … 1924 1912 1925 1913 IEMOP_MNEMONIC(dec_eBP, "dec eBP"); 1926 return FNIEMOP_CALL_2(iemOpCommonUnaryGReg, &g_iemAImpl_dec, X86_GREG_xBP);1914 IEMOP_BODY_UNARY_GReg(iemAImpl_dec_u16, iemAImpl_dec_u32, X86_GREG_xBP); 1927 1915 } 1928 1916 … … 1949 1937 1950 1938 IEMOP_MNEMONIC(dec_eSI, "dec eSI"); 1951 return FNIEMOP_CALL_2(iemOpCommonUnaryGReg, &g_iemAImpl_dec, X86_GREG_xSI);1939 IEMOP_BODY_UNARY_GReg(iemAImpl_dec_u16, iemAImpl_dec_u32, X86_GREG_xSI); 1952 1940 } 1953 1941 … … 1975 1963 1976 1964 IEMOP_MNEMONIC(dec_eDI, "dec eDI"); 1977 return FNIEMOP_CALL_2(iemOpCommonUnaryGReg, &g_iemAImpl_dec, X86_GREG_xDI);1965 IEMOP_BODY_UNARY_GReg(iemAImpl_dec_u16, iemAImpl_dec_u32, X86_GREG_xDI); 1978 1966 } 1979 1967 … … 11690 11678 11691 11679 /** 11692 * Common implementation of 'inc/dec/not/neg Ev'. 11693 * 11694 * @param bRm The RM byte. 11695 * @param pImpl The instruction implementation. 11696 */ 11697 FNIEMOP_DEF_2(iemOpCommonUnaryEv, uint8_t, bRm, PCIEMOPUNARYSIZES, pImpl) 11698 { 11699 /* Registers are handled by a common worker. */ 11700 if (IEM_IS_MODRM_REG_MODE(bRm)) 11701 return FNIEMOP_CALL_2(iemOpCommonUnaryGReg, pImpl, IEM_GET_MODRM_RM(pVCpu, bRm)); 11702 11703 /* Memory we do here. */ 11704 switch (pVCpu->iem.s.enmEffOpSize) 11705 { 11706 case IEMMODE_16BIT: 11707 IEM_MC_BEGIN(2, 2); 11708 IEM_MC_ARG(uint16_t *, pu16Dst, 0); 11709 IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 1); 11710 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst); 11711 11712 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0); 11713 IEM_MC_MEM_MAP(pu16Dst, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0 /*arg*/); 11714 IEM_MC_FETCH_EFLAGS(EFlags); 11715 if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK)) 11716 IEM_MC_CALL_VOID_AIMPL_2(pImpl->pfnNormalU16, pu16Dst, pEFlags); 11717 else 11718 IEM_MC_CALL_VOID_AIMPL_2(pImpl->pfnLockedU16, pu16Dst, pEFlags); 11719 11720 IEM_MC_MEM_COMMIT_AND_UNMAP(pu16Dst, IEM_ACCESS_DATA_RW); 11721 IEM_MC_COMMIT_EFLAGS(EFlags); 11722 IEM_MC_ADVANCE_RIP_AND_FINISH(); 11723 IEM_MC_END(); 11724 break; 11725 11726 case IEMMODE_32BIT: 11727 IEM_MC_BEGIN(2, 2); 11728 IEM_MC_ARG(uint32_t *, pu32Dst, 0); 11729 IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 1); 11730 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst); 11731 11732 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0); 11733 IEM_MC_MEM_MAP(pu32Dst, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0 /*arg*/); 11734 IEM_MC_FETCH_EFLAGS(EFlags); 11735 if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK)) 11736 IEM_MC_CALL_VOID_AIMPL_2(pImpl->pfnNormalU32, pu32Dst, pEFlags); 11737 else 11738 IEM_MC_CALL_VOID_AIMPL_2(pImpl->pfnLockedU32, pu32Dst, pEFlags); 11739 11740 IEM_MC_MEM_COMMIT_AND_UNMAP(pu32Dst, IEM_ACCESS_DATA_RW); 11741 IEM_MC_COMMIT_EFLAGS(EFlags); 11742 IEM_MC_ADVANCE_RIP_AND_FINISH(); 11743 IEM_MC_END(); 11744 break; 11745 11746 case IEMMODE_64BIT: 11747 IEM_MC_BEGIN(2, 2); 11748 IEM_MC_ARG(uint64_t *, pu64Dst, 0); 11749 IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 1); 11750 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst); 11751 11752 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0); 11753 IEM_MC_MEM_MAP(pu64Dst, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0 /*arg*/); 11754 IEM_MC_FETCH_EFLAGS(EFlags); 11755 if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK)) 11756 IEM_MC_CALL_VOID_AIMPL_2(pImpl->pfnNormalU64, pu64Dst, pEFlags); 11757 else 11758 IEM_MC_CALL_VOID_AIMPL_2(pImpl->pfnLockedU64, pu64Dst, pEFlags); 11759 11760 IEM_MC_MEM_COMMIT_AND_UNMAP(pu64Dst, IEM_ACCESS_DATA_RW); 11761 IEM_MC_COMMIT_EFLAGS(EFlags); 11762 IEM_MC_ADVANCE_RIP_AND_FINISH(); 11763 IEM_MC_END(); 11764 break; 11765 11766 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 11767 } 11768 } 11680 * Body for 'inc/dec/not/neg Ev' (groups 3 and 5). 11681 */ 11682 #define IEMOP_BODY_UNARY_Ev(a_fnNormalU16, a_fnNormalU32, a_fnNormalU64) \ 11683 if (IEM_IS_MODRM_REG_MODE(bRm)) \ 11684 { \ 11685 /* \ 11686 * Register target \ 11687 */ \ 11688 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); \ 11689 switch (pVCpu->iem.s.enmEffOpSize) \ 11690 { \ 11691 case IEMMODE_16BIT: \ 11692 IEM_MC_BEGIN(2, 0); \ 11693 IEM_MC_ARG(uint16_t *, pu16Dst, 0); \ 11694 IEM_MC_ARG(uint32_t *, pEFlags, 1); \ 11695 IEM_MC_REF_GREG_U16(pu16Dst, IEM_GET_MODRM_RM(pVCpu, bRm)); \ 11696 IEM_MC_REF_EFLAGS(pEFlags); \ 11697 IEM_MC_CALL_VOID_AIMPL_2(a_fnNormalU16, pu16Dst, pEFlags); \ 11698 IEM_MC_ADVANCE_RIP_AND_FINISH(); \ 11699 IEM_MC_END(); \ 11700 break; \ 11701 \ 11702 case IEMMODE_32BIT: \ 11703 IEM_MC_BEGIN(2, 0); \ 11704 IEM_MC_ARG(uint32_t *, pu32Dst, 0); \ 11705 IEM_MC_ARG(uint32_t *, pEFlags, 1); \ 11706 IEM_MC_REF_GREG_U32(pu32Dst, IEM_GET_MODRM_RM(pVCpu, bRm)); \ 11707 IEM_MC_REF_EFLAGS(pEFlags); \ 11708 IEM_MC_CALL_VOID_AIMPL_2(a_fnNormalU32, pu32Dst, pEFlags); \ 11709 IEM_MC_ADVANCE_RIP_AND_FINISH(); \ 11710 IEM_MC_END(); \ 11711 break; \ 11712 \ 11713 case IEMMODE_64BIT: \ 11714 IEM_MC_BEGIN(2, 0); \ 11715 IEM_MC_ARG(uint64_t *, pu64Dst, 0); \ 11716 IEM_MC_ARG(uint32_t *, pEFlags, 1); \ 11717 IEM_MC_REF_GREG_U64(pu64Dst, IEM_GET_MODRM_RM(pVCpu, bRm)); \ 11718 IEM_MC_REF_EFLAGS(pEFlags); \ 11719 IEM_MC_CALL_VOID_AIMPL_2(a_fnNormalU64, pu64Dst, pEFlags); \ 11720 IEM_MC_ADVANCE_RIP_AND_FINISH(); \ 11721 IEM_MC_END(); \ 11722 break; \ 11723 \ 11724 IEM_NOT_REACHED_DEFAULT_CASE_RET(); \ 11725 } \ 11726 } \ 11727 else \ 11728 { \ 11729 /* \ 11730 * Memory target. \ 11731 */ \ 11732 if (!(pVCpu->iem.s.fPrefixes & IEM_OP_PRF_LOCK)) \ 11733 { \ 11734 switch (pVCpu->iem.s.enmEffOpSize) \ 11735 { \ 11736 case IEMMODE_16BIT: \ 11737 IEM_MC_BEGIN(2, 2); \ 11738 IEM_MC_ARG(uint16_t *, pu16Dst, 0); \ 11739 IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 1); \ 11740 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst); \ 11741 \ 11742 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0); \ 11743 IEM_MC_MEM_MAP(pu16Dst, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0 /*arg*/); \ 11744 IEM_MC_FETCH_EFLAGS(EFlags); \ 11745 IEM_MC_CALL_VOID_AIMPL_2(a_fnNormalU16, pu16Dst, pEFlags); \ 11746 \ 11747 IEM_MC_MEM_COMMIT_AND_UNMAP(pu16Dst, IEM_ACCESS_DATA_RW); \ 11748 IEM_MC_COMMIT_EFLAGS(EFlags); \ 11749 IEM_MC_ADVANCE_RIP_AND_FINISH(); \ 11750 IEM_MC_END(); \ 11751 break; \ 11752 \ 11753 case IEMMODE_32BIT: \ 11754 IEM_MC_BEGIN(2, 2); \ 11755 IEM_MC_ARG(uint32_t *, pu32Dst, 0); \ 11756 IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 1); \ 11757 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst); \ 11758 \ 11759 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0); \ 11760 IEM_MC_MEM_MAP(pu32Dst, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0 /*arg*/); \ 11761 IEM_MC_FETCH_EFLAGS(EFlags); \ 11762 IEM_MC_CALL_VOID_AIMPL_2(a_fnNormalU32, pu32Dst, pEFlags); \ 11763 \ 11764 IEM_MC_MEM_COMMIT_AND_UNMAP(pu32Dst, IEM_ACCESS_DATA_RW); \ 11765 IEM_MC_COMMIT_EFLAGS(EFlags); \ 11766 IEM_MC_ADVANCE_RIP_AND_FINISH(); \ 11767 IEM_MC_END(); \ 11768 break; \ 11769 \ 11770 case IEMMODE_64BIT: \ 11771 IEM_MC_BEGIN(2, 2); \ 11772 IEM_MC_ARG(uint64_t *, pu64Dst, 0); \ 11773 IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 1); \ 11774 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst); \ 11775 \ 11776 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0); \ 11777 IEM_MC_MEM_MAP(pu64Dst, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0 /*arg*/); \ 11778 IEM_MC_FETCH_EFLAGS(EFlags); \ 11779 IEM_MC_CALL_VOID_AIMPL_2(a_fnNormalU64, pu64Dst, pEFlags); \ 11780 \ 11781 IEM_MC_MEM_COMMIT_AND_UNMAP(pu64Dst, IEM_ACCESS_DATA_RW); \ 11782 IEM_MC_COMMIT_EFLAGS(EFlags); \ 11783 IEM_MC_ADVANCE_RIP_AND_FINISH(); \ 11784 IEM_MC_END(); \ 11785 break; \ 11786 \ 11787 IEM_NOT_REACHED_DEFAULT_CASE_RET(); \ 11788 } \ 11789 } \ 11790 else \ 11791 { \ 11792 (void)0 11793 11794 #define IEMOP_BODY_UNARY_Ev_LOCKED(a_fnLockedU16, a_fnLockedU32, a_fnLockedU64) \ 11795 switch (pVCpu->iem.s.enmEffOpSize) \ 11796 { \ 11797 case IEMMODE_16BIT: \ 11798 IEM_MC_BEGIN(2, 2); \ 11799 IEM_MC_ARG(uint16_t *, pu16Dst, 0); \ 11800 IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 1); \ 11801 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst); \ 11802 \ 11803 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0); \ 11804 IEM_MC_MEM_MAP(pu16Dst, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0 /*arg*/); \ 11805 IEM_MC_FETCH_EFLAGS(EFlags); \ 11806 IEM_MC_CALL_VOID_AIMPL_2(a_fnLockedU16, pu16Dst, pEFlags); \ 11807 \ 11808 IEM_MC_MEM_COMMIT_AND_UNMAP(pu16Dst, IEM_ACCESS_DATA_RW); \ 11809 IEM_MC_COMMIT_EFLAGS(EFlags); \ 11810 IEM_MC_ADVANCE_RIP_AND_FINISH(); \ 11811 IEM_MC_END(); \ 11812 break; \ 11813 \ 11814 case IEMMODE_32BIT: \ 11815 IEM_MC_BEGIN(2, 2); \ 11816 IEM_MC_ARG(uint32_t *, pu32Dst, 0); \ 11817 IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 1); \ 11818 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst); \ 11819 \ 11820 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0); \ 11821 IEM_MC_MEM_MAP(pu32Dst, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0 /*arg*/); \ 11822 IEM_MC_FETCH_EFLAGS(EFlags); \ 11823 IEM_MC_CALL_VOID_AIMPL_2(a_fnLockedU32, pu32Dst, pEFlags); \ 11824 \ 11825 IEM_MC_MEM_COMMIT_AND_UNMAP(pu32Dst, IEM_ACCESS_DATA_RW); \ 11826 IEM_MC_COMMIT_EFLAGS(EFlags); \ 11827 IEM_MC_ADVANCE_RIP_AND_FINISH(); \ 11828 IEM_MC_END(); \ 11829 break; \ 11830 \ 11831 case IEMMODE_64BIT: \ 11832 IEM_MC_BEGIN(2, 2); \ 11833 IEM_MC_ARG(uint64_t *, pu64Dst, 0); \ 11834 IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 1); \ 11835 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst); \ 11836 \ 11837 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 0); \ 11838 IEM_MC_MEM_MAP(pu64Dst, IEM_ACCESS_DATA_RW, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0 /*arg*/); \ 11839 IEM_MC_FETCH_EFLAGS(EFlags); \ 11840 IEM_MC_CALL_VOID_AIMPL_2(a_fnLockedU64, pu64Dst, pEFlags); \ 11841 \ 11842 IEM_MC_MEM_COMMIT_AND_UNMAP(pu64Dst, IEM_ACCESS_DATA_RW); \ 11843 IEM_MC_COMMIT_EFLAGS(EFlags); \ 11844 IEM_MC_ADVANCE_RIP_AND_FINISH(); \ 11845 IEM_MC_END(); \ 11846 break; \ 11847 \ 11848 IEM_NOT_REACHED_DEFAULT_CASE_RET(); \ 11849 } \ 11850 } \ 11851 } \ 11852 (void)0 11769 11853 11770 11854 … … 11816 11900 IEM_MC_ADVANCE_RIP_AND_FINISH(); 11817 11901 IEM_MC_END(); 11818 }11819 }11820 11821 11822 /** Opcode 0xf7 /0. */11823 FNIEMOP_DEF_1(iemOp_grp3_test_Ev, uint8_t, bRm)11824 {11825 IEMOP_MNEMONIC(test_Ev_Iv, "test Ev,Iv");11826 IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_AF);11827 11828 if (IEM_IS_MODRM_REG_MODE(bRm))11829 {11830 /* register access */11831 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();11832 switch (pVCpu->iem.s.enmEffOpSize)11833 {11834 case IEMMODE_16BIT:11835 {11836 uint16_t u16Imm; IEM_OPCODE_GET_NEXT_U16(&u16Imm);11837 IEM_MC_BEGIN(3, 0);11838 IEM_MC_ARG(uint16_t *, pu16Dst, 0);11839 IEM_MC_ARG_CONST(uint16_t, u16Src,/*=*/u16Imm, 1);11840 IEM_MC_ARG(uint32_t *, pEFlags, 2);11841 IEM_MC_REF_GREG_U16(pu16Dst, IEM_GET_MODRM_RM(pVCpu, bRm));11842 IEM_MC_REF_EFLAGS(pEFlags);11843 IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_test_u16, pu16Dst, u16Src, pEFlags);11844 IEM_MC_ADVANCE_RIP_AND_FINISH();11845 IEM_MC_END();11846 break;11847 }11848 11849 case IEMMODE_32BIT:11850 {11851 uint32_t u32Imm; IEM_OPCODE_GET_NEXT_U32(&u32Imm);11852 IEM_MC_BEGIN(3, 0);11853 IEM_MC_ARG(uint32_t *, pu32Dst, 0);11854 IEM_MC_ARG_CONST(uint32_t, u32Src,/*=*/u32Imm, 1);11855 IEM_MC_ARG(uint32_t *, pEFlags, 2);11856 IEM_MC_REF_GREG_U32(pu32Dst, IEM_GET_MODRM_RM(pVCpu, bRm));11857 IEM_MC_REF_EFLAGS(pEFlags);11858 IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_test_u32, pu32Dst, u32Src, pEFlags);11859 /* No clearing the high dword here - test doesn't write back the result. */11860 IEM_MC_ADVANCE_RIP_AND_FINISH();11861 IEM_MC_END();11862 break;11863 }11864 11865 case IEMMODE_64BIT:11866 {11867 uint64_t u64Imm; IEM_OPCODE_GET_NEXT_S32_SX_U64(&u64Imm);11868 IEM_MC_BEGIN(3, 0);11869 IEM_MC_ARG(uint64_t *, pu64Dst, 0);11870 IEM_MC_ARG_CONST(uint64_t, u64Src,/*=*/u64Imm, 1);11871 IEM_MC_ARG(uint32_t *, pEFlags, 2);11872 IEM_MC_REF_GREG_U64(pu64Dst, IEM_GET_MODRM_RM(pVCpu, bRm));11873 IEM_MC_REF_EFLAGS(pEFlags);11874 IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_test_u64, pu64Dst, u64Src, pEFlags);11875 IEM_MC_ADVANCE_RIP_AND_FINISH();11876 IEM_MC_END();11877 break;11878 }11879 11880 IEM_NOT_REACHED_DEFAULT_CASE_RET();11881 }11882 }11883 else11884 {11885 /* memory access. */11886 switch (pVCpu->iem.s.enmEffOpSize)11887 {11888 case IEMMODE_16BIT:11889 {11890 IEM_MC_BEGIN(3, 2);11891 IEM_MC_ARG(uint16_t *, pu16Dst, 0);11892 IEM_MC_ARG(uint16_t, u16Src, 1);11893 IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 2);11894 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);11895 11896 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 2);11897 uint16_t u16Imm; IEM_OPCODE_GET_NEXT_U16(&u16Imm);11898 IEM_MC_ASSIGN(u16Src, u16Imm);11899 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();11900 IEM_MC_MEM_MAP(pu16Dst, IEM_ACCESS_DATA_R, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0 /*arg*/);11901 IEM_MC_FETCH_EFLAGS(EFlags);11902 IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_test_u16, pu16Dst, u16Src, pEFlags);11903 11904 IEM_MC_MEM_COMMIT_AND_UNMAP(pu16Dst, IEM_ACCESS_DATA_R);11905 IEM_MC_COMMIT_EFLAGS(EFlags);11906 IEM_MC_ADVANCE_RIP_AND_FINISH();11907 IEM_MC_END();11908 break;11909 }11910 11911 case IEMMODE_32BIT:11912 {11913 IEM_MC_BEGIN(3, 2);11914 IEM_MC_ARG(uint32_t *, pu32Dst, 0);11915 IEM_MC_ARG(uint32_t, u32Src, 1);11916 IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 2);11917 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);11918 11919 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 4);11920 uint32_t u32Imm; IEM_OPCODE_GET_NEXT_U32(&u32Imm);11921 IEM_MC_ASSIGN(u32Src, u32Imm);11922 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();11923 IEM_MC_MEM_MAP(pu32Dst, IEM_ACCESS_DATA_R, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0 /*arg*/);11924 IEM_MC_FETCH_EFLAGS(EFlags);11925 IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_test_u32, pu32Dst, u32Src, pEFlags);11926 11927 IEM_MC_MEM_COMMIT_AND_UNMAP(pu32Dst, IEM_ACCESS_DATA_R);11928 IEM_MC_COMMIT_EFLAGS(EFlags);11929 IEM_MC_ADVANCE_RIP_AND_FINISH();11930 IEM_MC_END();11931 break;11932 }11933 11934 case IEMMODE_64BIT:11935 {11936 IEM_MC_BEGIN(3, 2);11937 IEM_MC_ARG(uint64_t *, pu64Dst, 0);11938 IEM_MC_ARG(uint64_t, u64Src, 1);11939 IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 2);11940 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst);11941 11942 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 4);11943 uint64_t u64Imm; IEM_OPCODE_GET_NEXT_S32_SX_U64(&u64Imm);11944 IEM_MC_ASSIGN(u64Src, u64Imm);11945 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX();11946 IEM_MC_MEM_MAP(pu64Dst, IEM_ACCESS_DATA_R, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0 /*arg*/);11947 IEM_MC_FETCH_EFLAGS(EFlags);11948 IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_test_u64, pu64Dst, u64Src, pEFlags);11949 11950 IEM_MC_MEM_COMMIT_AND_UNMAP(pu64Dst, IEM_ACCESS_DATA_R);11951 IEM_MC_COMMIT_EFLAGS(EFlags);11952 IEM_MC_ADVANCE_RIP_AND_FINISH();11953 IEM_MC_END();11954 break;11955 }11956 11957 IEM_NOT_REACHED_DEFAULT_CASE_RET();11958 }11959 11902 } 11960 11903 } … … 12253 12196 12254 12197 12198 /** Opcode 0xf7 /0. */ 12199 FNIEMOP_DEF_1(iemOp_grp3_test_Ev, uint8_t, bRm) 12200 { 12201 IEMOP_MNEMONIC(test_Ev_Iv, "test Ev,Iv"); 12202 IEMOP_VERIFICATION_UNDEFINED_EFLAGS(X86_EFL_AF); 12203 12204 if (IEM_IS_MODRM_REG_MODE(bRm)) 12205 { 12206 /* register access */ 12207 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 12208 switch (pVCpu->iem.s.enmEffOpSize) 12209 { 12210 case IEMMODE_16BIT: 12211 { 12212 uint16_t u16Imm; IEM_OPCODE_GET_NEXT_U16(&u16Imm); 12213 IEM_MC_BEGIN(3, 0); 12214 IEM_MC_ARG(uint16_t *, pu16Dst, 0); 12215 IEM_MC_ARG_CONST(uint16_t, u16Src,/*=*/u16Imm, 1); 12216 IEM_MC_ARG(uint32_t *, pEFlags, 2); 12217 IEM_MC_REF_GREG_U16(pu16Dst, IEM_GET_MODRM_RM(pVCpu, bRm)); 12218 IEM_MC_REF_EFLAGS(pEFlags); 12219 IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_test_u16, pu16Dst, u16Src, pEFlags); 12220 IEM_MC_ADVANCE_RIP_AND_FINISH(); 12221 IEM_MC_END(); 12222 break; 12223 } 12224 12225 case IEMMODE_32BIT: 12226 { 12227 uint32_t u32Imm; IEM_OPCODE_GET_NEXT_U32(&u32Imm); 12228 IEM_MC_BEGIN(3, 0); 12229 IEM_MC_ARG(uint32_t *, pu32Dst, 0); 12230 IEM_MC_ARG_CONST(uint32_t, u32Src,/*=*/u32Imm, 1); 12231 IEM_MC_ARG(uint32_t *, pEFlags, 2); 12232 IEM_MC_REF_GREG_U32(pu32Dst, IEM_GET_MODRM_RM(pVCpu, bRm)); 12233 IEM_MC_REF_EFLAGS(pEFlags); 12234 IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_test_u32, pu32Dst, u32Src, pEFlags); 12235 /* No clearing the high dword here - test doesn't write back the result. */ 12236 IEM_MC_ADVANCE_RIP_AND_FINISH(); 12237 IEM_MC_END(); 12238 break; 12239 } 12240 12241 case IEMMODE_64BIT: 12242 { 12243 uint64_t u64Imm; IEM_OPCODE_GET_NEXT_S32_SX_U64(&u64Imm); 12244 IEM_MC_BEGIN(3, 0); 12245 IEM_MC_ARG(uint64_t *, pu64Dst, 0); 12246 IEM_MC_ARG_CONST(uint64_t, u64Src,/*=*/u64Imm, 1); 12247 IEM_MC_ARG(uint32_t *, pEFlags, 2); 12248 IEM_MC_REF_GREG_U64(pu64Dst, IEM_GET_MODRM_RM(pVCpu, bRm)); 12249 IEM_MC_REF_EFLAGS(pEFlags); 12250 IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_test_u64, pu64Dst, u64Src, pEFlags); 12251 IEM_MC_ADVANCE_RIP_AND_FINISH(); 12252 IEM_MC_END(); 12253 break; 12254 } 12255 12256 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 12257 } 12258 } 12259 else 12260 { 12261 /* memory access. */ 12262 switch (pVCpu->iem.s.enmEffOpSize) 12263 { 12264 case IEMMODE_16BIT: 12265 { 12266 IEM_MC_BEGIN(3, 2); 12267 IEM_MC_ARG(uint16_t *, pu16Dst, 0); 12268 IEM_MC_ARG(uint16_t, u16Src, 1); 12269 IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 2); 12270 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst); 12271 12272 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 2); 12273 uint16_t u16Imm; IEM_OPCODE_GET_NEXT_U16(&u16Imm); 12274 IEM_MC_ASSIGN(u16Src, u16Imm); 12275 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 12276 IEM_MC_MEM_MAP(pu16Dst, IEM_ACCESS_DATA_R, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0 /*arg*/); 12277 IEM_MC_FETCH_EFLAGS(EFlags); 12278 IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_test_u16, pu16Dst, u16Src, pEFlags); 12279 12280 IEM_MC_MEM_COMMIT_AND_UNMAP(pu16Dst, IEM_ACCESS_DATA_R); 12281 IEM_MC_COMMIT_EFLAGS(EFlags); 12282 IEM_MC_ADVANCE_RIP_AND_FINISH(); 12283 IEM_MC_END(); 12284 break; 12285 } 12286 12287 case IEMMODE_32BIT: 12288 { 12289 IEM_MC_BEGIN(3, 2); 12290 IEM_MC_ARG(uint32_t *, pu32Dst, 0); 12291 IEM_MC_ARG(uint32_t, u32Src, 1); 12292 IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 2); 12293 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst); 12294 12295 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 4); 12296 uint32_t u32Imm; IEM_OPCODE_GET_NEXT_U32(&u32Imm); 12297 IEM_MC_ASSIGN(u32Src, u32Imm); 12298 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 12299 IEM_MC_MEM_MAP(pu32Dst, IEM_ACCESS_DATA_R, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0 /*arg*/); 12300 IEM_MC_FETCH_EFLAGS(EFlags); 12301 IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_test_u32, pu32Dst, u32Src, pEFlags); 12302 12303 IEM_MC_MEM_COMMIT_AND_UNMAP(pu32Dst, IEM_ACCESS_DATA_R); 12304 IEM_MC_COMMIT_EFLAGS(EFlags); 12305 IEM_MC_ADVANCE_RIP_AND_FINISH(); 12306 IEM_MC_END(); 12307 break; 12308 } 12309 12310 case IEMMODE_64BIT: 12311 { 12312 IEM_MC_BEGIN(3, 2); 12313 IEM_MC_ARG(uint64_t *, pu64Dst, 0); 12314 IEM_MC_ARG(uint64_t, u64Src, 1); 12315 IEM_MC_ARG_LOCAL_EFLAGS( pEFlags, EFlags, 2); 12316 IEM_MC_LOCAL(RTGCPTR, GCPtrEffDst); 12317 12318 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffDst, bRm, 4); 12319 uint64_t u64Imm; IEM_OPCODE_GET_NEXT_S32_SX_U64(&u64Imm); 12320 IEM_MC_ASSIGN(u64Src, u64Imm); 12321 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX(); 12322 IEM_MC_MEM_MAP(pu64Dst, IEM_ACCESS_DATA_R, pVCpu->iem.s.iEffSeg, GCPtrEffDst, 0 /*arg*/); 12323 IEM_MC_FETCH_EFLAGS(EFlags); 12324 IEM_MC_CALL_VOID_AIMPL_3(iemAImpl_test_u64, pu64Dst, u64Src, pEFlags); 12325 12326 IEM_MC_MEM_COMMIT_AND_UNMAP(pu64Dst, IEM_ACCESS_DATA_R); 12327 IEM_MC_COMMIT_EFLAGS(EFlags); 12328 IEM_MC_ADVANCE_RIP_AND_FINISH(); 12329 IEM_MC_END(); 12330 break; 12331 } 12332 12333 IEM_NOT_REACHED_DEFAULT_CASE_RET(); 12334 } 12335 } 12336 } 12337 12338 12339 /** Opcode 0xf7 /2. */ 12340 FNIEMOP_DEF_1(iemOp_grp3_not_Ev, uint8_t, bRm) 12341 { 12342 IEMOP_MNEMONIC(not_Ev, "not Ev"); 12343 IEMOP_BODY_UNARY_Ev( iemAImpl_not_u16, iemAImpl_not_u32, iemAImpl_not_u64); 12344 IEMOP_BODY_UNARY_Ev_LOCKED(iemAImpl_not_u16_locked, iemAImpl_not_u32_locked, iemAImpl_not_u64_locked); 12345 } 12346 12347 12348 /** Opcode 0xf7 /3. */ 12349 FNIEMOP_DEF_1(iemOp_grp3_neg_Ev, uint8_t, bRm) 12350 { 12351 IEMOP_MNEMONIC(neg_Ev, "neg Ev"); 12352 IEMOP_BODY_UNARY_Ev( iemAImpl_neg_u16, iemAImpl_neg_u32, iemAImpl_neg_u64); 12353 IEMOP_BODY_UNARY_Ev_LOCKED(iemAImpl_neg_u16_locked, iemAImpl_neg_u32_locked, iemAImpl_neg_u64_locked); 12354 } 12355 12356 12255 12357 /** 12256 12358 * @opcode 0xf7 … … 12261 12363 switch (IEM_GET_MODRM_REG_8(bRm)) 12262 12364 { 12263 case 0: 12264 return FNIEMOP_CALL_1(iemOp_grp3_test_Ev, bRm); 12265 case 1: 12266 /** @todo testcase: Present on <=386, most 486 (not early), Pentiums, and current CPUs too. CPUUNDOC.EXE */ 12267 return IEMOP_RAISE_INVALID_OPCODE(); 12268 case 2: 12269 IEMOP_MNEMONIC(not_Ev, "not Ev"); 12270 return FNIEMOP_CALL_2(iemOpCommonUnaryEv, bRm, &g_iemAImpl_not); 12271 case 3: 12272 IEMOP_MNEMONIC(neg_Ev, "neg Ev"); 12273 return FNIEMOP_CALL_2(iemOpCommonUnaryEv, bRm, &g_iemAImpl_neg); 12365 case 0: return FNIEMOP_CALL_1(iemOp_grp3_test_Ev, bRm); 12366 case 1: return FNIEMOP_CALL_1(iemOp_grp3_test_Ev, bRm); 12367 case 2: return FNIEMOP_CALL_1(iemOp_grp3_not_Ev, bRm); 12368 case 3: return FNIEMOP_CALL_1(iemOp_grp3_neg_Ev, bRm); 12274 12369 case 4: 12275 12370 IEMOP_MNEMONIC(mul_Ev, "mul Ev"); … … 12407 12502 } 12408 12503 12504 /** Opcode 0xff /0. */ 12505 FNIEMOP_DEF_1(iemOp_Grp5_inc_Ev, uint8_t, bRm) 12506 { 12507 IEMOP_MNEMONIC(inc_Ev, "inc Ev"); 12508 IEMOP_BODY_UNARY_Ev( iemAImpl_inc_u16, iemAImpl_inc_u32, iemAImpl_inc_u64); 12509 IEMOP_BODY_UNARY_Ev_LOCKED(iemAImpl_inc_u16_locked, iemAImpl_inc_u32_locked, iemAImpl_inc_u64_locked); 12510 } 12511 12512 12513 /** Opcode 0xff /1. */ 12514 FNIEMOP_DEF_1(iemOp_Grp5_dec_Ev, uint8_t, bRm) 12515 { 12516 IEMOP_MNEMONIC(dec_Ev, "dec Ev"); 12517 IEMOP_BODY_UNARY_Ev( iemAImpl_dec_u16, iemAImpl_dec_u32, iemAImpl_dec_u64); 12518 IEMOP_BODY_UNARY_Ev_LOCKED(iemAImpl_dec_u16_locked, iemAImpl_dec_u32_locked, iemAImpl_dec_u64_locked); 12519 } 12520 12409 12521 12410 12522 /** … … 12733 12845 { 12734 12846 case 0: 12735 IEMOP_MNEMONIC(inc_Ev, "inc Ev"); 12736 return FNIEMOP_CALL_2(iemOpCommonUnaryEv, bRm, &g_iemAImpl_inc); 12847 return FNIEMOP_CALL_1(iemOp_Grp5_inc_Ev, bRm); 12737 12848 case 1: 12738 IEMOP_MNEMONIC(dec_Ev, "dec Ev"); 12739 return FNIEMOP_CALL_2(iemOpCommonUnaryEv, bRm, &g_iemAImpl_dec); 12849 return FNIEMOP_CALL_1(iemOp_Grp5_dec_Ev, bRm); 12740 12850 case 2: 12741 12851 return FNIEMOP_CALL_1(iemOp_Grp5_calln_Ev, bRm);
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