- Timestamp:
- Apr 7, 2023 10:10:07 AM (22 months ago)
- Location:
- trunk/src/VBox/Disassembler
- Files:
-
- 3 edited
-
DisasmCore-armv8.cpp (modified) (7 diffs)
-
DisasmInternal-armv8.h (modified) (4 diffs)
-
DisasmTables-armv8.cpp (modified) (11 diffs)
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/Disassembler/DisasmCore-armv8.cpp
r99319 r99334 79 79 static FNDISPARSEARMV8 disArmV8ParseHw; 80 80 static FNDISPARSEARMV8 disArmV8ParseCond; 81 static FNDISPARSEARMV8 disArmV8ParsePState; 81 82 /** @} */ 82 83 … … 85 86 * @{ */ 86 87 static FNDISDECODEARMV8 disArmV8DecodeIllegal; 88 static FNDISDECODEARMV8 disArmV8DecodeLookup; 87 89 /** @} */ 88 90 … … 101 103 disArmV8ParseImmsImmrN, 102 104 disArmV8ParseHw, 103 disArmV8ParseCond 105 disArmV8ParseCond, 106 disArmV8ParsePState, 104 107 }; 105 108 … … 109 112 { 110 113 disArmV8DecodeIllegal, 114 disArmV8DecodeLookup, 111 115 }; 112 116 … … 258 262 259 263 264 static int disArmV8ParsePState(PDISSTATE pDis, uint32_t u32Insn, PCDISARMV8INSNCLASS pInsnClass, PDISOPPARAM pParam, PCDISARMV8INSNPARAM pInsnParm, bool f64Bit) 265 { 266 RT_NOREF(pDis, u32Insn, pInsnClass, pParam, pInsnParm, f64Bit); 267 //AssertFailed(); 268 /** @todo */ 269 return VINF_SUCCESS; 270 } 271 272 260 273 static uint32_t disArmV8DecodeIllegal(PDISSTATE pDis, uint32_t u32Insn, PCDISARMV8INSNCLASS pInsnClass) 261 274 { … … 266 279 267 280 268 static int disArmV8A64ParseInstruction(PDISSTATE pDis, uint32_t u32Insn, PCDISOPCODE pOp, PCDISARMV8INSNCLASS pInsnClass) 281 static uint32_t disArmV8DecodeLookup(PDISSTATE pDis, uint32_t u32Insn, PCDISARMV8INSNCLASS pInsnClass) 282 { 283 RT_NOREF(pDis); 284 285 for (uint32_t i = 0; i < pInsnClass->Hdr.cDecode; i++) 286 { 287 PCDISARMV8OPCODE pOp = &pInsnClass->paOpcodes[i]; 288 if (u32Insn == pOp->fValue) 289 return i; 290 } 291 292 return UINT32_MAX; 293 } 294 295 296 static int disArmV8A64ParseInstruction(PDISSTATE pDis, uint32_t u32Insn, PCDISARMV8OPCODE pOp, PCDISARMV8INSNCLASS pInsnClass) 269 297 { 270 298 AssertPtr(pOp); 271 299 AssertPtr(pDis); 300 Assert((u32Insn & pOp->fMask) == pOp->fValue); 272 301 273 302 /* Should contain the parameter type on input. */ 274 pDis->Param1.arch.armv8.fParam = pOp-> fParam1;275 pDis->Param2.arch.armv8.fParam = pOp-> fParam2;276 pDis->Param3.arch.armv8.fParam = pOp-> fParam3;277 pDis->Param4.arch.armv8.fParam = pOp-> fParam4;278 279 pDis->pCurInstr = pOp;280 Assert( pOp!= &g_ArmV8A64InvalidOpcode[0]);303 pDis->Param1.arch.armv8.fParam = pOp->Opc.fParam1; 304 pDis->Param2.arch.armv8.fParam = pOp->Opc.fParam2; 305 pDis->Param3.arch.armv8.fParam = pOp->Opc.fParam3; 306 pDis->Param4.arch.armv8.fParam = pOp->Opc.fParam4; 307 308 pDis->pCurInstr = &pOp->Opc; 309 Assert(&pOp->Opc != &g_ArmV8A64InvalidOpcode[0]); 281 310 282 311 bool f64Bit = false; … … 369 398 370 399 /* Decode the opcode from the instruction class. */ 371 uint32_t uOpcRaw = (u32Insn & pInsnClass->fMask) >> pInsnClass->cShift; 372 if (pInsnClass->enmOpcDecode != kDisArmV8OpcDecodeNop) 373 uOpcRaw = g_apfnOpcDecode[pInsnClass->enmOpcDecode](pDis, u32Insn, pInsnClass); 400 uint32_t uOpcRaw = 0; 401 if (pInsnClass->Hdr.cDecode > 1) 402 { 403 uOpcRaw = (u32Insn & pInsnClass->fMask) >> pInsnClass->cShift; 404 if (pInsnClass->enmOpcDecode != kDisArmV8OpcDecodeNop) 405 uOpcRaw = g_apfnOpcDecode[pInsnClass->enmOpcDecode](pDis, uOpcRaw, pInsnClass); 406 } 374 407 375 408 if (uOpcRaw < pInsnClass->Hdr.cDecode) 376 409 { 377 PCDIS OPCODE pOp = &pInsnClass->paOpcodes[uOpcRaw];410 PCDISARMV8OPCODE pOp = &pInsnClass->paOpcodes[uOpcRaw]; 378 411 return disArmV8A64ParseInstruction(pDis, u32Insn, pOp, pInsnClass); 379 412 } -
trunk/src/VBox/Disassembler/DisasmInternal-armv8.h
r99320 r99334 58 58 kDisParmParseHw, 59 59 kDisParmParseCond, 60 kDisParmParsePState, 60 61 kDisParmParseMax 61 62 } DISPARMPARSEIDX; 62 63 /** @} */ 64 65 66 /** 67 * Opcode structure. 68 */ 69 typedef struct DISARMV8OPCODE 70 { 71 /** The mask defining the static bits of the opcode. */ 72 uint32_t fMask; 73 /** The value of masked bits of the isntruction. */ 74 uint32_t fValue; 75 /** The generic opcode structure. */ 76 DISOPCODE Opc; 77 } DISARMV8OPCODE; 78 /** Pointer to a const opcode. */ 79 typedef const DISARMV8OPCODE *PCDISARMV8OPCODE; 63 80 64 81 … … 86 103 { 87 104 kDisArmV8OpcDecodeNop = 0, 105 kDisArmV8OpcDecodeLookup, 88 106 kDisArmV8OpcDecodeMax 89 107 } DISARMV8OPCDECODE; … … 129 147 DISARMV8DECODEHDR Hdr; 130 148 /** Pointer to the arry of opcodes. */ 131 PCDIS OPCODEpaOpcodes;149 PCDISARMV8OPCODE paOpcodes; 132 150 /** Some flags for this instruction class. */ 133 151 uint32_t fClass; … … 153 171 154 172 #define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(a_Name) \ 155 static const DIS OPCODE a_Name ## Opcodes[] = {173 static const DISARMV8OPCODE a_Name ## Opcodes[] = { 156 174 #define DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS(a_Name, a_fClass, a_enmOpcDecode, a_fMask, a_cShift) \ 157 175 }; \ -
trunk/src/VBox/Disassembler/DisasmTables-armv8.cpp
r99319 r99334 39 39 *********************************************************************************************************************************/ 40 40 41 #define DIS_ARMV8_OP(a_ szOpcode, a_uOpcode, a_fOpType) \42 OP(a_szOpcode, 0, 0, 0, a_uOpcode, OP_ARMV8_PARM_NONE, OP_ARMV8_PARM_NONE, OP_ARMV8_PARM_NONE, a_fOpType)41 #define DIS_ARMV8_OP(a_fMask, a_fValue, a_szOpcode, a_uOpcode, a_fOpType) \ 42 { a_fMask, a_fValue, OP(a_szOpcode, 0, 0, 0, a_uOpcode, OP_ARMV8_PARM_NONE, OP_ARMV8_PARM_NONE, OP_ARMV8_PARM_NONE, a_fOpType) } 43 43 44 44 #ifndef DIS_CORE_ONLY … … 47 47 48 48 #define INVALID_OPCODE \ 49 DIS_ARMV8_OP( g_szInvalidOpcode, OP_ARMV8_INVALID, DISOPTYPE_INVALID)49 DIS_ARMV8_OP(0xffffffff, 0, g_szInvalidOpcode, OP_ARMV8_INVALID, DISOPTYPE_INVALID) 50 50 51 51 … … 53 53 DECL_HIDDEN_CONST(DISOPCODE) g_ArmV8A64InvalidOpcode[1] = 54 54 { 55 INVALID_OPCODE55 OP(g_szInvalidOpcode, 0, 0, 0, OP_ARMV8_INVALID, OP_ARMV8_PARM_NONE, OP_ARMV8_PARM_NONE, OP_ARMV8_PARM_NONE, DISOPTYPE_INVALID) 56 56 }; 57 57 … … 59 59 /* UDF */ 60 60 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(g_aArmV8A64InsnRsvd) 61 DIS_ARMV8_OP("udf %I" , OP_ARMV8_A64_UDF, DISOPTYPE_INVALID) 62 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS(g_aArmV8A64InsnRsvd, 0 /*fClass*/, kDisArmV8OpcDecodeNop, 0xffff0000, 16) 61 DIS_ARMV8_OP(0xffff0000, 0x00000000, "udf %I" , OP_ARMV8_A64_UDF, DISOPTYPE_INVALID) 62 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS(g_aArmV8A64InsnRsvd, 0 /*fClass*/, 63 kDisArmV8OpcDecodeNop, 0xffff0000, 16) 63 64 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseImm, 0, 16), 64 65 DIS_ARMV8_INSN_PARAM_NONE, … … 70 71 /* ADR/ADRP */ 71 72 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(g_ArmV8A64Adr) 72 DIS_ARMV8_OP("adr %X,%I" , OP_ARMV8_A64_ADR, DISOPTYPE_HARMLESS), 73 DIS_ARMV8_OP("adrp %X,%I" , OP_ARMV8_A64_ADRP, DISOPTYPE_HARMLESS) 74 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS(g_ArmV8A64Adr, DISARMV8INSNCLASS_F_FORCED_64BIT, kDisArmV8OpcDecodeNop, RT_BIT_32(31), 31) 73 DIS_ARMV8_OP(0x9f000000, 0x10000000, "adr %X,%I" , OP_ARMV8_A64_ADR, DISOPTYPE_HARMLESS), 74 DIS_ARMV8_OP(0x9f000000, 0x90000000, "adrp %X,%I" , OP_ARMV8_A64_ADRP, DISOPTYPE_HARMLESS) 75 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS(g_ArmV8A64Adr, DISARMV8INSNCLASS_F_FORCED_64BIT, 76 kDisArmV8OpcDecodeNop, RT_BIT_32(31), 31) 75 77 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 0, 5), 76 78 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseImmAdr, 0, 0), … … 82 84 /* ADD/ADDS/SUB/SUBS */ 83 85 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(g_ArmV8A64AddSubImm) 84 DIS_ARMV8_OP("add %X,%X,%I" , OP_ARMV8_A64_ADD, DISOPTYPE_HARMLESS), 85 DIS_ARMV8_OP("adds %X,%X,%I" , OP_ARMV8_A64_ADDS, DISOPTYPE_HARMLESS), 86 DIS_ARMV8_OP("sub %X,%X,%I" , OP_ARMV8_A64_SUB, DISOPTYPE_HARMLESS), 87 DIS_ARMV8_OP("subs %X,%X,%I" , OP_ARMV8_A64_SUBS, DISOPTYPE_HARMLESS), 88 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS(g_ArmV8A64AddSubImm, DISARMV8INSNCLASS_F_SF, kDisArmV8OpcDecodeNop, RT_BIT_32(29) | RT_BIT_32(30), 29) 86 DIS_ARMV8_OP(0x7f800000, 0x11000000, "add %X,%X,%I" , OP_ARMV8_A64_ADD, DISOPTYPE_HARMLESS), 87 DIS_ARMV8_OP(0x7f800000, 0x31000000, "adds %X,%X,%I" , OP_ARMV8_A64_ADDS, DISOPTYPE_HARMLESS), 88 DIS_ARMV8_OP(0x7f800000, 0x51000000, "sub %X,%X,%I" , OP_ARMV8_A64_SUB, DISOPTYPE_HARMLESS), 89 DIS_ARMV8_OP(0x7f800000, 0x71000000, "subs %X,%X,%I" , OP_ARMV8_A64_SUBS, DISOPTYPE_HARMLESS), 90 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS(g_ArmV8A64AddSubImm, DISARMV8INSNCLASS_F_SF, 91 kDisArmV8OpcDecodeNop, RT_BIT_32(29) | RT_BIT_32(30), 29) 89 92 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 0, 5), 90 93 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 5, 5), … … 96 99 /* AND/ORR/EOR/ANDS */ 97 100 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(g_ArmV8A64LogicalImm) 98 DIS_ARMV8_OP("and %X,%X,%I" , OP_ARMV8_A64_AND, DISOPTYPE_HARMLESS), 99 DIS_ARMV8_OP("orr %X,%X,%I" , OP_ARMV8_A64_ORR, DISOPTYPE_HARMLESS), 100 DIS_ARMV8_OP("eor %X,%X,%I" , OP_ARMV8_A64_EOR, DISOPTYPE_HARMLESS), 101 DIS_ARMV8_OP("ands %X,%X,%I" , OP_ARMV8_A64_ANDS, DISOPTYPE_HARMLESS), 102 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS(g_ArmV8A64LogicalImm, DISARMV8INSNCLASS_F_SF, kDisArmV8OpcDecodeNop, RT_BIT_32(29) | RT_BIT_32(30), 29) 101 DIS_ARMV8_OP(0x7f800000, 0x12000000, "and %X,%X,%I" , OP_ARMV8_A64_AND, DISOPTYPE_HARMLESS), 102 DIS_ARMV8_OP(0x7f800000, 0x32000000, "orr %X,%X,%I" , OP_ARMV8_A64_ORR, DISOPTYPE_HARMLESS), 103 DIS_ARMV8_OP(0x7f800000, 0x52000000, "eor %X,%X,%I" , OP_ARMV8_A64_EOR, DISOPTYPE_HARMLESS), 104 DIS_ARMV8_OP(0x7f800000, 0x72000000, "ands %X,%X,%I" , OP_ARMV8_A64_ANDS, DISOPTYPE_HARMLESS), 105 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS(g_ArmV8A64LogicalImm, DISARMV8INSNCLASS_F_SF, 106 kDisArmV8OpcDecodeNop, RT_BIT_32(29) | RT_BIT_32(30), 29) 103 107 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 0, 5), 104 108 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 5, 6), … … 110 114 /* MOVN/MOVZ/MOVK */ 111 115 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(g_ArmV8A64MoveWide) 112 DIS_ARMV8_OP( "movn %X,%I LSL %I", OP_ARMV8_A64_MOVN,DISOPTYPE_HARMLESS),116 DIS_ARMV8_OP(0x7f800000, 0x12800000, "movn %X,%I LSL %I", OP_ARMV8_A64_MOVN, DISOPTYPE_HARMLESS), 113 117 INVALID_OPCODE, 114 DIS_ARMV8_OP("movz %X,%I LSL %I" , OP_ARMV8_A64_MOVZ, DISOPTYPE_HARMLESS), 115 DIS_ARMV8_OP("movk %X,%I LSL %I" , OP_ARMV8_A64_MOVK, DISOPTYPE_HARMLESS), 116 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS(g_ArmV8A64MoveWide, DISARMV8INSNCLASS_F_SF, kDisArmV8OpcDecodeNop, RT_BIT_32(29) | RT_BIT_32(30), 29) 118 DIS_ARMV8_OP(0x7f800000, 0x52800000, "movz %X,%I LSL %I" , OP_ARMV8_A64_MOVZ, DISOPTYPE_HARMLESS), 119 DIS_ARMV8_OP(0x7f800000, 0x72800000, "movk %X,%I LSL %I" , OP_ARMV8_A64_MOVK, DISOPTYPE_HARMLESS), 120 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS(g_ArmV8A64MoveWide, DISARMV8INSNCLASS_F_SF, 121 kDisArmV8OpcDecodeNop, RT_BIT_32(29) | RT_BIT_32(30), 29) 117 122 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 0, 5), 118 123 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseImm, 5, 16), … … 124 129 /* SBFM/BFM/UBFM */ 125 130 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(g_ArmV8A64Bitfield) 126 DIS_ARMV8_OP( "sbfm %X,%X,%I", OP_ARMV8_A64_SBFM,DISOPTYPE_HARMLESS),127 DIS_ARMV8_OP( "bfm %X,%X,%I" , OP_ARMV8_A64_BFM,DISOPTYPE_HARMLESS),128 DIS_ARMV8_OP( "ubfm %X,%X,%I" , OP_ARMV8_A64_UBFM,DISOPTYPE_HARMLESS),131 DIS_ARMV8_OP(0x7f800000, 0x13000000, "sbfm %X,%X,%I", OP_ARMV8_A64_SBFM, DISOPTYPE_HARMLESS), 132 DIS_ARMV8_OP(0x7f800000, 0x33000000, "bfm %X,%X,%I", OP_ARMV8_A64_BFM, DISOPTYPE_HARMLESS), 133 DIS_ARMV8_OP(0x7f800000, 0x23000000, "ubfm %X,%X,%I", OP_ARMV8_A64_UBFM, DISOPTYPE_HARMLESS), 129 134 INVALID_OPCODE, 130 135 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS(g_ArmV8A64Bitfield, DISARMV8INSNCLASS_F_SF | DISARMV8INSNCLASS_F_N_FORCED_1_ON_64BIT, … … 165 170 /* B.cond/BC.cond */ 166 171 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(g_ArmV8A64CondBr) 167 DIS_ARMV8_OP( "b.%C %J",OP_ARMV8_A64_B, DISOPTYPE_HARMLESS | DISOPTYPE_CONTROLFLOW | DISOPTYPE_RELATIVE_CONTROLFLOW | DISOPTYPE_COND_CONTROLFLOW),168 DIS_ARMV8_OP( "bc.%C %J" ,OP_ARMV8_A64_BC, DISOPTYPE_HARMLESS | DISOPTYPE_CONTROLFLOW | DISOPTYPE_RELATIVE_CONTROLFLOW | DISOPTYPE_COND_CONTROLFLOW),172 DIS_ARMV8_OP(0xff000010, 0x54000000, "b.%C %J", OP_ARMV8_A64_B, DISOPTYPE_HARMLESS | DISOPTYPE_CONTROLFLOW | DISOPTYPE_RELATIVE_CONTROLFLOW | DISOPTYPE_COND_CONTROLFLOW), 173 DIS_ARMV8_OP(0xff000010, 0x54000010, "bc.%C %J" , OP_ARMV8_A64_BC, DISOPTYPE_HARMLESS | DISOPTYPE_CONTROLFLOW | DISOPTYPE_RELATIVE_CONTROLFLOW | DISOPTYPE_COND_CONTROLFLOW), 169 174 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS(g_ArmV8A64CondBr, 0 /*fClass*/, 170 175 kDisArmV8OpcDecodeNop, RT_BIT_32(4), 4) … … 176 181 177 182 183 /* SVC/HVC/SMC/BRK/HLT/TCANCEL/DCPS1/DCPS2/DCPS3 */ 184 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(g_ArmV8A64Excp) 185 DIS_ARMV8_OP(0xffe0001f, 0xd4000001, "svc %I", OP_ARMV8_A64_SVC, DISOPTYPE_CONTROLFLOW | DISOPTYPE_INTERRUPT), 186 DIS_ARMV8_OP(0xffe0001f, 0xd4000002, "hvc %I", OP_ARMV8_A64_HVC, DISOPTYPE_CONTROLFLOW | DISOPTYPE_INTERRUPT | DISOPTYPE_PRIVILEGED), 187 DIS_ARMV8_OP(0xffe0001f, 0xd4000003, "smc %I", OP_ARMV8_A64_SMC, DISOPTYPE_CONTROLFLOW | DISOPTYPE_INTERRUPT | DISOPTYPE_PRIVILEGED), 188 DIS_ARMV8_OP(0xffe0001f, 0xd4200000, "brk %I", OP_ARMV8_A64_BRK, DISOPTYPE_CONTROLFLOW | DISOPTYPE_INTERRUPT), 189 DIS_ARMV8_OP(0xffe0001f, 0xd4400000, "hlt %I", OP_ARMV8_A64_HLT, DISOPTYPE_CONTROLFLOW | DISOPTYPE_INTERRUPT), 190 DIS_ARMV8_OP(0xffe0001f, 0xd4600000, "tcancel %I", OP_ARMV8_A64_TCANCEL, DISOPTYPE_CONTROLFLOW | DISOPTYPE_INTERRUPT), /* FEAT_TME */ 191 DIS_ARMV8_OP(0xffe0001f, 0xd4a00001, "dcps1 %I", OP_ARMV8_A64_DCPS1, DISOPTYPE_CONTROLFLOW | DISOPTYPE_INTERRUPT), 192 DIS_ARMV8_OP(0xffe0001f, 0xd4a00002, "dcps2 %I", OP_ARMV8_A64_DCPS2, DISOPTYPE_CONTROLFLOW | DISOPTYPE_INTERRUPT), 193 DIS_ARMV8_OP(0xffe0001f, 0xd4a00003, "dcps3 %I", OP_ARMV8_A64_DCPS3, DISOPTYPE_CONTROLFLOW | DISOPTYPE_INTERRUPT), 194 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS(g_ArmV8A64Excp, 0 /*fClass*/, 195 kDisArmV8OpcDecodeLookup, 0xffe0001f, 0) 196 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseImm, 5, 16), 197 DIS_ARMV8_INSN_PARAM_NONE, 198 DIS_ARMV8_INSN_PARAM_NONE, 199 DIS_ARMV8_INSN_PARAM_NONE 200 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END; 201 202 203 /* WFET/WFIT */ 204 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(g_ArmV8A64SysReg) 205 DIS_ARMV8_OP(0xffffffe0, 0xd5031000, "wfet %X", OP_ARMV8_A64_WFET, DISOPTYPE_HARMLESS), /* FEAT_WFxT */ 206 DIS_ARMV8_OP(0xffffffe0, 0x54000010, "wfit %X" , OP_ARMV8_A64_WFIT, DISOPTYPE_HARMLESS), /* FEAT_WFxT */ 207 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS(g_ArmV8A64SysReg, DISARMV8INSNCLASS_F_FORCED_64BIT, 208 kDisArmV8OpcDecodeNop, 0xfe0, 5) 209 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 0, 5), 210 DIS_ARMV8_INSN_PARAM_NONE, 211 DIS_ARMV8_INSN_PARAM_NONE, 212 DIS_ARMV8_INSN_PARAM_NONE 213 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END; 214 215 216 /* Various hint instructions */ 217 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(g_ArmV8A64Hints) 218 DIS_ARMV8_OP(0xffffffff, 0xd503201f, "nop", OP_ARMV8_A64_NOP, DISOPTYPE_HARMLESS), 219 DIS_ARMV8_OP(0xffffffff, 0xd503203f, "yield", OP_ARMV8_A64_YIELD, DISOPTYPE_HARMLESS), 220 DIS_ARMV8_OP(0xffffffff, 0xd503205f, "wfe", OP_ARMV8_A64_WFE, DISOPTYPE_HARMLESS), 221 DIS_ARMV8_OP(0xffffffff, 0xd503207f, "wfi", OP_ARMV8_A64_WFI, DISOPTYPE_HARMLESS), 222 DIS_ARMV8_OP(0xffffffff, 0xd503209f, "sev", OP_ARMV8_A64_SEV, DISOPTYPE_HARMLESS), 223 DIS_ARMV8_OP(0xffffffff, 0xd50320bf, "sevl", OP_ARMV8_A64_SEVL, DISOPTYPE_HARMLESS), 224 DIS_ARMV8_OP(0xffffffff, 0xd50320df, "dgh", OP_ARMV8_A64_DGH, DISOPTYPE_HARMLESS), /* FEAT_DGH */ 225 DIS_ARMV8_OP(0xffffffff, 0xd50320ff, "xpaclri", OP_ARMV8_A64_XPACLRI, DISOPTYPE_HARMLESS), /* FEAT_PAuth */ 226 /** @todo */ 227 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS(g_ArmV8A64Hints, 0 /*fClass*/, 228 kDisArmV8OpcDecodeNop, 0xfe0, 5) 229 DIS_ARMV8_INSN_PARAM_NONE, 230 DIS_ARMV8_INSN_PARAM_NONE, 231 DIS_ARMV8_INSN_PARAM_NONE, 232 DIS_ARMV8_INSN_PARAM_NONE 233 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END; 234 235 236 /* CLREX */ 237 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(g_ArmV8A64Clrex) 238 DIS_ARMV8_OP(0xfffff0ff, 0xd503305f, "clrex %I", OP_ARMV8_A64_CLREX, DISOPTYPE_HARMLESS), 239 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS(g_ArmV8A64Clrex, 0 /*fClass*/, 240 kDisArmV8OpcDecodeNop, 0, 0) 241 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseImm, 8, 4), 242 DIS_ARMV8_INSN_PARAM_NONE, 243 DIS_ARMV8_INSN_PARAM_NONE, 244 DIS_ARMV8_INSN_PARAM_NONE 245 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END; 246 247 248 /* Barrier instructions, we divide these instructions further based on the op2 field. */ 249 DIS_ARMV8_DECODE_MAP_DEFINE_BEGIN(g_ArmV8A64DecodeBarriers) 250 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, 251 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo DSB - Encoding */ 252 DIS_ARMV8_DECODE_MAP_ENTRY(g_ArmV8A64Clrex), /* CLREX */ 253 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo TCOMMIT */ 254 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo DSB - Encoding */ 255 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo DMB */ 256 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY, /** @todo ISB */ 257 DIS_ARMV8_DECODE_MAP_INVALID_ENTRY /** @todo SB */ 258 DIS_ARMV8_DECODE_MAP_DEFINE_END(g_ArmV8A64DecodeBarriers, RT_BIT_32(5) | RT_BIT_32(6) | RT_BIT_32(7), 5); 259 260 261 /* MSR (and potentially CFINV,XAFLAG,AXFLAG) */ 262 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(g_ArmV8A64PState) 263 DIS_ARMV8_OP(0xfffff0ff, 0xd503305f, "msr %P, %I", OP_ARMV8_A64_MSR, DISOPTYPE_PRIVILEGED), 264 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS(g_ArmV8A64PState, 0 /*fClass*/, 265 kDisArmV8OpcDecodeNop, 0, 0) 266 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParsePState, 0, 0), /* This is special for the MSR instruction. */ 267 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseImm, 8, 4), /* CRm field encodes the immediate value */ 268 DIS_ARMV8_INSN_PARAM_NONE, 269 DIS_ARMV8_INSN_PARAM_NONE 270 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END; 271 272 273 /* TSTART/TTEST */ 274 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_BEGIN(g_ArmV8A64SysResult) 275 DIS_ARMV8_OP(0xfffffffe, 0xd5233060, "tstart %X", OP_ARMV8_A64_TSTART, DISOPTYPE_HARMLESS | DISOPTYPE_PRIVILEGED), /* FEAT_TME */ 276 DIS_ARMV8_OP(0xfffffffe, 0xd5233160, "ttest %X", OP_ARMV8_A64_TTEST, DISOPTYPE_HARMLESS), /* FEAT_TME */ 277 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_PARAMS(g_ArmV8A64SysResult, DISARMV8INSNCLASS_F_FORCED_64BIT, 278 kDisArmV8OpcDecodeNop, RT_BIT_32(8) | RT_BIT_32(9) | RT_BIT_32(10) | RT_BIT_32(11), 8) 279 DIS_ARMV8_INSN_PARAM_CREATE(kDisParmParseReg, 0, 5), 280 DIS_ARMV8_INSN_PARAM_NONE, 281 DIS_ARMV8_INSN_PARAM_NONE, 282 DIS_ARMV8_INSN_PARAM_NONE 283 DIS_ARMV8_DECODE_INSN_CLASS_DEFINE_END; 284 285 178 286 DIS_ARMV8_DECODE_TBL_DEFINE_BEGIN(g_ArmV8A64BrExcpSys) 179 DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xff000000, RT_BIT_32(26) | RT_BIT_32(28) | RT_BIT_32(30), g_ArmV8A64CondBr) /* op0: 010, op1: 0xxxxxxxxxxxxx, op2: - (including o1 from the conditional branch (immediate) class to save us one layer). */ 287 DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfe000000, RT_BIT_32(26) | RT_BIT_32(28) | RT_BIT_32(30), g_ArmV8A64CondBr), /* op0: 010, op1: 0xxxxxxxxxxxxx, op2: - (including o1 from the conditional branch (immediate) class to save us one layer). */ 288 DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xff000000, RT_BIT_32(26) | RT_BIT_32(28) | RT_BIT_32(30) | RT_BIT_32(31), g_ArmV8A64Excp), /* op0: 110, op1: 00xxxxxxxxxxxx, op2: -. */ 289 DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfffff000, 0xd5031000, g_ArmV8A64SysReg), /* op0: 110, op1: 01000000110001, op2: -. */ 290 DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfffff01f, 0xd503201f, g_ArmV8A64Hints), /* op0: 110, op1: 01000000110010, op2: 11111. */ 291 DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfffff01f, 0xd503301f, g_ArmV8A64DecodeBarriers), /* op0: 110, op1: 01000000110011, op2: - (we include Rt: 11111 from the next stage here). */ 292 DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfff8f01f, 0xd500401f, g_ArmV8A64PState), /* op0: 110, op1: 0100000xxx0100, op2: - (we include Rt: 11111 from the next stage here). */ 293 DIS_ARMV8_DECODE_TBL_ENTRY_INIT(0xfffff0e0, 0xd5233060, g_ArmV8A64SysResult) /* op0: 110, op1: 0100100xxxxxxx, op2: - (we include op1, CRn and op2 from the next stage here). */ 180 294 DIS_ARMV8_DECODE_TBL_DEFINE_END(g_ArmV8A64BrExcpSys); 181 295
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