- Timestamp:
- Apr 7, 2023 12:40:01 PM (22 months ago)
- Location:
- trunk/src/VBox/VMM
- Files:
-
- 5 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsPython.py
r99339 r99340 2661 2661 'IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT': McBlock.parseMcGeneric, 2662 2662 'IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT': McBlock.parseMcGeneric, 2663 'IEM_MC_MAYBE_RAISE_SSE42_RELATED_XCPT': McBlock.parseMcGeneric,2664 2663 'IEM_MC_MAYBE_RAISE_WAIT_DEVICE_NOT_AVAILABLE': McBlock.parseMcGeneric, 2665 2664 'IEM_MC_MEM_COMMIT_AND_UNMAP': McBlock.parseMcGeneric, -
trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsThree0f38.cpp.h
r99339 r99340 286 286 IEM_MC_ARG(PRTUINT128U, puDst, 0); 287 287 IEM_MC_ARG(PCRTUINT128U, puSrc, 1); 288 IEM_MC_MAYBE_RAISE_SSE 42_RELATED_XCPT();288 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT(); 289 289 IEM_MC_PREPARE_SSE_USAGE(); 290 290 IEM_MC_REF_XREG_U128(puDst, IEM_GET_MODRM_REG(pVCpu, bRm)); … … 307 307 IEM_MC_CALC_RM_EFF_ADDR(GCPtrEffSrc, bRm, 0); 308 308 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse42); 309 IEM_MC_MAYBE_RAISE_SSE 42_RELATED_XCPT();309 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT(); 310 310 IEM_MC_FETCH_MEM_U128_ALIGN_SSE(uSrc, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); 311 311 -
trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsThree0f3a.cpp.h
r99339 r99340 1154 1154 IEM_MC_ARG_LOCAL_REF(PIEMPCMPESTRXSRC, pSrc, Src, 2); 1155 1155 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3); 1156 IEM_MC_MAYBE_RAISE_SSE 42_RELATED_XCPT();1156 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT(); 1157 1157 IEM_MC_PREPARE_SSE_USAGE(); 1158 1158 IEM_MC_FETCH_XREG_U128(Src.uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm)); … … 1185 1185 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3); 1186 1186 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse42); 1187 IEM_MC_MAYBE_RAISE_SSE 42_RELATED_XCPT();1187 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT(); 1188 1188 IEM_MC_FETCH_MEM_U128(Src.uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); 1189 1189 … … 1218 1218 IEM_MC_ARG_LOCAL_REF(PIEMPCMPESTRXSRC, pSrc, Src, 2); 1219 1219 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3); 1220 IEM_MC_MAYBE_RAISE_SSE 42_RELATED_XCPT();1220 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT(); 1221 1221 IEM_MC_PREPARE_SSE_USAGE(); 1222 1222 IEM_MC_FETCH_XREG_U128(Src.uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm)); … … 1249 1249 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3); 1250 1250 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse42); 1251 IEM_MC_MAYBE_RAISE_SSE 42_RELATED_XCPT();1251 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT(); 1252 1252 IEM_MC_FETCH_MEM_U128(Src.uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); 1253 1253 … … 1290 1290 IEM_MC_ARG_LOCAL_REF(PIEMPCMPESTRXSRC, pSrc, Src, 2); 1291 1291 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3); 1292 IEM_MC_MAYBE_RAISE_SSE 42_RELATED_XCPT();1292 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT(); 1293 1293 IEM_MC_PREPARE_SSE_USAGE(); 1294 1294 IEM_MC_REF_GREG_U32(pu32Ecx, X86_GREG_xCX); … … 1322 1322 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3); 1323 1323 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse42); 1324 IEM_MC_MAYBE_RAISE_SSE 42_RELATED_XCPT();1324 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT(); 1325 1325 IEM_MC_FETCH_MEM_U128(Src.uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); 1326 1326 … … 1355 1355 IEM_MC_ARG_LOCAL_REF(PIEMPCMPESTRXSRC, pSrc, Src, 2); 1356 1356 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3); 1357 IEM_MC_MAYBE_RAISE_SSE 42_RELATED_XCPT();1357 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT(); 1358 1358 IEM_MC_PREPARE_SSE_USAGE(); 1359 1359 IEM_MC_REF_GREG_U32(pu32Ecx, X86_GREG_xCX); … … 1387 1387 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3); 1388 1388 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse42); 1389 IEM_MC_MAYBE_RAISE_SSE 42_RELATED_XCPT();1389 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT(); 1390 1390 IEM_MC_FETCH_MEM_U128(Src.uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); 1391 1391 … … 1427 1427 IEM_MC_ARG_LOCAL_REF(PIEMPCMPISTRXSRC, pSrc, Src, 2); 1428 1428 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3); 1429 IEM_MC_MAYBE_RAISE_SSE 42_RELATED_XCPT();1429 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT(); 1430 1430 IEM_MC_PREPARE_SSE_USAGE(); 1431 1431 IEM_MC_FETCH_XREG_U128(Src.uSrc1, IEM_GET_MODRM_REG(pVCpu, bRm)); … … 1456 1456 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3); 1457 1457 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse42); 1458 IEM_MC_MAYBE_RAISE_SSE 42_RELATED_XCPT();1458 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT(); 1459 1459 IEM_MC_FETCH_MEM_U128(Src.uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); 1460 1460 … … 1492 1492 IEM_MC_ARG_LOCAL_REF(PIEMPCMPISTRXSRC, pSrc, Src, 2); 1493 1493 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3); 1494 IEM_MC_MAYBE_RAISE_SSE 42_RELATED_XCPT();1494 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT(); 1495 1495 IEM_MC_PREPARE_SSE_USAGE(); 1496 1496 IEM_MC_REF_GREG_U32(pu32Ecx, X86_GREG_xCX); … … 1522 1522 IEM_MC_ARG_CONST(uint8_t, bImmArg, /*=*/ bImm, 3); 1523 1523 IEMOP_HLP_DONE_DECODING_NO_LOCK_PREFIX_EX(fSse42); 1524 IEM_MC_MAYBE_RAISE_SSE 42_RELATED_XCPT();1524 IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT(); 1525 1525 IEM_MC_FETCH_MEM_U128(Src.uSrc2, pVCpu->iem.s.iEffSeg, GCPtrEffSrc); 1526 1526 -
trunk/src/VBox/VMM/include/IEMMc.h
r99339 r99340 106 106 } while (0) 107 107 #define IEM_MC_MAYBE_RAISE_SHA_RELATED_XCPT() \ 108 do { \109 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \110 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR)) \111 return iemRaiseUndefinedOpcode(pVCpu); \112 if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS) \113 return iemRaiseDeviceNotAvailable(pVCpu); \114 } while (0)115 #define IEM_MC_MAYBE_RAISE_SSE42_RELATED_XCPT() \116 108 do { \ 117 109 if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \ -
trunk/src/VBox/VMM/testcase/tstIEMCheckMc.cpp
r99339 r99340 578 578 #define IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT() do { (void)fMcBegin; } while (0) 579 579 #define IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT() do { (void)fMcBegin; } while (0) 580 #define IEM_MC_MAYBE_RAISE_SSE42_RELATED_XCPT() do { (void)fMcBegin; } while (0)581 580 #define IEM_MC_MAYBE_RAISE_AESNI_RELATED_XCPT() do { (void)fMcBegin; } while (0) 582 581 #define IEM_MC_MAYBE_RAISE_SHA_RELATED_XCPT() do { (void)fMcBegin; } while (0)
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