Changeset 99352 in vbox for trunk/src/VBox
- Timestamp:
- Apr 8, 2023 12:19:35 AM (2 years ago)
- svn:sync-xref-src-repo-rev:
- 156755
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
trunk/src/VBox/VMM/include/IEMMc.h
r99351 r99352 76 76 #define IEM_MC_MAYBE_RAISE_DEVICE_NOT_AVAILABLE() \ 77 77 do { \ 78 if (!(pVCpu->cpum.GstCtx.cr0 & (X86_CR0_EM | X86_CR0_TS))) { /* probable */ } \ 78 if (RT_LIKELY(!(pVCpu->cpum.GstCtx.cr0 & (X86_CR0_EM | X86_CR0_TS)))) \ 79 { /* probable */ } \ 79 80 else return iemRaiseDeviceNotAvailable(pVCpu); \ 80 81 } while (0) 81 82 #define IEM_MC_MAYBE_RAISE_WAIT_DEVICE_NOT_AVAILABLE() \ 82 83 do { \ 83 if (!((pVCpu->cpum.GstCtx.cr0 & (X86_CR0_MP | X86_CR0_TS)) == (X86_CR0_MP | X86_CR0_TS))) { /* probable */ } \ 84 if (RT_LIKELY(!((pVCpu->cpum.GstCtx.cr0 & (X86_CR0_MP | X86_CR0_TS)) == (X86_CR0_MP | X86_CR0_TS)))) \ 85 { /* probable */ } \ 84 86 else return iemRaiseDeviceNotAvailable(pVCpu); \ 85 87 } while (0) 86 88 #define IEM_MC_MAYBE_RAISE_FPU_XCPT() \ 87 89 do { \ 88 if (!(pVCpu->cpum.GstCtx.XState.x87.FSW & X86_FSW_ES)) { /* probable */ } \ 90 if (RT_LIKELY(!(pVCpu->cpum.GstCtx.XState.x87.FSW & X86_FSW_ES))) \ 91 { /* probable */ } \ 89 92 else return iemRaiseMathFault(pVCpu); \ 90 93 } while (0) … … 100 103 #define IEM_MC_MAYBE_RAISE_SSE_RELATED_XCPT() \ 101 104 do { \ 102 if ( !(pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \ 103 && (pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR)) { /* probable */ } \ 104 else return iemRaiseUndefinedOpcode(pVCpu); \ 105 \ 106 if (!(pVCpu->cpum.GstCtx.cr0 & X86_CR0_TS)) { /* probable */ } \ 107 else return iemRaiseDeviceNotAvailable(pVCpu); \ 105 /* Since the CR4 and CR0 bits doesn't overlap, it can be reduced to a 106 single compare branch in the more probable code path. */ \ 107 AssertCompile(!((X86_CR0_EM | X86_CR0_TS) & X86_CR4_OSFXSR)); \ 108 if (RT_LIKELY( ( (pVCpu->cpum.GstCtx.cr0 & (X86_CR0_EM | X86_CR0_TS)) \ 109 | (pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR)) \ 110 == X86_CR4_OSFXSR)) \ 111 { /* likely */ } \ 112 else if ( (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \ 113 || !(pVCpu->cpum.GstCtx.cr4 & X86_CR4_OSFXSR)) \ 114 return iemRaiseUndefinedOpcode(pVCpu); \ 115 else \ 116 return iemRaiseDeviceNotAvailable(pVCpu); \ 108 117 } while (0) 109 118 #define IEM_MC_MAYBE_RAISE_MMX_RELATED_XCPT() \ 110 119 do { \ 111 if ( !(pVCpu->cpum.GstCtx.cr0 & (X86_CR0_EM | X86_CR0_TS))) \120 if (RT_LIKELY(!(pVCpu->cpum.GstCtx.cr0 & (X86_CR0_EM | X86_CR0_TS)))) \ 112 121 { /* probable */ } \ 113 122 else if (pVCpu->cpum.GstCtx.cr0 & X86_CR0_EM) \ … … 121 130 #define IEM_MC_RAISE_GP0_IF_CPL_NOT_ZERO() \ 122 131 do { \ 123 if ( pVCpu->iem.s.uCpl == 0) { /* probable */ } \132 if (RT_LIKELY(pVCpu->iem.s.uCpl == 0)) { /* probable */ } \ 124 133 else return iemRaiseGeneralProtectionFault0(pVCpu); \ 125 134 } while (0) … … 131 140 #define IEM_MC_MAYBE_RAISE_FSGSBASE_XCPT() \ 132 141 do { \ 133 if ( pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT \ 134 && (pVCpu->cpum.GstCtx.cr4 & X86_CR4_FSGSBASE)) { /* probable */ } \ 142 if (RT_LIKELY( pVCpu->iem.s.enmCpuMode == IEMMODE_64BIT \ 143 && (pVCpu->cpum.GstCtx.cr4 & X86_CR4_FSGSBASE))) \ 144 { /* probable */ } \ 135 145 else return iemRaiseUndefinedOpcode(pVCpu); \ 136 146 } while (0) … … 142 152 #define IEM_MC_MAYBE_RAISE_SSE_AVX_SIMD_FP_OR_UD_XCPT() \ 143 153 do { \ 144 if ( ( ~((pVCpu->cpum.GstCtx.XState.x87.MXCSR & X86_MXCSR_XCPT_MASK) >> X86_MXCSR_XCPT_MASK_SHIFT) \145 & (pVCpu->cpum.GstCtx.XState.x87.MXCSR & X86_MXCSR_XCPT_FLAGS)) == 0) \154 if (RT_LIKELY(( ~((pVCpu->cpum.GstCtx.XState.x87.MXCSR & X86_MXCSR_XCPT_MASK) >> X86_MXCSR_XCPT_MASK_SHIFT) \ 155 & (pVCpu->cpum.GstCtx.XState.x87.MXCSR & X86_MXCSR_XCPT_FLAGS)) == 0)) \ 146 156 { /* probable */ } \ 147 157 else \
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