Changeset 99379 in vbox

Timestamp:

Apr 12, 2023 10:30:59 AM (2 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

156805

Message:

VMM/ARMv8: Sync and log the TCR_EL1 register as well, bugref:10390, bugref:10387, bugref:10388

Location:

trunk

Files:

• include/VBox/vmm/cpumctx-armv8.h (modified) (3 diffs)
• include/VBox/vmm/dbgf.h (modified) (1 diff)
• src/VBox/VMM/VMMR3/CPUMDbg-armv8.cpp (modified) (1 diff)
• src/VBox/VMM/VMMR3/NEMR3Native-darwin-armv8.cpp (modified) (4 diffs)

trunk/include/VBox/vmm/cpumctx-armv8.h

@@ -141 +141 @@
     /** The SCTLR_EL1 register. */
     CPUMCTXSYSREG   Sctlr;
+    /** THe TCR_EL1 register. */
+    CPUMCTXSYSREG   Tcr;
     /** The TTBR0_EL1 register. */
     CPUMCTXSYSREG   Ttbr0;
@@ -158 +160 @@
     uint64_t        fExtrn;
 
-    uint64_t        au64Padding1[3];
+    uint64_t        au64Padding1[2];
 } CPUMCTX;
 
@@ -192 +194 @@
 /** The PSTATE value is kept externally. */
 #define CPUMCTX_EXTRN_PSTATE                    UINT64_C(0x0000000000000040)
-/** The SCTRL_EL1/TTBR{0,1}_EL1 system registers are kept externally. */
-#define CPUMCTX_EXTRN_SCTLR_TTBR                UINT64_C(0x0000000000000080)
+/** The SCTRL_EL1/TCR_EL1/TTBR{0,1}_EL1 system registers are kept externally. */
+#define CPUMCTX_EXTRN_SCTLR_TCR_TTBR            UINT64_C(0x0000000000000080)
 
 /** The X0 register value is kept externally. */

trunk/include/VBox/vmm/dbgf.h

@@ -2155 +2155 @@
     DBGFREG_ARMV8_SPSR_EL1,
     DBGFREG_ARMV8_SPSR_EL2,
+    DBGFREG_ARMV8_PSTATE = DBGFREG_ARMV8_SPSR_EL2,
     DBGFREG_ARMV8_SCTLR_EL1,
+    DBGFREG_ARMV8_TCR_EL1,
     DBGFREG_ARMV8_TTBR0_EL1,
     DBGFREG_ARMV8_TTBR1_EL1,
-    DBGFREG_ARMV8_PSTATE = DBGFREG_ARMV8_SPSR_EL2,
     DBGFREG_ARMV8_ELR_EL1,
 

trunk/src/VBox/VMM/VMMR3/CPUMDbg-armv8.cpp

@@ -276 +276 @@
     CPU_REG_RW_AS("spsr_el1",       SPSR_EL1,       U64, Spsr,            cpumR3RegGet_Generic,         cpumR3RegSet_Generic,         NULL,                       NULL                    ),
     CPU_REG_RW_AS("sctlr_el1",      SCTLR_EL1,      U64, Sctlr,           cpumR3RegGet_Generic,         cpumR3RegSet_Generic,         NULL,                       NULL                    ),
+    CPU_REG_RW_AS("tcr_el1",        TCR_EL1,        U64, Tcr,             cpumR3RegGet_Generic,         cpumR3RegSet_Generic,         NULL,                       NULL                    ),
     CPU_REG_RW_AS("ttbr0_el1",      TTBR0_EL1,      U64, Ttbr0,           cpumR3RegGet_Generic,         cpumR3RegSet_Generic,         NULL,                       NULL                    ),
     CPU_REG_RW_AS("ttbr1_el1",      TTBR1_EL1,      U64, Ttbr1,           cpumR3RegGet_Generic,         cpumR3RegSet_Generic,         NULL,                       NULL                    ),

trunk/src/VBox/VMM/VMMR3/NEMR3Native-darwin-armv8.cpp

@@ -177 +177 @@
 } s_aCpumSysRegs[] =
 {
-    { HV_SYS_REG_SP_EL0,    CPUMCTX_EXTRN_SP,            RT_UOFFSETOF(CPUMCTX, aSpReg[0].u64)    },
-    { HV_SYS_REG_SP_EL1,    CPUMCTX_EXTRN_SP,            RT_UOFFSETOF(CPUMCTX, aSpReg[1].u64)    },
-    { HV_SYS_REG_SPSR_EL1,  CPUMCTX_EXTRN_SPSR,          RT_UOFFSETOF(CPUMCTX, Spsr.u64)         },
-    { HV_SYS_REG_ELR_EL1,   CPUMCTX_EXTRN_ELR,           RT_UOFFSETOF(CPUMCTX, Elr.u64)          },
-    { HV_SYS_REG_SCTLR_EL1, CPUMCTX_EXTRN_SCTLR_TTBR,    RT_UOFFSETOF(CPUMCTX, Sctlr.u64)        },
-    { HV_SYS_REG_TTBR0_EL1, CPUMCTX_EXTRN_SCTLR_TTBR,    RT_UOFFSETOF(CPUMCTX, Ttbr0.u64)        },
-    { HV_SYS_REG_TTBR1_EL1, CPUMCTX_EXTRN_SCTLR_TTBR,    RT_UOFFSETOF(CPUMCTX, Ttbr1.u64)        },
+    { HV_SYS_REG_SP_EL0,    CPUMCTX_EXTRN_SP,               RT_UOFFSETOF(CPUMCTX, aSpReg[0].u64)    },
+    { HV_SYS_REG_SP_EL1,    CPUMCTX_EXTRN_SP,               RT_UOFFSETOF(CPUMCTX, aSpReg[1].u64)    },
+    { HV_SYS_REG_SPSR_EL1,  CPUMCTX_EXTRN_SPSR,             RT_UOFFSETOF(CPUMCTX, Spsr.u64)         },
+    { HV_SYS_REG_ELR_EL1,   CPUMCTX_EXTRN_ELR,              RT_UOFFSETOF(CPUMCTX, Elr.u64)          },
+    { HV_SYS_REG_SCTLR_EL1, CPUMCTX_EXTRN_SCTLR_TCR_TTBR,   RT_UOFFSETOF(CPUMCTX, Sctlr.u64)        },
+    { HV_SYS_REG_TCR_EL1,   CPUMCTX_EXTRN_SCTLR_TCR_TTBR,   RT_UOFFSETOF(CPUMCTX, Tcr.u64)          },
+    { HV_SYS_REG_TTBR0_EL1, CPUMCTX_EXTRN_SCTLR_TCR_TTBR,   RT_UOFFSETOF(CPUMCTX, Ttbr0.u64)        },
+    { HV_SYS_REG_TTBR1_EL1, CPUMCTX_EXTRN_SCTLR_TCR_TTBR,   RT_UOFFSETOF(CPUMCTX, Ttbr1.u64)        },
 };
 
@@ -419 +420 @@
                         "pc=%016VR{pc} pstate=%016VR{pstate}\n"
                         "sp_el0=%016VR{sp_el0} sp_el1=%016VR{sp_el1} elr_el1=%016VR{elr_el1}\n"
-                        "sctlr_el1=%016VR{sctlr_el1} ttbr0_el1=%016VR{ttbr0_el1} ttbr1_el1=%016VR{ttbr1_el1}\n"
+                        "sctlr_el1=%016VR{sctlr_el1} tcr_el1=%016VR{tcr_el1}\n"
+                        "ttbr0_el1=%016VR{ttbr0_el1} ttbr1_el1=%016VR{ttbr1_el1}\n"
                         );
         char szInstr[256]; RT_ZERO(szInstr);
@@ -462 +464 @@
 
     if (   hrc == HV_SUCCESS
-        && (fWhat & (CPUMCTX_EXTRN_SPSR | CPUMCTX_EXTRN_ELR | CPUMCTX_EXTRN_SP | CPUMCTX_EXTRN_SCTLR_TTBR)))
+        && (fWhat & (CPUMCTX_EXTRN_SPSR | CPUMCTX_EXTRN_ELR | CPUMCTX_EXTRN_SP | CPUMCTX_EXTRN_SCTLR_TCR_TTBR)))
     {
         /* System registers. */
@@ -650 +652 @@
 
     if (   hrc == HV_SUCCESS
-        &&     (pVCpu->cpum.GstCtx.fExtrn & (CPUMCTX_EXTRN_SPSR | CPUMCTX_EXTRN_ELR | CPUMCTX_EXTRN_SP))
-            !=                              (CPUMCTX_EXTRN_SPSR | CPUMCTX_EXTRN_ELR | CPUMCTX_EXTRN_SP))
+        &&     (pVCpu->cpum.GstCtx.fExtrn & (CPUMCTX_EXTRN_SPSR | CPUMCTX_EXTRN_ELR | CPUMCTX_EXTRN_SP | CPUMCTX_EXTRN_SCTLR_TCR_TTBR))
+            !=                              (CPUMCTX_EXTRN_SPSR | CPUMCTX_EXTRN_ELR | CPUMCTX_EXTRN_SP | CPUMCTX_EXTRN_SCTLR_TCR_TTBR))
     {
         /* System registers. */