Changeset 99404 in vbox for trunk/src/VBox/Devices/EFI/FirmwareNew/UefiCpuPkg/Universal
- Timestamp:
- Apr 14, 2023 3:17:44 PM (2 years ago)
- svn:sync-xref-src-repo-rev:
- 156854
- Location:
- trunk/src/VBox/Devices/EFI/FirmwareNew
- Files:
-
- 4 edited
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- Unmodified
- Added
- Removed
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trunk/src/VBox/Devices/EFI/FirmwareNew
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to (toggle deleted branches)/vendor/edk2/current 103735-103757,103769-103776,129194-145445 /vendor/edk2/current 103735-103757,103769-103776,129194-156846
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trunk/src/VBox/Devices/EFI/FirmwareNew/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/Ia32/AsmFuncs.nasm
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text/x-asm
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trunk/src/VBox/Devices/EFI/FirmwareNew/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/S3Resume.c
r80721 r99404 5 5 control is passed to OS waking up handler. 6 6 7 Copyright (c) 2006 - 20 19, Intel Corporation. All rights reserved.<BR>7 Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR> 8 8 Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR> 9 9 … … 59 59 typedef union { 60 60 struct { 61 UINT32 LimitLow : 16;62 UINT32 BaseLow : 16;63 UINT32 BaseMid : 8;64 UINT32 Type : 4;65 UINT32 System : 1;66 UINT32 Dpl : 2;67 UINT32 Present : 1;68 UINT32 LimitHigh : 4;69 UINT32 Software : 1;70 UINT32 Reserved : 1;71 UINT32 DefaultSize : 1;72 UINT32 Granularity : 1;73 UINT32 BaseHigh : 8;61 UINT32 LimitLow : 16; 62 UINT32 BaseLow : 16; 63 UINT32 BaseMid : 8; 64 UINT32 Type : 4; 65 UINT32 System : 1; 66 UINT32 Dpl : 2; 67 UINT32 Present : 1; 68 UINT32 LimitHigh : 4; 69 UINT32 Software : 1; 70 UINT32 Reserved : 1; 71 UINT32 DefaultSize : 1; 72 UINT32 Granularity : 1; 73 UINT32 BaseHigh : 8; 74 74 } Bits; 75 UINT64 Uint64;75 UINT64 Uint64; 76 76 } IA32_GDT; 77 77 … … 82 82 typedef union { 83 83 struct { 84 UINT64 Present:1;// 0 = Not present in memory, 1 = Present in memory85 UINT64 ReadWrite:1;// 0 = Read-Only, 1= Read/Write86 UINT64 UserSupervisor:1;// 0 = Supervisor, 1=User87 UINT64 WriteThrough:1;// 0 = Write-Back caching, 1=Write-Through caching88 UINT64 CacheDisabled:1;// 0 = Cached, 1=Non-Cached89 UINT64 Accessed:1;// 0 = Not accessed, 1 = Accessed (set by CPU)90 UINT64 Reserved:1;// Reserved91 UINT64 MustBeZero:2;// Must Be Zero92 UINT64 Available:3;// Available for use by system software93 UINT64 PageTableBaseAddress:40;// Page Table Base Address94 UINT64 AvabilableHigh:11;// Available for use by system software95 UINT64 Nx:1;// No Execute bit84 UINT64 Present : 1; // 0 = Not present in memory, 1 = Present in memory 85 UINT64 ReadWrite : 1; // 0 = Read-Only, 1= Read/Write 86 UINT64 UserSupervisor : 1; // 0 = Supervisor, 1=User 87 UINT64 WriteThrough : 1; // 0 = Write-Back caching, 1=Write-Through caching 88 UINT64 CacheDisabled : 1; // 0 = Cached, 1=Non-Cached 89 UINT64 Accessed : 1; // 0 = Not accessed, 1 = Accessed (set by CPU) 90 UINT64 Reserved : 1; // Reserved 91 UINT64 MustBeZero : 2; // Must Be Zero 92 UINT64 Available : 3; // Available for use by system software 93 UINT64 PageTableBaseAddress : 40; // Page Table Base Address 94 UINT64 AvabilableHigh : 11; // Available for use by system software 95 UINT64 Nx : 1; // No Execute bit 96 96 } Bits; 97 97 UINT64 Uint64; … … 103 103 typedef union { 104 104 struct { 105 UINT64 Present:1;// 0 = Not present in memory, 1 = Present in memory106 UINT64 ReadWrite:1;// 0 = Read-Only, 1= Read/Write107 UINT64 UserSupervisor:1;// 0 = Supervisor, 1=User108 UINT64 WriteThrough:1;// 0 = Write-Back caching, 1=Write-Through caching109 UINT64 CacheDisabled:1;// 0 = Cached, 1=Non-Cached110 UINT64 Accessed:1;// 0 = Not accessed, 1 = Accessed (set by CPU)111 UINT64 Dirty:1;// 0 = Not Dirty, 1 = written by processor on access to page112 UINT64 MustBe1:1;// Must be 1113 UINT64 Global:1;// 0 = Not global page, 1 = global page TLB not cleared on CR3 write114 UINT64 Available:3;// Available for use by system software115 UINT64 PAT:1;//116 UINT64 MustBeZero:8;// Must be zero;117 UINT64 PageTableBaseAddress:31;// Page Table Base Address118 UINT64 AvabilableHigh:11;// Available for use by system software119 UINT64 Nx:1;// 0 = Execute Code, 1 = No Code Execution105 UINT64 Present : 1; // 0 = Not present in memory, 1 = Present in memory 106 UINT64 ReadWrite : 1; // 0 = Read-Only, 1= Read/Write 107 UINT64 UserSupervisor : 1; // 0 = Supervisor, 1=User 108 UINT64 WriteThrough : 1; // 0 = Write-Back caching, 1=Write-Through caching 109 UINT64 CacheDisabled : 1; // 0 = Cached, 1=Non-Cached 110 UINT64 Accessed : 1; // 0 = Not accessed, 1 = Accessed (set by CPU) 111 UINT64 Dirty : 1; // 0 = Not Dirty, 1 = written by processor on access to page 112 UINT64 MustBe1 : 1; // Must be 1 113 UINT64 Global : 1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write 114 UINT64 Available : 3; // Available for use by system software 115 UINT64 PAT : 1; // 116 UINT64 MustBeZero : 8; // Must be zero; 117 UINT64 PageTableBaseAddress : 31; // Page Table Base Address 118 UINT64 AvabilableHigh : 11; // Available for use by system software 119 UINT64 Nx : 1; // 0 = Execute Code, 1 = No Code Execution 120 120 } Bits; 121 121 UINT64 Uint64; … … 127 127 typedef union { 128 128 struct { 129 UINT64 Present:1;// 0 = Not present in memory, 1 = Present in memory130 UINT64 ReadWrite:1;// 0 = Read-Only, 1= Read/Write131 UINT64 UserSupervisor:1;// 0 = Supervisor, 1=User132 UINT64 WriteThrough:1;// 0 = Write-Back caching, 1=Write-Through caching133 UINT64 CacheDisabled:1;// 0 = Cached, 1=Non-Cached134 UINT64 Accessed:1;// 0 = Not accessed, 1 = Accessed (set by CPU)135 UINT64 Dirty:1;// 0 = Not Dirty, 1 = written by processor on access to page136 UINT64 MustBe1:1;// Must be 1137 UINT64 Global:1;// 0 = Not global page, 1 = global page TLB not cleared on CR3 write138 UINT64 Available:3;// Available for use by system software139 UINT64 PAT:1;//140 UINT64 MustBeZero:17;// Must be zero;141 UINT64 PageTableBaseAddress:22;// Page Table Base Address142 UINT64 AvabilableHigh:11;// Available for use by system software143 UINT64 Nx:1;// 0 = Execute Code, 1 = No Code Execution129 UINT64 Present : 1; // 0 = Not present in memory, 1 = Present in memory 130 UINT64 ReadWrite : 1; // 0 = Read-Only, 1= Read/Write 131 UINT64 UserSupervisor : 1; // 0 = Supervisor, 1=User 132 UINT64 WriteThrough : 1; // 0 = Write-Back caching, 1=Write-Through caching 133 UINT64 CacheDisabled : 1; // 0 = Cached, 1=Non-Cached 134 UINT64 Accessed : 1; // 0 = Not accessed, 1 = Accessed (set by CPU) 135 UINT64 Dirty : 1; // 0 = Not Dirty, 1 = written by processor on access to page 136 UINT64 MustBe1 : 1; // Must be 1 137 UINT64 Global : 1; // 0 = Not global page, 1 = global page TLB not cleared on CR3 write 138 UINT64 Available : 3; // Available for use by system software 139 UINT64 PAT : 1; // 140 UINT64 MustBeZero : 17; // Must be zero; 141 UINT64 PageTableBaseAddress : 22; // Page Table Base Address 142 UINT64 AvabilableHigh : 11; // Available for use by system software 143 UINT64 Nx : 1; // 0 = Execute Code, 1 = No Code Execution 144 144 } Bits; 145 145 UINT64 Uint64; … … 151 151 // 152 152 typedef struct { 153 EFI_GUID HeaderGuid;154 UINT32 MessageLength;155 UINT8 Data[1];153 EFI_GUID HeaderGuid; 154 UINT32 MessageLength; 155 UINT8 Data[1]; 156 156 } SMM_COMMUNICATE_HEADER_32; 157 157 158 158 typedef struct { 159 EFI_GUID HeaderGuid;160 UINT64 MessageLength;161 UINT8 Data[1];159 EFI_GUID HeaderGuid; 160 UINT64 MessageLength; 161 UINT8 Data[1]; 162 162 } SMM_COMMUNICATE_HEADER_64; 163 163 … … 167 167 // Function prototypes 168 168 // 169 169 170 /** 170 171 a ASM function to transfer control to OS. … … 175 176 typedef 176 177 VOID 177 (EFIAPI *ASM_TRANSFER_CONTROL) 178 (EFIAPI *ASM_TRANSFER_CONTROL)( 178 179 IN UINT32 S3WakingVector, 179 180 IN UINT32 AcpiLowMemoryBase … … 226 227 EFIAPI 227 228 AsmSetDataSelectors ( 228 IN UINT16 229 IN UINT16 SelectorValue 229 230 ); 230 231 … … 232 233 // Globals 233 234 // 234 EFI_PEI_S3_RESUME2_PPI 235 236 EFI_PEI_PPI_DESCRIPTOR mPpiList = {235 EFI_PEI_S3_RESUME2_PPI mS3ResumePpi = { S3RestoreConfig2 }; 236 237 EFI_PEI_PPI_DESCRIPTOR mPpiList = { 237 238 (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), 238 239 &gEfiPeiS3Resume2PpiGuid, … … 240 241 }; 241 242 242 EFI_PEI_PPI_DESCRIPTOR mPpiListPostScriptTable = {243 EFI_PEI_PPI_DESCRIPTOR mPpiListPostScriptTable = { 243 244 (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), 244 245 &gPeiPostScriptTablePpiGuid, … … 246 247 }; 247 248 248 EFI_PEI_PPI_DESCRIPTOR mPpiListEndOfPeiTable = {249 EFI_PEI_PPI_DESCRIPTOR mPpiListEndOfPeiTable = { 249 250 (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), 250 251 &gEfiEndOfPeiSignalPpiGuid, … … 252 253 }; 253 254 254 EFI_PEI_PPI_DESCRIPTOR mPpiListS3SmmInitDoneTable = {255 EFI_PEI_PPI_DESCRIPTOR mPpiListS3SmmInitDoneTable = { 255 256 (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST), 256 257 &gEdkiiS3SmmInitDoneGuid, … … 261 262 // Global Descriptor Table (GDT) 262 263 // 263 GLOBAL_REMOVE_IF_UNREFERENCED IA32_GDT mGdtEntries[] = { 264 /* selector { Global Segment Descriptor } */ 265 /* 0x00 */ {{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}}, 266 /* 0x08 */ {{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}}, 267 /* 0x10 */ {{0xFFFF, 0, 0, 0xB, 1, 0, 1, 0xF, 0, 0, 1, 1, 0}}, 268 /* 0x18 */ {{0xFFFF, 0, 0, 0x3, 1, 0, 1, 0xF, 0, 0, 1, 1, 0}}, 269 /* 0x20 */ {{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}}, 270 /* 0x28 */ {{0xFFFF, 0, 0, 0xB, 1, 0, 1, 0xF, 0, 0, 0, 1, 0}}, 271 /* 0x30 */ {{0xFFFF, 0, 0, 0x3, 1, 0, 1, 0xF, 0, 0, 0, 1, 0}}, 272 /* 0x38 */ {{0xFFFF, 0, 0, 0xB, 1, 0, 1, 0xF, 0, 1, 0, 1, 0}}, 273 /* 0x40 */ {{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}}, 264 GLOBAL_REMOVE_IF_UNREFERENCED IA32_GDT mGdtEntries[] = { 265 /* selector { Global Segment Descriptor } */ 266 /* 0x00 */ { 267 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } 268 }, 269 /* 0x08 */ { 270 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } 271 }, 272 /* 0x10 */ { 273 { 0xFFFF, 0, 0, 0xB, 1, 0, 1, 0xF, 0, 0, 1, 1, 0 } 274 }, 275 /* 0x18 */ { 276 { 0xFFFF, 0, 0, 0x3, 1, 0, 1, 0xF, 0, 0, 1, 1, 0 } 277 }, 278 /* 0x20 */ { 279 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } 280 }, 281 /* 0x28 */ { 282 { 0xFFFF, 0, 0, 0xB, 1, 0, 1, 0xF, 0, 0, 0, 1, 0 } 283 }, 284 /* 0x30 */ { 285 { 0xFFFF, 0, 0, 0x3, 1, 0, 1, 0xF, 0, 0, 0, 1, 0 } 286 }, 287 /* 0x38 */ { 288 { 0xFFFF, 0, 0, 0xB, 1, 0, 1, 0xF, 0, 1, 0, 1, 0 } 289 }, 290 /* 0x40 */ { 291 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 } 292 }, 274 293 }; 275 294 276 #define DATA_SEGEMENT_SELECTOR 295 #define DATA_SEGEMENT_SELECTOR 0x18 277 296 278 297 // 279 298 // IA32 Gdt register 280 299 // 281 GLOBAL_REMOVE_IF_UNREFERENCED CONST IA32_DESCRIPTOR mGdt = {300 GLOBAL_REMOVE_IF_UNREFERENCED CONST IA32_DESCRIPTOR mGdt = { 282 301 sizeof (mGdtEntries) - 1, 283 (UINTN) mGdtEntries 284 }; 285 302 (UINTN)mGdtEntries 303 }; 286 304 287 305 /** … … 295 313 BOOLEAN 296 314 IsLongModeWakingVector ( 297 IN ACPI_S3_CONTEXT 315 IN ACPI_S3_CONTEXT *AcpiS3Context 298 316 ) 299 317 { 300 318 EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE *Facs; 301 319 302 Facs = (EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE *) ((UINTN)(AcpiS3Context->AcpiFacsTable));320 Facs = (EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE *)((UINTN)(AcpiS3Context->AcpiFacsTable)); 303 321 if ((Facs == NULL) || 304 322 (Facs->Signature != EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE) || 305 ((Facs->FirmwareWakingVector == 0) && (Facs->XFirmwareWakingVector == 0)) ) { 323 ((Facs->FirmwareWakingVector == 0) && (Facs->XFirmwareWakingVector == 0))) 324 { 306 325 // Something wrong with FACS 307 326 return FALSE; 308 327 } 328 309 329 if (Facs->XFirmwareWakingVector != 0) { 310 330 if ((Facs->Version == EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION) && 311 331 ((Facs->Flags & EFI_ACPI_4_0_64BIT_WAKE_SUPPORTED_F) != 0) && 312 ((Facs->OspmFlags & EFI_ACPI_4_0_OSPM_64BIT_WAKE__F) != 0)) { 332 ((Facs->OspmFlags & EFI_ACPI_4_0_OSPM_64BIT_WAKE__F) != 0)) 333 { 313 334 // Both BIOS and OS wants 64bit vector 314 if (FeaturePcdGet (PcdDxeIplSwitchToLongMode)) {315 316 317 318 } 335 ASSERT ((FeaturePcdGet (PcdDxeIplSwitchToLongMode)) || (sizeof (UINTN) == sizeof (UINT64))); 336 return TRUE; 337 } 338 } 339 319 340 return FALSE; 320 341 } … … 328 349 VOID 329 350 SignalToSmmByCommunication ( 330 IN EFI_GUID 351 IN EFI_GUID *HandlerType 331 352 ) 332 353 { 333 EFI_STATUS 334 EFI_PEI_SMM_COMMUNICATION_PPI 335 UINTN 336 SMM_COMMUNICATE_HEADER_32 337 SMM_COMMUNICATE_HEADER_64 338 VOID 354 EFI_STATUS Status; 355 EFI_PEI_SMM_COMMUNICATION_PPI *SmmCommunicationPpi; 356 UINTN CommSize; 357 SMM_COMMUNICATE_HEADER_32 Header32; 358 SMM_COMMUNICATE_HEADER_64 Header64; 359 VOID *CommBuffer; 339 360 340 361 DEBUG ((DEBUG_INFO, "Signal %g to SMM - Enter\n", HandlerType)); … … 346 367 // or (FeaturePcdGet (PcdDxeIplSwitchToLongMode)), DXE will switch to 64 bits. 347 368 // 348 if ((sizeof (UINTN) == sizeof(UINT64)) || (FeaturePcdGet (PcdDxeIplSwitchToLongMode))) {349 CommBuffer = &Header64;369 if ((sizeof (UINTN) == sizeof (UINT64)) || (FeaturePcdGet (PcdDxeIplSwitchToLongMode))) { 370 CommBuffer = &Header64; 350 371 Header64.MessageLength = 0; 351 CommSize = OFFSET_OF (SMM_COMMUNICATE_HEADER_64, Data);372 CommSize = OFFSET_OF (SMM_COMMUNICATE_HEADER_64, Data); 352 373 } else { 353 CommBuffer = &Header32;374 CommBuffer = &Header32; 354 375 Header32.MessageLength = 0; 355 CommSize = OFFSET_OF (SMM_COMMUNICATE_HEADER_32, Data); 356 } 376 CommSize = OFFSET_OF (SMM_COMMUNICATE_HEADER_32, Data); 377 } 378 357 379 CopyGuid (CommBuffer, HandlerType); 358 380 … … 391 413 EFIAPI 392 414 S3ResumeBootOs ( 393 IN ACPI_S3_CONTEXT 394 IN PEI_S3_RESUME_STATE 415 IN ACPI_S3_CONTEXT *AcpiS3Context, 416 IN PEI_S3_RESUME_STATE *PeiS3ResumeState 395 417 ) 396 418 { … … 437 459 // Get ACPI Table Address 438 460 // 439 Facs = (EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE *) ((UINTN)(AcpiS3Context->AcpiFacsTable));461 Facs = (EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE *)((UINTN)(AcpiS3Context->AcpiFacsTable)); 440 462 441 463 if ((Facs == NULL) || 442 464 (Facs->Signature != EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE) || 443 ((Facs->FirmwareWakingVector == 0) && (Facs->XFirmwareWakingVector == 0)) ) { 465 ((Facs->FirmwareWakingVector == 0) && (Facs->XFirmwareWakingVector == 0))) 466 { 444 467 // 445 468 // Report Status code that no valid vector is found … … 450 473 ); 451 474 CpuDeadLoop (); 452 return 475 return; 453 476 } 454 477 … … 456 479 // Install EndOfPeiPpi 457 480 // 458 PERF_INMODULE_BEGIN ("EndOfPeiPpi");481 PERF_INMODULE_BEGIN ("EndOfPeiPpi"); 459 482 460 483 Status = PeiServicesInstallPpi (&mPpiListEndOfPeiTable); 461 484 ASSERT_EFI_ERROR (Status); 462 485 463 PERF_INMODULE_END ("EndOfPeiPpi");464 465 PERF_INMODULE_BEGIN ("EndOfS3Resume");486 PERF_INMODULE_END ("EndOfPeiPpi"); 487 488 PERF_INMODULE_BEGIN ("EndOfS3Resume"); 466 489 467 490 DEBUG ((DEBUG_INFO, "Signal EndOfS3Resume\n")); … … 483 506 // Switch to native waking vector 484 507 // 485 TempStackTop = (UINTN)&TempStack + sizeof (TempStack);508 TempStackTop = (UINTN)&TempStack + sizeof (TempStack); 486 509 DEBUG (( 487 510 DEBUG_INFO, … … 493 516 if ((Facs->Version == EFI_ACPI_4_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION) && 494 517 ((Facs->Flags & EFI_ACPI_4_0_64BIT_WAKE_SUPPORTED_F) != 0) && 495 ((Facs->OspmFlags & EFI_ACPI_4_0_OSPM_64BIT_WAKE__F) != 0)) { 518 ((Facs->OspmFlags & EFI_ACPI_4_0_OSPM_64BIT_WAKE__F) != 0)) 519 { 496 520 // 497 521 // X64 long mode waking vector 498 522 // 499 DEBUG ((DEBUG_INFO, "Transfer to 64bit OS waking vector - %x\r\n", (UINTN)Facs->XFirmwareWakingVector));523 DEBUG ((DEBUG_INFO, "Transfer from PEI to 64bit OS waking vector - %x\r\n", (UINTN)Facs->XFirmwareWakingVector)); 500 524 if (FeaturePcdGet (PcdDxeIplSwitchToLongMode)) { 525 // 526 // 32bit PEI calls to 64bit OS S3 waking vector 527 // 501 528 AsmEnablePaging64 ( 502 529 0x38, … … 507 534 ); 508 535 } else { 509 // 510 // Report Status code that no valid waking vector is found 511 // 512 REPORT_STATUS_CODE ( 513 EFI_ERROR_CODE | EFI_ERROR_MAJOR, 514 (EFI_SOFTWARE_PEI_MODULE | EFI_SW_PEI_EC_S3_OS_WAKE_ERROR) 515 ); 516 DEBUG (( EFI_D_ERROR, "Unsupported for 32bit DXE transfer to 64bit OS waking vector!\r\n")); 517 ASSERT (FALSE); 518 CpuDeadLoop (); 519 return ; 536 if (sizeof (UINTN) == sizeof (UINT64)) { 537 // 538 // 64bit PEI calls to 64bit OS S3 waking vector 539 // 540 SwitchStack ( 541 (SWITCH_STACK_ENTRY_POINT)(UINTN)Facs->XFirmwareWakingVector, 542 NULL, 543 NULL, 544 (VOID *)(UINTN)TempStackTop 545 ); 546 } else { 547 // 548 // Report Status code that no valid waking vector is found. 549 // Note: 32bit PEI + 32bit DXE firmware calling to 64bit OS S3 waking vector is an invalid configuration. 550 // 551 REPORT_STATUS_CODE ( 552 EFI_ERROR_CODE | EFI_ERROR_MAJOR, 553 (EFI_SOFTWARE_PEI_MODULE | EFI_SW_PEI_EC_S3_OS_WAKE_ERROR) 554 ); 555 DEBUG ((DEBUG_ERROR, "Unsupported for 32bit DXE transfer to 64bit OS waking vector!\r\n")); 556 ASSERT (FALSE); 557 CpuDeadLoop (); 558 return; 559 } 520 560 } 521 561 } else { … … 524 564 // 525 565 DEBUG ((DEBUG_INFO, "Transfer to 32bit OS waking vector - %x\r\n", (UINTN)Facs->XFirmwareWakingVector)); 526 SwitchStack ( 527 (SWITCH_STACK_ENTRY_POINT) (UINTN) Facs->XFirmwareWakingVector, 528 NULL, 529 NULL, 530 (VOID *)(UINTN)TempStackTop 531 ); 566 if (sizeof (UINTN) == sizeof (UINT64)) { 567 // 568 // 64bit PEI calls to 32bit OS S3 waking vector 569 // 570 AsmDisablePaging64 ( 571 0x10, 572 (UINT32)Facs->XFirmwareWakingVector, 573 0, 574 0, 575 (UINT32)TempStackTop 576 ); 577 } else { 578 // 579 // 32bit PEI calls to 32bit OS S3 waking vector 580 // 581 SwitchStack ( 582 (SWITCH_STACK_ENTRY_POINT)(UINTN)Facs->XFirmwareWakingVector, 583 NULL, 584 NULL, 585 (VOID *)(UINTN)TempStackTop 586 ); 587 } 532 588 } 533 589 } else { … … 550 606 // Never run to here 551 607 // 552 CpuDeadLoop ();608 CpuDeadLoop (); 553 609 } 554 610 555 611 /** 556 612 Restore S3 page table because we do not trust ACPINvs content. 557 If BootScriptExec tor driver will not run in 64-bit mode, this function will do nothing.613 If BootScriptExecutor driver will not run in 64-bit mode, this function will do nothing. 558 614 559 615 @param S3NvsPageTableAddress PageTableAddress in ACPINvs … … 562 618 VOID 563 619 RestoreS3PageTables ( 564 IN UINTN 565 IN BOOLEAN 620 IN UINTN S3NvsPageTableAddress, 621 IN BOOLEAN Build4GPageTableOnly 566 622 ) 567 623 { 568 if ( FeaturePcdGet (PcdDxeIplSwitchToLongMode)) {569 UINT32 570 UINT32 571 UINT8 572 EFI_PHYSICAL_ADDRESS 573 UINTN 574 UINTN 575 UINTN 576 UINT32 577 UINT32 578 PAGE_MAP_AND_DIRECTORY_POINTER 579 PAGE_MAP_AND_DIRECTORY_POINTER 580 PAGE_MAP_AND_DIRECTORY_POINTER 581 PAGE_TABLE_ENTRY 582 VOID 583 BOOLEAN 584 PAGE_TABLE_1G_ENTRY 585 UINT64 624 if ((FeaturePcdGet (PcdDxeIplSwitchToLongMode)) || (sizeof (UINTN) == sizeof (UINT64))) { 625 UINT32 RegEax; 626 UINT32 RegEdx; 627 UINT8 PhysicalAddressBits; 628 EFI_PHYSICAL_ADDRESS PageAddress; 629 UINTN IndexOfPml4Entries; 630 UINTN IndexOfPdpEntries; 631 UINTN IndexOfPageDirectoryEntries; 632 UINT32 NumberOfPml4EntriesNeeded; 633 UINT32 NumberOfPdpEntriesNeeded; 634 PAGE_MAP_AND_DIRECTORY_POINTER *PageMapLevel4Entry; 635 PAGE_MAP_AND_DIRECTORY_POINTER *PageMap; 636 PAGE_MAP_AND_DIRECTORY_POINTER *PageDirectoryPointerEntry; 637 PAGE_TABLE_ENTRY *PageDirectoryEntry; 638 VOID *Hob; 639 BOOLEAN Page1GSupport; 640 PAGE_TABLE_1G_ENTRY *PageDirectory1GEntry; 641 UINT64 AddressEncMask; 586 642 587 643 // … … 601 657 // By architecture only one PageMapLevel4 exists - so lets allocate storage for it. 602 658 // 603 PageMap = (PAGE_MAP_AND_DIRECTORY_POINTER *)S3NvsPageTableAddress;659 PageMap = (PAGE_MAP_AND_DIRECTORY_POINTER *)S3NvsPageTableAddress; 604 660 S3NvsPageTableAddress += SIZE_4KB; 605 661 606 662 Page1GSupport = FALSE; 607 if (PcdGetBool (PcdUse1GPageTable)) {663 if (PcdGetBool (PcdUse1GPageTable)) { 608 664 AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL); 609 665 if (RegEax >= 0x80000001) { … … 620 676 Hob = GetFirstHob (EFI_HOB_TYPE_CPU); 621 677 if (Hob != NULL) { 622 PhysicalAddressBits = ((EFI_HOB_CPU *) 678 PhysicalAddressBits = ((EFI_HOB_CPU *)Hob)->SizeOfMemorySpace; 623 679 } else { 624 680 AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL); 625 681 if (RegEax >= 0x80000008) { 626 682 AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL); 627 PhysicalAddressBits = (UINT8) 683 PhysicalAddressBits = (UINT8)RegEax; 628 684 } else { 629 685 PhysicalAddressBits = 36; … … 645 701 if (Build4GPageTableOnly) { 646 702 PhysicalAddressBits = 32; 647 ZeroMem (PageMap, EFI_PAGES_TO_SIZE(2)); 648 } 703 ZeroMem (PageMap, EFI_PAGES_TO_SIZE (2)); 704 } 705 649 706 // 650 707 // Calculate the table entries needed. … … 652 709 if (PhysicalAddressBits <= 39) { 653 710 NumberOfPml4EntriesNeeded = 1; 654 NumberOfPdpEntriesNeeded = (UINT32)LShiftU64 (1, (PhysicalAddressBits - 30));711 NumberOfPdpEntriesNeeded = (UINT32)LShiftU64 (1, (PhysicalAddressBits - 30)); 655 712 } else { 656 713 NumberOfPml4EntriesNeeded = (UINT32)LShiftU64 (1, (PhysicalAddressBits - 39)); 657 NumberOfPdpEntriesNeeded = 512;714 NumberOfPdpEntriesNeeded = 512; 658 715 } 659 716 … … 666 723 // 667 724 PageDirectoryPointerEntry = (PAGE_MAP_AND_DIRECTORY_POINTER *)S3NvsPageTableAddress; 668 S3NvsPageTableAddress += SIZE_4KB;725 S3NvsPageTableAddress += SIZE_4KB; 669 726 670 727 // 671 728 // Make a PML4 Entry 672 729 // 673 PageMapLevel4Entry->Uint64 = (UINT64)(UINTN)PageDirectoryPointerEntry | AddressEncMask;730 PageMapLevel4Entry->Uint64 = (UINT64)(UINTN)PageDirectoryPointerEntry | AddressEncMask; 674 731 PageMapLevel4Entry->Bits.ReadWrite = 1; 675 PageMapLevel4Entry->Bits.Present = 1;732 PageMapLevel4Entry->Bits.Present = 1; 676 733 677 734 if (Page1GSupport) { 678 PageDirectory1GEntry = (VOID *) 735 PageDirectory1GEntry = (VOID *)PageDirectoryPointerEntry; 679 736 680 737 for (IndexOfPageDirectoryEntries = 0; IndexOfPageDirectoryEntries < 512; IndexOfPageDirectoryEntries++, PageDirectory1GEntry++, PageAddress += SIZE_1GB) { … … 682 739 // Fill in the Page Directory entries 683 740 // 684 PageDirectory1GEntry->Uint64 = (UINT64)PageAddress | AddressEncMask;741 PageDirectory1GEntry->Uint64 = (UINT64)PageAddress | AddressEncMask; 685 742 PageDirectory1GEntry->Bits.ReadWrite = 1; 686 PageDirectory1GEntry->Bits.Present = 1;687 PageDirectory1GEntry->Bits.MustBe1 = 1;743 PageDirectory1GEntry->Bits.Present = 1; 744 PageDirectory1GEntry->Bits.MustBe1 = 1; 688 745 } 689 746 } else { … … 693 750 // So allocate space for them and fill them in in the IndexOfPageDirectoryEntries loop. 694 751 // 695 PageDirectoryEntry = (PAGE_TABLE_ENTRY *)S3NvsPageTableAddress;752 PageDirectoryEntry = (PAGE_TABLE_ENTRY *)S3NvsPageTableAddress; 696 753 S3NvsPageTableAddress += SIZE_4KB; 697 754 … … 699 756 // Fill in a Page Directory Pointer Entries 700 757 // 701 PageDirectoryPointerEntry->Uint64 = (UINT64)(UINTN)PageDirectoryEntry | AddressEncMask;758 PageDirectoryPointerEntry->Uint64 = (UINT64)(UINTN)PageDirectoryEntry | AddressEncMask; 702 759 PageDirectoryPointerEntry->Bits.ReadWrite = 1; 703 PageDirectoryPointerEntry->Bits.Present = 1;760 PageDirectoryPointerEntry->Bits.Present = 1; 704 761 705 762 for (IndexOfPageDirectoryEntries = 0; IndexOfPageDirectoryEntries < 512; IndexOfPageDirectoryEntries++, PageDirectoryEntry++, PageAddress += SIZE_2MB) { … … 707 764 // Fill in the Page Directory entries 708 765 // 709 PageDirectoryEntry->Uint64 = (UINT64)PageAddress | AddressEncMask;766 PageDirectoryEntry->Uint64 = (UINT64)PageAddress | AddressEncMask; 710 767 PageDirectoryEntry->Bits.ReadWrite = 1; 711 PageDirectoryEntry->Bits.Present = 1;712 PageDirectoryEntry->Bits.MustBe1 = 1;768 PageDirectoryEntry->Bits.Present = 1; 769 PageDirectoryEntry->Bits.MustBe1 = 1; 713 770 } 714 771 } 715 772 } 716 773 } 717 return ; 774 775 return; 718 776 } else { 719 777 // 720 778 // If DXE is running 32-bit mode, no need to establish page table. 721 779 // 722 return 780 return; 723 781 } 724 782 } … … 740 798 ) 741 799 { 742 EFI_STATUS 743 PEI_SMM_ACCESS_PPI 744 UINTN 745 VOID 746 PEI_S3_RESUME_STATE 747 BOOLEAN 800 EFI_STATUS Status; 801 PEI_SMM_ACCESS_PPI *SmmAccess; 802 UINTN Index; 803 VOID *GuidHob; 804 PEI_S3_RESUME_STATE *PeiS3ResumeState; 805 BOOLEAN InterruptStatus; 748 806 749 807 DEBUG ((DEBUG_INFO, "S3ResumeExecuteBootScript()\n")); … … 768 826 769 827 Status = PeiServicesLocatePpi ( 770 771 772 773 (VOID **)&SmmAccess774 828 &gPeiSmmAccessPpiGuid, 829 0, 830 NULL, 831 (VOID **)&SmmAccess 832 ); 775 833 if (!EFI_ERROR (Status)) { 776 834 DEBUG ((DEBUG_INFO, "Close all SMRAM regions before executing boot script\n")); … … 799 857 } 800 858 801 if ( FeaturePcdGet (PcdDxeIplSwitchToLongMode)) {859 if ((FeaturePcdGet (PcdDxeIplSwitchToLongMode)) || (sizeof (UINTN) == sizeof (UINT64))) { 802 860 AsmWriteCr3 ((UINTN)AcpiS3Context->S3NvsPageTableAddress); 803 861 } … … 820 878 // Prepare data for return back 821 879 // 822 PeiS3ResumeState = AllocatePool (sizeof (*PeiS3ResumeState));880 PeiS3ResumeState = AllocatePool (sizeof (*PeiS3ResumeState)); 823 881 if (PeiS3ResumeState == NULL) { 824 882 REPORT_STATUS_CODE ( … … 828 886 ASSERT (FALSE); 829 887 } 888 830 889 DEBUG ((DEBUG_INFO, "PeiS3ResumeState - %x\r\n", PeiS3ResumeState)); 831 890 PeiS3ResumeState->ReturnCs = 0x10; … … 866 925 DEBUG ((DEBUG_INFO, "transfer control to Standalone Boot Script Executor\r\n")); 867 926 SwitchStack ( 868 (SWITCH_STACK_ENTRY_POINT) (UINTN)EfiBootScriptExecutorVariable->BootScriptExecutorEntrypoint,927 (SWITCH_STACK_ENTRY_POINT)(UINTN)EfiBootScriptExecutorVariable->BootScriptExecutorEntrypoint, 869 928 (VOID *)AcpiS3Context, 870 929 (VOID *)PeiS3ResumeState, … … 876 935 // Never run to here 877 936 // 878 CpuDeadLoop ();937 CpuDeadLoop (); 879 938 } 939 880 940 /** 881 941 Restores the platform to its preboot configuration for an S3 resume and … … 915 975 ) 916 976 { 917 EFI_STATUS 918 PEI_SMM_ACCESS_PPI 919 UINTN 920 ACPI_S3_CONTEXT 921 EFI_PHYSICAL_ADDRESS 922 EFI_PHYSICAL_ADDRESS 923 BOOT_SCRIPT_EXECUTOR_VARIABLE 924 UINTN 925 EFI_SMRAM_DESCRIPTOR 926 SMM_S3_RESUME_STATE 927 VOID 928 BOOLEAN 929 BOOLEAN 930 IA32_CR0 931 932 TempAcpiS3Context = 0;977 EFI_STATUS Status; 978 PEI_SMM_ACCESS_PPI *SmmAccess; 979 UINTN Index; 980 ACPI_S3_CONTEXT *AcpiS3Context; 981 EFI_PHYSICAL_ADDRESS TempEfiBootScriptExecutorVariable; 982 EFI_PHYSICAL_ADDRESS TempAcpiS3Context; 983 BOOT_SCRIPT_EXECUTOR_VARIABLE *EfiBootScriptExecutorVariable; 984 UINTN VarSize; 985 EFI_SMRAM_DESCRIPTOR *SmramDescriptor; 986 SMM_S3_RESUME_STATE *SmmS3ResumeState; 987 VOID *GuidHob; 988 BOOLEAN Build4GPageTableOnly; 989 BOOLEAN InterruptStatus; 990 IA32_CR0 Cr0; 991 992 TempAcpiS3Context = 0; 933 993 TempEfiBootScriptExecutorVariable = 0; 934 994 … … 936 996 937 997 VarSize = sizeof (EFI_PHYSICAL_ADDRESS); 938 Status = RestoreLockBox (939 &gEfiAcpiVariableGuid,940 &TempAcpiS3Context,941 &VarSize942 );998 Status = RestoreLockBox ( 999 &gEfiAcpiVariableGuid, 1000 &TempAcpiS3Context, 1001 &VarSize 1002 ); 943 1003 ASSERT_EFI_ERROR (Status); 944 1004 … … 953 1013 ASSERT (AcpiS3Context != NULL); 954 1014 955 VarSize 956 Status = RestoreLockBox (957 &gEfiBootScriptExecutorVariableGuid,958 &TempEfiBootScriptExecutorVariable,959 &VarSize960 );1015 VarSize = sizeof (EFI_PHYSICAL_ADDRESS); 1016 Status = RestoreLockBox ( 1017 &gEfiBootScriptExecutorVariableGuid, 1018 &TempEfiBootScriptExecutorVariable, 1019 &VarSize 1020 ); 961 1021 ASSERT_EFI_ERROR (Status); 962 1022 … … 968 1028 ASSERT_EFI_ERROR (Status); 969 1029 970 EfiBootScriptExecutorVariable = (BOOT_SCRIPT_EXECUTOR_VARIABLE *) (UINTN)TempEfiBootScriptExecutorVariable;1030 EfiBootScriptExecutorVariable = (BOOT_SCRIPT_EXECUTOR_VARIABLE *)(UINTN)TempEfiBootScriptExecutorVariable; 971 1031 ASSERT (EfiBootScriptExecutorVariable != NULL); 972 1032 973 DEBUG (( 974 DEBUG (( DEBUG_INFO, "Waking Vector = %x\n", ((EFI_ACPI_2_0_FIRMWARE_ACPI_CONTROL_STRUCTURE *) ((UINTN)(AcpiS3Context->AcpiFacsTable)))->FirmwareWakingVector));975 DEBUG (( 976 DEBUG (( 977 DEBUG (( 978 DEBUG (( 979 DEBUG (( 980 DEBUG (( 981 DEBUG (( 1033 DEBUG ((DEBUG_INFO, "AcpiS3Context = %x\n", AcpiS3Context)); 1034 DEBUG ((DEBUG_INFO, "Waking Vector = %x\n", ((EFI_ACPI_2_0_FIRMWARE_ACPI_CONTROL_STRUCTURE *)((UINTN)(AcpiS3Context->AcpiFacsTable)))->FirmwareWakingVector)); 1035 DEBUG ((DEBUG_INFO, "AcpiS3Context->AcpiFacsTable = %x\n", AcpiS3Context->AcpiFacsTable)); 1036 DEBUG ((DEBUG_INFO, "AcpiS3Context->IdtrProfile = %x\n", AcpiS3Context->IdtrProfile)); 1037 DEBUG ((DEBUG_INFO, "AcpiS3Context->S3NvsPageTableAddress = %x\n", AcpiS3Context->S3NvsPageTableAddress)); 1038 DEBUG ((DEBUG_INFO, "AcpiS3Context->S3DebugBufferAddress = %x\n", AcpiS3Context->S3DebugBufferAddress)); 1039 DEBUG ((DEBUG_INFO, "AcpiS3Context->BootScriptStackBase = %x\n", AcpiS3Context->BootScriptStackBase)); 1040 DEBUG ((DEBUG_INFO, "AcpiS3Context->BootScriptStackSize = %x\n", AcpiS3Context->BootScriptStackSize)); 1041 DEBUG ((DEBUG_INFO, "EfiBootScriptExecutorVariable->BootScriptExecutorEntrypoint = %x\n", EfiBootScriptExecutorVariable->BootScriptExecutorEntrypoint)); 982 1042 983 1043 // … … 993 1053 } 994 1054 995 if ( FeaturePcdGet (PcdDxeIplSwitchToLongMode)) {1055 if ((FeaturePcdGet (PcdDxeIplSwitchToLongMode)) || (sizeof (UINTN) == sizeof (UINT64))) { 996 1056 // 997 1057 // Need reconstruct page table here, since we do not trust ACPINvs. … … 1002 1062 Build4GPageTableOnly = TRUE; 1003 1063 } 1064 1004 1065 RestoreS3PageTables ((UINTN)AcpiS3Context->S3NvsPageTableAddress, Build4GPageTableOnly); 1005 1066 } … … 1010 1071 GuidHob = GetFirstGuidHob (&gEfiAcpiVariableGuid); 1011 1072 if (GuidHob != NULL) { 1012 //1013 // Below SwitchStack/AsmEnablePaging64 function has1014 // assumption that it's in 32 bits mode now.1015 // Add ASSERT code to indicate this assumption.1016 //1017 ASSERT(sizeof (UINTN) == sizeof (UINT32));1018 1019 1073 Status = PeiServicesLocatePpi ( 1020 1021 1022 1023 (VOID **)&SmmAccess1024 1074 &gPeiSmmAccessPpiGuid, 1075 0, 1076 NULL, 1077 (VOID **)&SmmAccess 1078 ); 1025 1079 for (Index = 0; !EFI_ERROR (Status); Index++) { 1026 1080 Status = SmmAccess->Open ((EFI_PEI_SERVICES **)GetPeiServicesTablePointer (), SmmAccess, Index); 1027 1081 } 1028 1082 1029 SmramDescriptor = (EFI_SMRAM_DESCRIPTOR *)GET_GUID_HOB_DATA (GuidHob);1083 SmramDescriptor = (EFI_SMRAM_DESCRIPTOR *)GET_GUID_HOB_DATA (GuidHob); 1030 1084 SmmS3ResumeState = (SMM_S3_RESUME_STATE *)(UINTN)SmramDescriptor->CpuStart; 1031 1085 … … 1036 1090 SmmS3ResumeState->ReturnStackPointer = (EFI_PHYSICAL_ADDRESS)STACK_ALIGN_DOWN (&Status); 1037 1091 1038 DEBUG (( DEBUG_INFO, "SMM S3 Signature = %x\n", SmmS3ResumeState->Signature)); 1039 DEBUG (( DEBUG_INFO, "SMM S3 Stack Base = %x\n", SmmS3ResumeState->SmmS3StackBase)); 1040 DEBUG (( DEBUG_INFO, "SMM S3 Stack Size = %x\n", SmmS3ResumeState->SmmS3StackSize)); 1041 DEBUG (( DEBUG_INFO, "SMM S3 Resume Entry Point = %x\n", SmmS3ResumeState->SmmS3ResumeEntryPoint)); 1042 DEBUG (( DEBUG_INFO, "SMM S3 CR0 = %x\n", SmmS3ResumeState->SmmS3Cr0)); 1043 DEBUG (( DEBUG_INFO, "SMM S3 CR3 = %x\n", SmmS3ResumeState->SmmS3Cr3)); 1044 DEBUG (( DEBUG_INFO, "SMM S3 CR4 = %x\n", SmmS3ResumeState->SmmS3Cr4)); 1045 DEBUG (( DEBUG_INFO, "SMM S3 Return CS = %x\n", SmmS3ResumeState->ReturnCs)); 1046 DEBUG (( DEBUG_INFO, "SMM S3 Return Entry Point = %x\n", SmmS3ResumeState->ReturnEntryPoint)); 1047 DEBUG (( DEBUG_INFO, "SMM S3 Return Context1 = %x\n", SmmS3ResumeState->ReturnContext1)); 1048 DEBUG (( DEBUG_INFO, "SMM S3 Return Context2 = %x\n", SmmS3ResumeState->ReturnContext2)); 1049 DEBUG (( DEBUG_INFO, "SMM S3 Return Stack Pointer = %x\n", SmmS3ResumeState->ReturnStackPointer)); 1050 DEBUG (( DEBUG_INFO, "SMM S3 Smst = %x\n", SmmS3ResumeState->Smst)); 1051 1052 if (SmmS3ResumeState->Signature == SMM_S3_RESUME_SMM_32) { 1092 DEBUG ((DEBUG_INFO, "SMM S3 Signature = %x\n", SmmS3ResumeState->Signature)); 1093 DEBUG ((DEBUG_INFO, "SMM S3 Stack Base = %x\n", SmmS3ResumeState->SmmS3StackBase)); 1094 DEBUG ((DEBUG_INFO, "SMM S3 Stack Size = %x\n", SmmS3ResumeState->SmmS3StackSize)); 1095 DEBUG ((DEBUG_INFO, "SMM S3 Resume Entry Point = %x\n", SmmS3ResumeState->SmmS3ResumeEntryPoint)); 1096 DEBUG ((DEBUG_INFO, "SMM S3 CR0 = %x\n", SmmS3ResumeState->SmmS3Cr0)); 1097 DEBUG ((DEBUG_INFO, "SMM S3 CR3 = %x\n", SmmS3ResumeState->SmmS3Cr3)); 1098 DEBUG ((DEBUG_INFO, "SMM S3 CR4 = %x\n", SmmS3ResumeState->SmmS3Cr4)); 1099 DEBUG ((DEBUG_INFO, "SMM S3 Return CS = %x\n", SmmS3ResumeState->ReturnCs)); 1100 DEBUG ((DEBUG_INFO, "SMM S3 Return Entry Point = %x\n", SmmS3ResumeState->ReturnEntryPoint)); 1101 DEBUG ((DEBUG_INFO, "SMM S3 Return Context1 = %x\n", SmmS3ResumeState->ReturnContext1)); 1102 DEBUG ((DEBUG_INFO, "SMM S3 Return Context2 = %x\n", SmmS3ResumeState->ReturnContext2)); 1103 DEBUG ((DEBUG_INFO, "SMM S3 Return Stack Pointer = %x\n", SmmS3ResumeState->ReturnStackPointer)); 1104 DEBUG ((DEBUG_INFO, "SMM S3 Smst = %x\n", SmmS3ResumeState->Smst)); 1105 1106 // 1107 // Directly do the switch stack when PEI and SMM env run in the same execution mode. 1108 // 1109 if (((SmmS3ResumeState->Signature == SMM_S3_RESUME_SMM_32) && (sizeof (UINTN) == sizeof (UINT32))) || 1110 ((SmmS3ResumeState->Signature == SMM_S3_RESUME_SMM_64) && (sizeof (UINTN) == sizeof (UINT64)))) 1111 { 1053 1112 SwitchStack ( 1054 1113 (SWITCH_STACK_ENTRY_POINT)(UINTN)SmmS3ResumeState->SmmS3ResumeEntryPoint, … … 1058 1117 ); 1059 1118 } 1119 1060 1120 if (SmmS3ResumeState->Signature == SMM_S3_RESUME_SMM_64) { 1061 1121 // … … 1086 1146 AsmWriteCr0 (Cr0.UintN); 1087 1147 } 1148 1088 1149 AsmWriteCr3 ((UINTN)SmmS3ResumeState->SmmS3Cr3); 1089 1150 … … 1103 1164 ); 1104 1165 } 1105 1106 } 1107 1108 S3ResumeExecuteBootScript (AcpiS3Context, EfiBootScriptExecutorVariable ); 1166 } 1167 1168 S3ResumeExecuteBootScript (AcpiS3Context, EfiBootScriptExecutorVariable); 1109 1169 return EFI_SUCCESS; 1110 1170 } 1171 1111 1172 /** 1112 1173 Main entry for S3 Resume PEIM. … … 1123 1184 EFIAPI 1124 1185 PeimS3ResumeEntryPoint ( 1125 IN EFI_PEI_FILE_HANDLE 1126 IN CONST EFI_PEI_SERVICES 1186 IN EFI_PEI_FILE_HANDLE FileHandle, 1187 IN CONST EFI_PEI_SERVICES **PeiServices 1127 1188 ) 1128 1189 { … … 1137 1198 return EFI_SUCCESS; 1138 1199 } 1139 -
trunk/src/VBox/Devices/EFI/FirmwareNew/UefiCpuPkg/Universal/Acpi/S3Resume2Pei/X64/AsmFuncs.nasm
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