Changeset 99492 in vbox for trunk/src/VBox/VMM

Timestamp:

Apr 20, 2023 7:21:44 PM (20 months ago)

Author:

vboxsync

Message:

VMM/GIC: Register the MMIO region handlers for the distributor and redisitributor frames, this is already enough for the UEFI firmware to not assert and continue with initialization, bugref:10404

Location:

trunk/src/VBox/VMM

Files:

• VMMAll/GICAll.cpp (modified) (2 diffs)
• VMMR3/GICR3.cpp (modified) (1 diff)
• include/GICInternal.h (added)

trunk/src/VBox/VMM/VMMAll/GICAll.cpp

@@ -148 +148 @@
  * @callback_method_impl{FNIOMMMIONEWREAD}
  */
-DECLCALLBACK(VBOXSTRICTRC) apicReadMmio(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void *pv, unsigned cb)
+DECL_HIDDEN_CALLBACK(VBOXSTRICTRC) gicDistMmioRead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void *pv, unsigned cb)
 {
     NOREF(pvUser);
-    Assert(!(off & 0xf));
-    Assert(cb == 4); RT_NOREF_PV(cb);
+    //Assert(!(off & 0xf));
+    //Assert(cb == 4); RT_NOREF_PV(cb);
 
     PVMCPUCC pVCpu    = PDMDevHlpGetVMCPU(pDevIns);
@@ -171 +171 @@
  * @callback_method_impl{FNIOMMMIONEWWRITE}
  */
-DECLCALLBACK(VBOXSTRICTRC) gicWriteMmio(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void const *pv, unsigned cb)
+DECL_HIDDEN_CALLBACK(VBOXSTRICTRC) gicDistMmioWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void const *pv, unsigned cb)
 {
     NOREF(pvUser);
-    Assert(!(off & 0xf));
-    Assert(cb == 4); RT_NOREF_PV(cb);
+    //Assert(!(off & 0xf));
+    //Assert(cb == 4); RT_NOREF_PV(cb);
+
+    PVMCPUCC pVCpu    = PDMDevHlpGetVMCPU(pDevIns);
+    uint16_t offReg   = off & 0xff0;
+    uint32_t uValue   = *(uint32_t *)pv;
+
+    STAM_COUNTER_INC(&pVCpu->gic.s.CTX_SUFF_Z(StatMmioWrite));
+
+    Log2(("GIC%u: gicWriteMmio: offReg=%#RX16 uValue=%#RX32\n", pVCpu->idCpu, offReg, uValue));
+    return gicWriteRegister(pDevIns, pVCpu, offReg, uValue);
+}
+
+
+/**
+ * @callback_method_impl{FNIOMMMIONEWREAD}
+ */
+DECL_HIDDEN_CALLBACK(VBOXSTRICTRC) gicReDistMmioRead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void *pv, unsigned cb)
+{
+    NOREF(pvUser);
+    //Assert(!(off & 0xf));
+    //Assert(cb == 4); RT_NOREF_PV(cb);
+
+    PVMCPUCC pVCpu    = PDMDevHlpGetVMCPU(pDevIns);
+    uint16_t offReg   = off & 0xff0;
+    uint32_t uValue   = 0;
+
+    STAM_COUNTER_INC(&pVCpu->gic.s.CTX_SUFF_Z(StatMmioRead));
+
+    VBOXSTRICTRC rc = VBOXSTRICTRC_VAL(gicReadRegister(pDevIns, pVCpu, offReg, &uValue));
+    *(uint32_t *)pv = uValue;
+
+    Log2(("GIC%u: gicReadMmio: offReg=%#RX16 uValue=%#RX32\n", pVCpu->idCpu, offReg, uValue));
+    return rc;
+}
+
+
+/**
+ * @callback_method_impl{FNIOMMMIONEWWRITE}
+ */
+DECL_HIDDEN_CALLBACK(VBOXSTRICTRC) gicReDistMmioWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void const *pv, unsigned cb)
+{
+    NOREF(pvUser);
+    //Assert(!(off & 0xf));
+    //Assert(cb == 4); RT_NOREF_PV(cb);
 
     PVMCPUCC pVCpu    = PDMDevHlpGetVMCPU(pDevIns);

trunk/src/VBox/VMM/VMMR3/GICR3.cpp

@@ -176 +176 @@
      * Register the MMIO ranges.
      */
-#if 0
-    rc = PDMDevHlpMmioCreateAndMap(pDevIns, GCPhysApicBase, sizeof(XAPICPAGE), apicWriteMmio, apicReadMmio,
-                                   IOMMMIO_FLAGS_READ_DWORD | IOMMMIO_FLAGS_WRITE_DWORD_ZEROED, "APIC", &pApicDev->hMmio);
-    AssertRCReturn(rc, rc);
-#endif
+    RTGCPHYS GCPhysMmioBase = 0;
+    rc = pHlp->pfnCFGMQueryU64(pCfg, "DistributorMmioBase", &GCPhysMmioBase);
+    if (RT_FAILURE(rc))
+        return PDMDEV_SET_ERROR(pDevIns, rc,
+                                N_("Configuration error: Failed to get the \"DistributorMmioBase\" value"));
+
+    rc = PDMDevHlpMmioCreateAndMap(pDevIns, GCPhysMmioBase, GIC_DIST_REG_FRAME_SIZE, gicDistMmioWrite, gicDistMmioRead,
+                                   IOMMMIO_FLAGS_READ_DWORD | IOMMMIO_FLAGS_WRITE_DWORD_ZEROED, "GICv3_Dist", &pGicDev->hMmioDist);
+    AssertRCReturn(rc, rc);
+
+    rc = pHlp->pfnCFGMQueryU64(pCfg, "RedistributorMmioBase", &GCPhysMmioBase);
+    if (RT_FAILURE(rc))
+        return PDMDEV_SET_ERROR(pDevIns, rc,
+                                N_("Configuration error: Failed to get the \"RedistributorMmioBase\" value"));
+
+    RTGCPHYS cbRegion = pVM->cCpus * (GIC_REDIST_REG_FRAME_SIZE + GIC_REDIST_SGI_PPI_REG_FRAME_SIZE); /* Adjacent and per vCPU. */
+    rc = PDMDevHlpMmioCreateAndMap(pDevIns, GCPhysMmioBase, cbRegion, gicReDistMmioWrite, gicReDistMmioRead,
+                                   IOMMMIO_FLAGS_READ_DWORD | IOMMMIO_FLAGS_WRITE_DWORD_ZEROED, "GICv3_ReDist", &pGicDev->hMmioReDist);
+    AssertRCReturn(rc, rc);
 
     /*