VirtualBox

Changeset 99576 in vbox


Ignore:
Timestamp:
May 3, 2023 10:24:27 AM (22 months ago)
Author:
vboxsync
svn:sync-xref-src-repo-rev:
157093
Message:

VMM: Preparations for getting interrupts injected into the guest. With ARMv8 there are two types of interrupts (normal interrupts and fast interrupts) which need to be mapped to forced action flags. Because the PIC and APIC flags are not needed those are mapped to IRQs and FIQs on ARM respectively, bugref:10389

Location:
trunk
Files:
10 edited

Legend:

Unmodified
Added
Removed

  • trunk/include/VBox/vmm/cpum-armv8.h

    r99385 r99576  
    274274/** @name Guest Register Getters.
    275275 * @{ */
     276VMMDECL(bool)           CPUMGetGuestIrqMasked(PVMCPUCC pVCpu);
     277VMMDECL(bool)           CPUMGetGuestFiqMasked(PVMCPUCC pVCpu);
    276278VMMDECL(VBOXSTRICTRC)   CPUMQueryGuestSysReg(PVMCPUCC pVCpu, uint32_t idSysReg, uint64_t *puValue);
     279/** @} */
     280
     281
     282/** @name Guest Register Setters.
     283 * @{ */
    277284VMMDECL(VBOXSTRICTRC)   CPUMSetGuestSysReg(PVMCPUCC pVCpu, uint32_t idSysReg, uint64_t uValue);
    278285/** @} */

  • trunk/include/VBox/vmm/vm.h

    r99385 r99576  
    459459
    460460
     461#if defined(VBOX_VMM_TARGET_ARMV8)
     462/** This action forces the VM to inject an IRQ into the guest. */
     463# define VMCPU_FF_INTERRUPT_IRQ              RT_BIT_64(VMCPU_FF_INTERRUPT_IRQ_BIT)
     464# define VMCPU_FF_INTERRUPT_IRQ_BIT          0
     465/** This action forces the VM to inject an FIQ into the guest. */
     466# define VMCPU_FF_INTERRUPT_FIQ              RT_BIT_64(VMCPU_FF_INTERRUPT_FIQ_BIT)
     467# define VMCPU_FF_INTERRUPT_FIQ_BIT          1
     468#else
    461469/** This action forces the VM to check any pending interrupts on the APIC. */
    462 #define VMCPU_FF_INTERRUPT_APIC             RT_BIT_64(VMCPU_FF_INTERRUPT_APIC_BIT)
    463 #define VMCPU_FF_INTERRUPT_APIC_BIT         0
     470# define VMCPU_FF_INTERRUPT_APIC             RT_BIT_64(VMCPU_FF_INTERRUPT_APIC_BIT)
     471# define VMCPU_FF_INTERRUPT_APIC_BIT         0
    464472/** This action forces the VM to check any pending interrups on the PIC. */
    465 #define VMCPU_FF_INTERRUPT_PIC              RT_BIT_64(VMCPU_FF_INTERRUPT_PIC_BIT)
    466 #define VMCPU_FF_INTERRUPT_PIC_BIT          1
     473# define VMCPU_FF_INTERRUPT_PIC              RT_BIT_64(VMCPU_FF_INTERRUPT_PIC_BIT)
     474# define VMCPU_FF_INTERRUPT_PIC_BIT          1
     475#endif
    467476/** This action forces the VM to schedule and run pending timer (TM).
    468477 * @remarks Don't move - PATM compatibility.  */
    … …  
    581590                                                 | VM_FF_PDM_QUEUES     | VM_FF_PDM_DMA | VM_FF_EMT_RENDEZVOUS )
    582591/** Externally forced VMCPU actions. Used to quit the idle/wait loop. */
    583 #define VMCPU_FF_EXTERNAL_HALTED_MASK           (  VMCPU_FF_UPDATE_APIC | VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC \
     592#if defined(VBOX_VMM_TARGET_ARMV8)
     593# define VMCPU_FF_EXTERNAL_HALTED_MASK          (  VMCPU_FF_INTERRUPT_IRQ | VMCPU_FF_INTERRUPT_FIQ \
     594                                                 | VMCPU_FF_REQUEST       | VMCPU_FF_INTERRUPT_NMI  | VMCPU_FF_INTERRUPT_SMI \
     595                                                 | VMCPU_FF_UNHALT        | VMCPU_FF_TIMER          | VMCPU_FF_DBGF )
     596#else
     597# define VMCPU_FF_EXTERNAL_HALTED_MASK          (  VMCPU_FF_UPDATE_APIC | VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC \
    584598                                                 | VMCPU_FF_REQUEST     | VMCPU_FF_INTERRUPT_NMI  | VMCPU_FF_INTERRUPT_SMI \
    585599                                                 | VMCPU_FF_UNHALT      | VMCPU_FF_TIMER          | VMCPU_FF_DBGF \
    586600                                                 | VMCPU_FF_INTERRUPT_NESTED_GUEST)
     601#endif
    587602
    588603/** High priority VM pre-execution actions. */
    … …  
    591606                                                 | VM_FF_EMT_RENDEZVOUS )
    592607/** High priority VMCPU pre-execution actions. */
    593 #define VMCPU_FF_HIGH_PRIORITY_PRE_MASK         (  VMCPU_FF_TIMER        | VMCPU_FF_INTERRUPT_APIC     | VMCPU_FF_INTERRUPT_PIC \
    594                                                  | VMCPU_FF_UPDATE_APIC  | VMCPU_FF_DBGF \
    595                                                  | VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \
    596                                                  | VMCPU_FF_INTERRUPT_NESTED_GUEST | VMCPU_FF_VMX_MTF  | VMCPU_FF_VMX_APIC_WRITE \
    597                                                  | VMCPU_FF_VMX_PREEMPT_TIMER | VMCPU_FF_VMX_NMI_WINDOW | VMCPU_FF_VMX_INT_WINDOW )
     608#if defined(VBOX_VMM_TARGET_ARMV8)
     609# define VMCPU_FF_HIGH_PRIORITY_PRE_MASK         (  VMCPU_FF_TIMER        | VMCPU_FF_INTERRUPT_IRQ     | VMCPU_FF_INTERRUPT_FIQ \
     610                                                  | VMCPU_FF_DBGF )
     611#else
     612# define VMCPU_FF_HIGH_PRIORITY_PRE_MASK         (  VMCPU_FF_TIMER        | VMCPU_FF_INTERRUPT_APIC     | VMCPU_FF_INTERRUPT_PIC \
     613                                                  | VMCPU_FF_UPDATE_APIC  | VMCPU_FF_DBGF \
     614                                                  | VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL \
     615                                                  | VMCPU_FF_INTERRUPT_NESTED_GUEST | VMCPU_FF_VMX_MTF  | VMCPU_FF_VMX_APIC_WRITE \
     616                                                  | VMCPU_FF_VMX_PREEMPT_TIMER | VMCPU_FF_VMX_NMI_WINDOW | VMCPU_FF_VMX_INT_WINDOW )
     617#endif
    598618
    599619/** High priority VM pre raw-mode execution mask. */
    … …  
    636656                                                  | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL | VMCPU_FF_DBGF | VMCPU_FF_VMX_MTF )
    637657#endif
     658
     659#if !defined(VBOX_VMM_TARGET_ARMV8)
    638660/** VMCPU flags that cause the REP[|NE|E] STRINS loops to yield, interrupts
    639661 *  enabled. */
    640 #define VMCPU_FF_YIELD_REPSTR_MASK              (  VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK \
    641                                                  | VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_UPDATE_APIC   | VMCPU_FF_INTERRUPT_PIC \
    642                                                  | VMCPU_FF_INTERRUPT_NMI  | VMCPU_FF_INTERRUPT_SMI | VMCPU_FF_PDM_CRITSECT \
    643                                                  | VMCPU_FF_TIMER          | VMCPU_FF_REQUEST       \
    644                                                  | VMCPU_FF_INTERRUPT_NESTED_GUEST )
     662# define VMCPU_FF_YIELD_REPSTR_MASK              (  VMCPU_FF_HIGH_PRIORITY_POST_REPSTR_MASK \
     663                                                  | VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_UPDATE_APIC   | VMCPU_FF_INTERRUPT_PIC \
     664                                                  | VMCPU_FF_INTERRUPT_NMI  | VMCPU_FF_INTERRUPT_SMI | VMCPU_FF_PDM_CRITSECT \
     665                                                  | VMCPU_FF_TIMER          | VMCPU_FF_REQUEST       \
     666                                                  | VMCPU_FF_INTERRUPT_NESTED_GUEST )
    645667/** VMCPU flags that cause the REP[|NE|E] STRINS loops to yield, interrupts
    646668 *  disabled. */
    647 #define VMCPU_FF_YIELD_REPSTR_NOINT_MASK        (  VMCPU_FF_YIELD_REPSTR_MASK \
    648                                                  & ~(  VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_UPDATE_APIC | VMCPU_FF_INTERRUPT_PIC \
    649                                                      | VMCPU_FF_INTERRUPT_NESTED_GUEST) )
     669# define VMCPU_FF_YIELD_REPSTR_NOINT_MASK        (  VMCPU_FF_YIELD_REPSTR_MASK \
     670                                                  & ~(  VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_UPDATE_APIC | VMCPU_FF_INTERRUPT_PIC \
     671                                                      | VMCPU_FF_INTERRUPT_NESTED_GUEST) )
     672#endif
    650673
    651674/** VM Flags that cause the HM loops to go back to ring-3. */

  • trunk/include/VBox/vmm/vmapi.h

    r98644 r99576  
    463463VMMR3_INT_DECL(void)        VMR3NotifyCpuFFU(PUVMCPU pUVMCpu, uint32_t fFlags);
    464464VMMR3DECL(int)              VMR3NotifyCpuDeviceReady(PVM pVM, VMCPUID idCpu);
    465 VMMR3_INT_DECL(int)         VMR3WaitHalted(PVM pVM, PVMCPU pVCpu, bool fIgnoreInterrupts);
     465
     466/** @name Flags for VMR3WaitHalted.
     467 * @{ */
     468/** Flag whether to ignore interrupts. */
     469#define VMWAITHALTED_F_IGNORE_IRQS  RT_BIT_32(0)
     470#if defined(VBOX_VMM_TARGET_ARMV8)
     471/** Flag whether to ignore fast interrupts. */
     472# define VMWAITHALTED_F_IGNORE_FIQS RT_BIT_32(1)
     473#endif
     474/** @} */
     475VMMR3_INT_DECL(int)         VMR3WaitHalted(PVM pVM, PVMCPU pVCpu, uint32_t fFlags);
     476
    466477VMMR3_INT_DECL(int)         VMR3WaitU(PUVMCPU pUVMCpu);
    467478VMMR3DECL(int)              VMR3WaitForDeviceReady(PVM pVM, VMCPUID idCpu);

  • trunk/src/VBox/VMM/VMMAll/CPUMAllRegs-armv8.cpp

    r99051 r99576  
    4646#include <VBox/vmm/hm.h>
    4747#include <VBox/vmm/tm.h>
     48
     49#include <iprt/armv8.h>
    4850#include <iprt/assert.h>
    4951#include <iprt/asm.h>
    … …  
    99101    AssertReleaseFailed(); /** @todo Exception level. */
    100102    return pVCpu->cpum.s.Guest.aSpReg[0].u64;
     103}
     104
     105
     106/**
     107 * Returns whether IRQs are currently masked.
     108 *
     109 * @returns true if IRQs are masked as indicated by the PState value.
     110 * @param   pVCpu       The cross context virtual CPU structure.
     111 */
     112VMMDECL(bool)       CPUMGetGuestIrqMasked(PVMCPUCC pVCpu)
     113{
     114    CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_PSTATE);
     115    return RT_BOOL(pVCpu->cpum.s.Guest.fPState & ARMV8_SPSR_EL2_AARCH64_I);
     116}
     117
     118
     119/**
     120 * Returns whether FIQs are currently masked.
     121 *
     122 * @returns true if FIQs are masked as indicated by the PState value.
     123 * @param   pVCpu       The cross context virtual CPU structure.
     124 */
     125VMMDECL(bool)       CPUMGetGuestFiqMasked(PVMCPUCC pVCpu)
     126{
     127    CPUM_INT_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_PSTATE);
     128    return RT_BOOL(pVCpu->cpum.s.Guest.fPState & ARMV8_SPSR_EL2_AARCH64_F);
    101129}
    102130

  • trunk/src/VBox/VMM/VMMAll/PDMAll.cpp

    r99051 r99576  
    4646
    4747
    48 
     48#if !defined(VBOX_VMM_TARGET_ARMV8)
    4949/**
    5050 * Gets the pending interrupt.
    … …  
    7070    {
    7171        VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_APIC);
    72 #if defined(VBOX_VMM_TARGET_ARMV8)
    73         AssertReleaseFailed();
    74 #else
     72
    7573        uint32_t uTagSrc;
    7674        rc = APICGetInterrupt(pVCpu, pu8Interrupt, &uTagSrc);
    … …  
    8381        /* else if it's masked by TPR/PPR/whatever, go ahead checking the PIC. Such masked
    8482           interrupts shouldn't prevent ExtINT from being delivered. */
    85 #endif
    8683    }
    8784
    … …  
    121118    return rc;
    122119}
     120#endif
    123121
    124122

  • trunk/src/VBox/VMM/VMMR3/EM.cpp

    r99220 r99576  
    21222122        /* check that we got them all  */
    21232123        AssertCompile(VM_FF_HIGH_PRIORITY_PRE_MASK == (VM_FF_TM_VIRTUAL_SYNC | VM_FF_DBGF | VM_FF_CHECK_VM_STATE | VM_FF_DEBUG_SUSPEND | VM_FF_PGM_NEED_HANDY_PAGES | VM_FF_PGM_NO_MEMORY | VM_FF_EMT_RENDEZVOUS));
     2124#if defined(VBOX_VMM_TARGET_ARMV8)
     2125        AssertCompile(VMCPU_FF_HIGH_PRIORITY_PRE_MASK == (VMCPU_FF_TIMER | VMCPU_FF_INTERRUPT_IRQ | VMCPU_FF_INTERRUPT_FIQ | VMCPU_FF_DBGF));
     2126#else
    21242127        AssertCompile(VMCPU_FF_HIGH_PRIORITY_PRE_MASK == (VMCPU_FF_TIMER | VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_UPDATE_APIC | VMCPU_FF_INTERRUPT_PIC | VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL | VMCPU_FF_DBGF | VMCPU_FF_INTERRUPT_NESTED_GUEST | VMCPU_FF_VMX_MTF | VMCPU_FF_VMX_APIC_WRITE | VMCPU_FF_VMX_PREEMPT_TIMER | VMCPU_FF_VMX_INT_WINDOW | VMCPU_FF_VMX_NMI_WINDOW));
     2128#endif
    21252129    }
    21262130
    … …  
    26732677                        {
    26742678#if defined(VBOX_VMM_TARGET_ARMV8)
    2675                             AssertReleaseFailed();
     2679                            if (VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INTERRUPT_IRQ | VMCPU_FF_INTERRUPT_FIQ
     2680                                                         | VMCPU_FF_INTERRUPT_NMI | VMCPU_FF_INTERRUPT_SMI | VMCPU_FF_UNHALT))
     2681                            {
     2682                                Log(("EMR3ExecuteVM: Triggering reschedule on pending IRQ after MWAIT\n"));
     2683                                rc = VINF_EM_RESCHEDULE;
     2684                            }
    26762685#else
    26772686                            if (VMCPU_FF_TEST_AND_CLEAR(pVCpu, VMCPU_FF_UPDATE_APIC))
    26782687                                APICUpdatePendingInterrupts(pVCpu);
    2679 #endif
    26802688
    26812689                            if (VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC
    … …  
    26862694                                rc = VINF_EM_RESCHEDULE;
    26872695                            }
     2696#endif
    26882697                        }
    26892698                    }
    … …  
    26912700                    {
    26922701#if defined(VBOX_VMM_TARGET_ARMV8)
    2693                         bool fIgnoreInterrupts = false;
    2694                         AssertReleaseFailed();
     2702                        uint32_t fWaitHalted =   (CPUMGetGuestIrqMasked(pVCpu) ? VMWAITHALTED_F_IGNORE_IRQS : 0)
     2703                                               | (CPUMGetGuestFiqMasked(pVCpu) ? VMWAITHALTED_F_IGNORE_FIQS : 0);
    26952704#else
    2696                         bool fIgnoreInterrupts = !(CPUMGetGuestEFlags(pVCpu) & X86_EFL_IF);
    2697 #endif
    2698                         rc = VMR3WaitHalted(pVM, pVCpu, fIgnoreInterrupts);
     2705                        uint32_t fWaitHalted = (CPUMGetGuestEFlags(pVCpu) & X86_EFL_IF) ? 0 : VMWAITHALTED_F_IGNORE_IRQS;
     2706#endif
     2707                        rc = VMR3WaitHalted(pVM, pVCpu, fWaitHalted);
    26992708                        /* We're only interested in NMI/SMIs here which have their own FFs, so we don't need to
    27002709                           check VMCPU_FF_UPDATE_APIC here. */

  • trunk/src/VBox/VMM/VMMR3/NEMR3Native-darwin-armv8.cpp

    r99575 r99576  
    10841084            return nemR3DarwinHandleExitException(pVM, pVCpu, pExit);
    10851085        case HV_EXIT_REASON_VTIMER_ACTIVATED:
     1086            /** @todo Set interrupt. */
    10861087            return VINF_EM_RESCHEDULE;
    10871088        default:
    … …  
    11241125{
    11251126#ifdef LOG_ENABLED
     1127    bool fIrq = false;
     1128    bool fFiq = false;
     1129
    11261130    if (LogIs3Enabled())
    11271131        nemR3DarwinLogState(pVM, pVCpu);
    … …  
    11321136    AssertRCReturn(rc, rc);
    11331137
    1134     LogFlowFunc(("Running vCPU\n"));
     1138    /* Set the pending interrupt state. */
     1139    if (VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INTERRUPT_IRQ | VMCPU_FF_INTERRUPT_FIQ))
     1140    {
     1141        hv_return_t hrc = HV_SUCCESS;
     1142
     1143        if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_IRQ))
     1144        {
     1145            hrc = hv_vcpu_set_pending_interrupt(pVCpu->nem.s.hVCpu, HV_INTERRUPT_TYPE_IRQ, true);
     1146            AssertReturn(hrc == HV_SUCCESS, VERR_NEM_IPE_9);
     1147#ifdef LOG_ENABLED
     1148            fIrq = true;
     1149#endif
     1150        }
     1151
     1152        if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_FIQ))
     1153        {
     1154            hrc = hv_vcpu_set_pending_interrupt(pVCpu->nem.s.hVCpu, HV_INTERRUPT_TYPE_FIQ, true);
     1155            AssertReturn(hrc == HV_SUCCESS, VERR_NEM_IPE_9);
     1156#ifdef LOG_ENABLED
     1157            fFiq = true;
     1158#endif
     1159        }
     1160    }
     1161    else
     1162    {
     1163        hv_return_t hrc = hv_vcpu_set_pending_interrupt(pVCpu->nem.s.hVCpu, HV_INTERRUPT_TYPE_IRQ, false);
     1164        AssertReturn(hrc == HV_SUCCESS, VERR_NEM_IPE_9);
     1165
     1166        hrc = hv_vcpu_set_pending_interrupt(pVCpu->nem.s.hVCpu, HV_INTERRUPT_TYPE_FIQ, false);
     1167        AssertReturn(hrc == HV_SUCCESS, VERR_NEM_IPE_9);
     1168    }
     1169
     1170    LogFlowFunc(("Running vCPU [%s,%s]\n", fIrq ? "I" : "nI", fFiq ? "F" : "nF"));
    11351171    pVCpu->nem.s.fEventPending = false;
    11361172    return VINF_SUCCESS;
    … …  
    12541290            || RT_FAILURE(rcStrict))
    12551291            fImport = CPUMCTX_EXTRN_ALL;
    1256         else if (VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INTERRUPT_PIC | VMCPU_FF_INTERRUPT_APIC
     1292        else if (VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_INTERRUPT_IRQ | VMCPU_FF_INTERRUPT_FIQ
    12571293                                          | VMCPU_FF_INTERRUPT_NMI | VMCPU_FF_INTERRUPT_SMI))
    12581294            fImport |= IEM_CPUMCTX_EXTRN_XCPT_MASK;

  • trunk/src/VBox/VMM/VMMR3/PDM.cpp

    r98122 r99576  
    10041004    {
    10051005        PVMCPU pVCpu = pVM->apCpusR3[idCpu];
     1006#if defined(VBOX_VMM_TARGET_ARMV8)
     1007        SSMR3PutU32(pSSM, VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_IRQ));
     1008        SSMR3PutU32(pSSM, VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_FIQ));
     1009#else
    10061010        SSMR3PutU32(pSSM, VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC));
    10071011        SSMR3PutU32(pSSM, VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_PIC));
     1012#endif
    10081013        SSMR3PutU32(pSSM, VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_NMI));
    10091014        SSMR3PutU32(pSSM, VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_SMI));
    … …  
    10341039    {
    10351040        PVMCPU pVCpu = pVM->apCpusR3[idCpu];
     1041#if defined(VBOX_VMM_TARGET_ARMV8)
     1042        LogFlow(("pdmR3LoadPrep: VCPU %u %s%s\n", idCpu,
     1043                VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_IRQ) ? " VMCPU_FF_INTERRUPT_IRQ" : "",
     1044                VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_FIQ) ? " VMCPU_FF_INTERRUPT_FIQ" : ""));
     1045#else
    10361046        LogFlow(("pdmR3LoadPrep: VCPU %u %s%s\n", idCpu,
    10371047                VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC) ? " VMCPU_FF_INTERRUPT_APIC" : "",
    10381048                VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_PIC)  ? " VMCPU_FF_INTERRUPT_PIC" : ""));
     1049#endif
    10391050    }
    10401051#endif
    … …  
    10521063    {
    10531064        PVMCPU pVCpu = pVM->apCpusR3[idCpu];
     1065#if defined(VBOX_VMM_TARGET_ARMV8)
     1066        VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_IRQ);
     1067        VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_FIQ);
     1068#else
    10541069        VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_APIC);
    10551070        VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_PIC);
     1071#endif
    10561072        VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI);
    10571073        VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_SMI);
    … …  
    11041120            PVMCPU pVCpu = pVM->apCpusR3[idCpu];
    11051121
    1106             /* APIC interrupt */
     1122            /* APIC/IRQ interrupt */
    11071123            uint32_t fInterruptPending = 0;
    11081124            rc = SSMR3GetU32(pSSM, &fInterruptPending);
    … …  
    11141130                return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
    11151131            }
     1132#if defined(VBOX_VMM_TARGET_ARMV8)
     1133            AssertLogRelMsg(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_IRQ),
     1134                            ("VCPU%03u: VMCPU_FF_INTERRUPT_IRQ set! Devices shouldn't set interrupts during state restore...\n", idCpu));
     1135            if (fInterruptPending)
     1136                VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_IRQ);
     1137#else
    11161138            AssertLogRelMsg(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC),
    11171139                            ("VCPU%03u: VMCPU_FF_INTERRUPT_APIC set! Devices shouldn't set interrupts during state restore...\n", idCpu));
    11181140            if (fInterruptPending)
    11191141                VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_APIC);
    1120 
    1121             /* PIC interrupt */
     1142#endif
     1143
     1144            /* PIC/FIQ interrupt */
    11221145            fInterruptPending = 0;
    11231146            rc = SSMR3GetU32(pSSM, &fInterruptPending);
    … …  
    11291152                return VERR_SSM_DATA_UNIT_FORMAT_CHANGED;
    11301153            }
     1154#if defined(VBOX_VMM_TARGET_ARMV8)
     1155            AssertLogRelMsg(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_FIQ),
     1156                            ("VCPU%03u: VMCPU_FF_INTERRUPT_FIQ set!  Devices shouldn't set interrupts during state restore...\n", idCpu));
     1157            if (fInterruptPending)
     1158                VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_FIQ);
     1159#else
    11311160            AssertLogRelMsg(!VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_INTERRUPT_PIC),
    11321161                            ("VCPU%03u: VMCPU_FF_INTERRUPT_PIC set!  Devices shouldn't set interrupts during state restore...\n", idCpu));
    11331162            if (fInterruptPending)
    11341163                VMCPU_FF_SET(pVCpu, VMCPU_FF_INTERRUPT_PIC);
     1164#endif
    11351165
    11361166            if (uVersion > PDM_SAVED_STATE_VERSION_PRE_NMI_FF)
    … …  
    16551685VMMR3_INT_DECL(void) PDMR3ResetCpu(PVMCPU pVCpu)
    16561686{
     1687#if defined(VBOX_VMM_TARGET_ARMV8)
     1688    VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_IRQ);
     1689    VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_FIQ);
     1690#else
    16571691    VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_APIC);
    16581692    VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_PIC);
     1693#endif
    16591694    VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_NMI);
    16601695    VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INTERRUPT_SMI);

  • trunk/src/VBox/VMM/VMMR3/VMEmt.cpp

    r98103 r99576  
    11071107 * @param   pVM         The cross context VM structure.
    11081108 * @param   pVCpu       The cross context virtual CPU structure.
    1109  * @param   fIgnoreInterrupts   If set the VM_FF_INTERRUPT flags is ignored.
     1109 * @param   fFlags      Combination of VMWAITHALTED_F_XXX.
    11101110 * @thread  The emulation thread.
    11111111 * @remarks Made visible for implementing vmsvga sync register.
    11121112 * @internal
    11131113 */
    1114 VMMR3_INT_DECL(int) VMR3WaitHalted(PVM pVM, PVMCPU pVCpu, bool fIgnoreInterrupts)
    1115 {
    1116     LogFlow(("VMR3WaitHalted: fIgnoreInterrupts=%d\n", fIgnoreInterrupts));
     1114VMMR3_INT_DECL(int) VMR3WaitHalted(PVM pVM, PVMCPU pVCpu, uint32_t fFlags)
     1115{
     1116    LogFlow(("VMR3WaitHalted: fFlags=%#x\n", fFlags));
    11171117
    11181118    /*
    11191119     * Check Relevant FFs.
    11201120     */
    1121     const uint32_t fMask = !fIgnoreInterrupts
     1121#if defined(VBOX_VMM_TARGET_ARMV8)
     1122    const uint32_t fMaskInterrupts =   ((fFlags & VMWAITHALTED_F_IGNORE_IRQS) ? VMCPU_FF_INTERRUPT_IRQ : 0)
     1123                                     | ((fFlags & VMWAITHALTED_F_IGNORE_FIQS) ? VMCPU_FF_INTERRUPT_FIQ : 0);
     1124    const uint32_t fMask = VMCPU_FF_EXTERNAL_HALTED_MASK & ~fMaskInterrupts;
     1125#else
     1126    const uint32_t fMask = !(fFlags & VMWAITHALTED_F_IGNORE_IRQS)
    11221127        ? VMCPU_FF_EXTERNAL_HALTED_MASK
    11231128        : VMCPU_FF_EXTERNAL_HALTED_MASK & ~(VMCPU_FF_UPDATE_APIC | VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC);
     1129#endif
     1130
    11241131    if (    VM_FF_IS_ANY_SET(pVM, VM_FF_EXTERNAL_HALTED_MASK)
    11251132        ||  VMCPU_FF_IS_ANY_SET(pVCpu, fMask))

  • trunk/src/VBox/VMM/VMMR3/VMM.cpp

    r99385 r99576  
    25572557        c = 0;
    25582558        f = fLocalForcedActions;
     2559#if defined(VBOX_VMM_TARGET_ARMV8)
     2560        PRINT_FLAG(VMCPU_FF_,INTERRUPT_IRQ);
     2561        PRINT_FLAG(VMCPU_FF_,INTERRUPT_FIQ);
     2562#else
    25592563        PRINT_FLAG(VMCPU_FF_,INTERRUPT_APIC);
    25602564        PRINT_FLAG(VMCPU_FF_,INTERRUPT_PIC);
     2565#endif
    25612566        PRINT_FLAG(VMCPU_FF_,TIMER);
    25622567        PRINT_FLAG(VMCPU_FF_,INTERRUPT_NMI);
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