Changeset 99577 in vbox
- Timestamp:
- May 3, 2023 10:30:42 AM (19 months ago)
- File:
-
- 1 edited
-
trunk/include/iprt/armv8.h (modified) (1 diff)
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- Unmodified
- Added
- Removed
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trunk/include/iprt/armv8.h
r99562 r99577 777 777 /** @} */ 778 778 779 780 /** @name TCR_EL1 - Translation Control Register (EL1) 781 * @{ 782 */ 783 /** Bit 0 - 5 - Size offset of the memory region addressed by TTBR0_EL1 (2^(64-T0SZ)). */ 784 #define ARMV8_TCR_EL1_AARCH64_T0SZ ( RT_BIT_64(0) | RT_BIT_64(1) | RT_BIT_64(2) \ 785 | RT_BIT_64(3) | RT_BIT_64(4) | RT_BIT_64(5)) 786 #define ARMV8_TCR_EL1_AARCH64_T0SZ_GET(a_Tcr) ((a_Tcr) & ARMV8_TCR_EL1_AARCH64_T1SZ) 787 /** Bit 7 - Translation table walk disable for translations using TTBR0_EL1. */ 788 #define ARMV8_TCR_EL1_AARCH64_EPD0 RT_BIT_64(7) 789 #define ARMV8_TCR_EL1_AARCH64_EPD0_BIT 7 790 /** Bit 8 - 9 - Inner cacheability attribute for memory associated with translation table walks using TTBR0_EL1. */ 791 #define ARMV8_TCR_EL1_AARCH64_IRGN0 (RT_BIT_64(8) | RT_BIT_64(9)) 792 #define ARMV8_TCR_EL1_AARCH64_IRGN0_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_IRGN0) >> 8) 793 /** Non cacheable. */ 794 # define ARMV8_TCR_EL1_AARCH64_IRGN0_NON_CACHEABLE 0 795 /** Write-Back, Read-Allocate, Write-Allocate Cacheable. */ 796 # define ARMV8_TCR_EL1_AARCH64_IRGN0_WB_RA_WA 1 797 /** Write-Through, Read-Allocate, No Write-Allocate Cacheable. */ 798 # define ARMV8_TCR_EL1_AARCH64_IRGN0_WT_RA_NWA 2 799 /** Write-Back, Read-Allocate, No Write-Allocate Cacheable. */ 800 # define ARMV8_TCR_EL1_AARCH64_IRGN0_WB_RA_NWA 3 801 /** Bit 27 - 26 - Outer cacheability attribute for memory associated with translation table walks using TTBR0_EL1. */ 802 #define ARMV8_TCR_EL1_AARCH64_ORGN0 (RT_BIT_64(10) | RT_BIT_64(11)) 803 #define ARMV8_TCR_EL1_AARCH64_ORGN0_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_ORGN0) >> 10) 804 /** Non cacheable. */ 805 # define ARMV8_TCR_EL1_AARCH64_ORGN0_NON_CACHEABLE 0 806 /** Write-Back, Read-Allocate, Write-Allocate Cacheable. */ 807 # define ARMV8_TCR_EL1_AARCH64_ORGN0_WB_RA_WA 1 808 /** Write-Through, Read-Allocate, No Write-Allocate Cacheable. */ 809 # define ARMV8_TCR_EL1_AARCH64_ORGN0_WT_RA_NWA 2 810 /** Write-Back, Read-Allocate, No Write-Allocate Cacheable. */ 811 # define ARMV8_TCR_EL1_AARCH64_ORGN0_WB_RA_NWA 3 812 /** Bit 12 - 13 - Shareability attribute memory associated with translation table walks using TTBR0_EL1. */ 813 #define ARMV8_TCR_EL1_AARCH64_SH0 (RT_BIT_64(12) | RT_BIT_64(13)) 814 #define ARMV8_TCR_EL1_AARCH64_SH0_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_SH0) >> 12) 815 /** Non shareable. */ 816 # define ARMV8_TCR_EL1_AARCH64_SH0_NON_SHAREABLE 0 817 /** Invalid value. */ 818 # define ARMV8_TCR_EL1_AARCH64_SH0_INVALID 1 819 /** Outer Shareable. */ 820 # define ARMV8_TCR_EL1_AARCH64_SH0_OUTER_SHAREABLE 2 821 /** Inner Shareable. */ 822 # define ARMV8_TCR_EL1_AARCH64_SH0_INNER_SHAREABLE 3 823 /** Bit 14 - 15 - Translation Granule Size for TTBR0_EL1. */ 824 #define ARMV8_TCR_EL1_AARCH64_TG0 (RT_BIT_64(14) | RT_BIT_64(15)) 825 #define ARMV8_TCR_EL1_AARCH64_TG0_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_TG0) >> 14) 826 /** Invalid granule size. */ 827 # define ARMV8_TCR_EL1_AARCH64_TG0_INVALID 0 828 /** 16KiB granule size. */ 829 # define ARMV8_TCR_EL1_AARCH64_TG0_16KB 1 830 /** 4KiB granule size. */ 831 # define ARMV8_TCR_EL1_AARCH64_TG0_4KB 2 832 /** 64KiB granule size. */ 833 # define ARMV8_TCR_EL1_AARCH64_TG0_64KB 3 834 /** Bit 16 - 21 - Size offset of the memory region addressed by TTBR1_EL1 (2^(64-T1SZ)). */ 835 #define ARMV8_TCR_EL1_AARCH64_T1SZ ( RT_BIT_64(16) | RT_BIT_64(17) | RT_BIT_64(18) \ 836 | RT_BIT_64(19) | RT_BIT_64(20) | RT_BIT_64(21)) 837 #define ARMV8_TCR_EL1_AARCH64_T1SZ_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_T1SZ) >> 16) 838 /** Bit 22 - Selects whether TTBR0_EL1 (0) or TTBR1_EL1 (1) defines the ASID. */ 839 #define ARMV8_TCR_EL1_AARCH64_A1 RT_BIT_64(22) 840 #define ARMV8_TCR_EL1_AARCH64_A1_BIT 22 841 /** Bit 23 - Translation table walk disable for translations using TTBR1_EL1. */ 842 #define ARMV8_TCR_EL1_AARCH64_EPD1 RT_BIT_64(23) 843 #define ARMV8_TCR_EL1_AARCH64_EPD1_BIT 23 844 /** Bit 24 - 25 - Inner cacheability attribute for memory associated with translation table walks using TTBR1_EL1. */ 845 #define ARMV8_TCR_EL1_AARCH64_IRGN1 (RT_BIT_64(24) | RT_BIT_64(25)) 846 #define ARMV8_TCR_EL1_AARCH64_IRGN1_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_IRGN1) >> 26) 847 /** Non cacheable. */ 848 # define ARMV8_TCR_EL1_AARCH64_IRGN1_NON_CACHEABLE 0 849 /** Write-Back, Read-Allocate, Write-Allocate Cacheable. */ 850 # define ARMV8_TCR_EL1_AARCH64_IRGN1_WB_RA_WA 1 851 /** Write-Through, Read-Allocate, No Write-Allocate Cacheable. */ 852 # define ARMV8_TCR_EL1_AARCH64_IRGN1_WT_RA_NWA 2 853 /** Write-Back, Read-Allocate, No Write-Allocate Cacheable. */ 854 # define ARMV8_TCR_EL1_AARCH64_IRGN1_WB_RA_NWA 3 855 /** Bit 27 - 26 - Outer cacheability attribute for memory associated with translation table walks using TTBR1_EL1. */ 856 #define ARMV8_TCR_EL1_AARCH64_ORGN1 (RT_BIT_64(26) | RT_BIT_64(27)) 857 #define ARMV8_TCR_EL1_AARCH64_ORGN1_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_ORGN1) >> 26) 858 /** Non cacheable. */ 859 # define ARMV8_TCR_EL1_AARCH64_ORGN1_NON_CACHEABLE 0 860 /** Write-Back, Read-Allocate, Write-Allocate Cacheable. */ 861 # define ARMV8_TCR_EL1_AARCH64_ORGN1_WB_RA_WA 1 862 /** Write-Through, Read-Allocate, No Write-Allocate Cacheable. */ 863 # define ARMV8_TCR_EL1_AARCH64_ORGN1_WT_RA_NWA 2 864 /** Write-Back, Read-Allocate, No Write-Allocate Cacheable. */ 865 # define ARMV8_TCR_EL1_AARCH64_ORGN1_WB_RA_NWA 3 866 /** Bit 28 - 29 - Shareability attribute memory associated with translation table walks using TTBR1_EL1. */ 867 #define ARMV8_TCR_EL1_AARCH64_SH1 (RT_BIT_64(28) | RT_BIT_64(29)) 868 #define ARMV8_TCR_EL1_AARCH64_SH1_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_SH1) >> 28) 869 /** Non shareable. */ 870 # define ARMV8_TCR_EL1_AARCH64_SH1_NON_SHAREABLE 0 871 /** Invalid value. */ 872 # define ARMV8_TCR_EL1_AARCH64_SH1_INVALID 1 873 /** Outer Shareable. */ 874 # define ARMV8_TCR_EL1_AARCH64_SH1_OUTER_SHAREABLE 2 875 /** Inner Shareable. */ 876 # define ARMV8_TCR_EL1_AARCH64_SH1_INNER_SHAREABLE 3 877 /** Bit 30 - 31 - Translation Granule Size for TTBR1_EL1. */ 878 #define ARMV8_TCR_EL1_AARCH64_TG1 (RT_BIT_64(30) | RT_BIT_64(31)) 879 #define ARMV8_TCR_EL1_AARCH64_TG1_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_TG1) >> 30) 880 /** Invalid granule size. */ 881 # define ARMV8_TCR_EL1_AARCH64_TG1_INVALID 0 882 /** 16KiB granule size. */ 883 # define ARMV8_TCR_EL1_AARCH64_TG1_16KB 1 884 /** 4KiB granule size. */ 885 # define ARMV8_TCR_EL1_AARCH64_TG1_4KB 2 886 /** 64KiB granule size. */ 887 # define ARMV8_TCR_EL1_AARCH64_TG1_64KB 3 888 /** Bit 32 - 34 - Intermediate Physical Address Size. */ 889 #define ARMV8_TCR_EL1_AARCH64_IPS (RT_BIT_64(32) | RT_BIT_64(33) | RT_BIT_64(34)) 890 #define ARMV8_TCR_EL1_AARCH64_IPS_GET(a_Tcr) (((a_Tcr) & ARMV8_TCR_EL1_AARCH64_IPS) >> 32) 891 /** IPA - 32 bits, 4GiB. */ 892 # define ARMV8_TCR_EL1_AARCH64_IPS_32BITS 0 893 /** IPA - 36 bits, 64GiB. */ 894 # define ARMV8_TCR_EL1_AARCH64_IPS_36BITS 1 895 /** IPA - 40 bits, 1TiB. */ 896 # define ARMV8_TCR_EL1_AARCH64_IPS_40BITS 2 897 /** IPA - 42 bits, 4TiB. */ 898 # define ARMV8_TCR_EL1_AARCH64_IPS_42BITS 3 899 /** IPA - 44 bits, 16TiB. */ 900 # define ARMV8_TCR_EL1_AARCH64_IPS_44BITS 4 901 /** IPA - 48 bits, 256TiB. */ 902 # define ARMV8_TCR_EL1_AARCH64_IPS_48BITS 5 903 /** IPA - 52 bits, 4PiB. */ 904 # define ARMV8_TCR_EL1_AARCH64_IPS_52BITS 6 905 /** Bit 36 - ASID Size (0 - 8 bit, 1 - 16 bit). */ 906 #define ARMV8_TCR_EL1_AARCH64_AS RT_BIT_64(36) 907 #define ARMV8_TCR_EL1_AARCH64_AS_BIT 36 908 /** Bit 37 - Top Byte Ignore for translations from TTBR0_EL1. */ 909 #define ARMV8_TCR_EL1_AARCH64_TBI0 RT_BIT_64(37) 910 #define ARMV8_TCR_EL1_AARCH64_TBI0_BIT 37 911 /** Bit 38 - Top Byte Ignore for translations from TTBR1_EL1. */ 912 #define ARMV8_TCR_EL1_AARCH64_TBI1 RT_BIT_64(38) 913 #define ARMV8_TCR_EL1_AARCH64_TBI1_BIT 38 914 /** Bit 39 - Hardware Access flag update in stage 1 translations from EL0 and EL1. */ 915 #define ARMV8_TCR_EL1_AARCH64_HA RT_BIT_64(39) 916 #define ARMV8_TCR_EL1_AARCH64_HA_BIT 39 917 /** Bit 40 - Hardware management of dirty state in stage 1 translations from EL0 and EL1. */ 918 #define ARMV8_TCR_EL1_AARCH64_HD RT_BIT_64(40) 919 #define ARMV8_TCR_EL1_AARCH64_HD_BIT 40 920 /** Bit 41 - Hierarchical Permission Disables for TTBR0_EL1. */ 921 #define ARMV8_TCR_EL1_AARCH64_HPD0 RT_BIT_64(41) 922 #define ARMV8_TCR_EL1_AARCH64_HPD0_BIT 41 923 /** Bit 42 - Hierarchical Permission Disables for TTBR1_EL1. */ 924 #define ARMV8_TCR_EL1_AARCH64_HPD1 RT_BIT_64(42) 925 #define ARMV8_TCR_EL1_AARCH64_HPD1_BIT 42 926 /** Bit 43 - Bit[59] Hardware Use for translations using TTBR0_EL1. */ 927 #define ARMV8_TCR_EL1_AARCH64_HWU059 RT_BIT_64(43) 928 #define ARMV8_TCR_EL1_AARCH64_HWU059_BIT 43 929 /** Bit 44 - Bit[60] Hardware Use for translations using TTBR0_EL1. */ 930 #define ARMV8_TCR_EL1_AARCH64_HWU060 RT_BIT_64(44) 931 #define ARMV8_TCR_EL1_AARCH64_HWU060_BIT 44 932 /** Bit 46 - Bit[61] Hardware Use for translations using TTBR0_EL1. */ 933 #define ARMV8_TCR_EL1_AARCH64_HWU061 RT_BIT_64(45) 934 #define ARMV8_TCR_EL1_AARCH64_HWU061_BIT 45 935 /** Bit 46 - Bit[62] Hardware Use for translations using TTBR0_EL1. */ 936 #define ARMV8_TCR_EL1_AARCH64_HWU062 RT_BIT_64(46) 937 #define ARMV8_TCR_EL1_AARCH64_HWU062_BIT 46 938 /** Bit 47 - Bit[59] Hardware Use for translations using TTBR1_EL1. */ 939 #define ARMV8_TCR_EL1_AARCH64_HWU159 RT_BIT_64(47) 940 #define ARMV8_TCR_EL1_AARCH64_HWU159_BIT 47 941 /** Bit 48 - Bit[60] Hardware Use for translations using TTBR1_EL1. */ 942 #define ARMV8_TCR_EL1_AARCH64_HWU160 RT_BIT_64(48) 943 #define ARMV8_TCR_EL1_AARCH64_HWU160_BIT 48 944 /** Bit 49 - Bit[61] Hardware Use for translations using TTBR1_EL1. */ 945 #define ARMV8_TCR_EL1_AARCH64_HWU161 RT_BIT_64(49) 946 #define ARMV8_TCR_EL1_AARCH64_HWU161_BIT 49 947 /** Bit 50 - Bit[62] Hardware Use for translations using TTBR1_EL1. */ 948 #define ARMV8_TCR_EL1_AARCH64_HWU162 RT_BIT_64(50) 949 #define ARMV8_TCR_EL1_AARCH64_HWU162_BIT 50 950 /** Bit 51 - Control the use of the top byte of instruction addresses for address matching for translations using TTBR0_EL1. */ 951 #define ARMV8_TCR_EL1_AARCH64_TBID0 RT_BIT_64(51) 952 #define ARMV8_TCR_EL1_AARCH64_TBID0_BIT 51 953 /** Bit 52 - Control the use of the top byte of instruction addresses for address matching for translations using TTBR1_EL1. */ 954 #define ARMV8_TCR_EL1_AARCH64_TBID1 RT_BIT_64(52) 955 #define ARMV8_TCR_EL1_AARCH64_TBID1_BIT 52 956 /** Bit 53 - Non fault translation table walk disable for stage 1 translations using TTBR0_EL1. */ 957 #define ARMV8_TCR_EL1_AARCH64_NFD0 RT_BIT_64(53) 958 #define ARMV8_TCR_EL1_AARCH64_NFD0_BIT 53 959 /** Bit 54 - Non fault translation table walk disable for stage 1 translations using TTBR1_EL1. */ 960 #define ARMV8_TCR_EL1_AARCH64_NFD1 RT_BIT_64(54) 961 #define ARMV8_TCR_EL1_AARCH64_NFD1_BIT 54 962 /** Bit 55 - Faulting Control for Unprivileged access to any address translated by TTBR0_EL1. */ 963 #define ARMV8_TCR_EL1_AARCH64_E0PD0 RT_BIT_64(55) 964 #define ARMV8_TCR_EL1_AARCH64_E0PD0_BIT 55 965 /** Bit 56 - Faulting Control for Unprivileged access to any address translated by TTBR1_EL1. */ 966 #define ARMV8_TCR_EL1_AARCH64_E0PD1 RT_BIT_64(56) 967 #define ARMV8_TCR_EL1_AARCH64_E0PD1_BIT 56 968 /** Bit 57 - TCMA0 */ 969 #define ARMV8_TCR_EL1_AARCH64_TCMA0 RT_BIT_64(57) 970 #define ARMV8_TCR_EL1_AARCH64_TCMA0_BIT 57 971 /** Bit 58 - TCMA1 */ 972 #define ARMV8_TCR_EL1_AARCH64_TCMA1 RT_BIT_64(58) 973 #define ARMV8_TCR_EL1_AARCH64_TCMA1_BIT 58 974 /** Bit 59 - Data Sharing(?). */ 975 #define ARMV8_TCR_EL1_AARCH64_DS RT_BIT_64(59) 976 #define ARMV8_TCR_EL1_AARCH64_DS_BIT 59 977 /** @} */ 978 979 980 /** @name TTBR<0,1>_EL1 - Translation Table Base Register <0,1> (EL1) 981 * @{ 982 */ 983 /** Bit 0 - Common not Private (FEAT_TTCNP). */ 984 #define ARMV8_TTBR_EL1_AARCH64_CNP RT_BIT_64(0) 985 #define ARMV8_TTBR_EL1_AARCH64_CNP_BIT 0 986 /** Bit 1 - 47 - Translation table base address. */ 987 #define ARMV8_TTBR_EL1_AARCH64_BADDR UINT64_C(0x0000fffffffffffe) 988 #define ARMV8_TTBR_EL1_AARCH64_BADDR_GET(a_Ttbr) (((a_Ttbr) & ARMV8_TTBR_EL1_AARCH64_BADDR) >> 1) 989 /** Bit 48 - 63 - ASID. */ 990 #define ARMV8_TTBR_EL1_AARCH64_ASID UINT64_C(0xffff000000000000) 991 #define ARMV8_TTBR_EL1_AARCH64_ASID_GET(a_Ttbr) (((a_Ttbr) & ARMV8_TTBR_EL1_AARCH64_ASID) >> 48) 992 /** @} */ 993 779 994 /** @} */ 780 995
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