Changeset 9961 in vbox for trunk

Timestamp:

Jun 26, 2008 2:39:54 PM (17 years ago)

Author:

vboxsync

svn:sync-xref-src-repo-rev:

32390

Message:

Extended the testcase.

File:

• trunk/src/VBox/HostDrivers/Support/testcase/tstGIP-2.cpp (modified) (5 diffs)

trunk/src/VBox/HostDrivers/Support/testcase/tstGIP-2.cpp

@@ -41 +41 @@
 #include <iprt/thread.h>
 #include <iprt/stream.h>
+#include <iprt/string.h>
 #include <iprt/initterm.h>
 #include <iprt/getopt.h>
@@ -54 +55 @@
     static const RTOPTIONDEF g_aOptions[] =
     {
-        { "--interations",      'i', RTGETOPT_REQ_INT32 }
+        { "--interations",      'i', RTGETOPT_REQ_INT32 },
+        { "--hex",              'h', RTGETOPT_REQ_NOTHING },
+        { "--decimal",          'd', RTGETOPT_REQ_NOTHING },
+        { "--spin",             's', RTGETOPT_REQ_NOTHING }
     };
 
     uint32_t cIterations = 40;
+    bool fHex = true;
+    bool fSpin = false;
     int ch;
     int iArg = 1;
@@ -67 +73 @@
             case 'i':
                 cIterations = ValueUnion.u32;
+                break;
+
+            case 'd':
+                fHex = false;
+                break;
+
+            case 'h':
+                fHex = true;
+                break;
+
+            case 's':
+                fSpin = true;
                 break;
 
@@ -92 +110 @@
         if (g_pSUPGlobalInfoPage)
         {
-            RTPrintf("tstGIP-2: u32UpdateHz=%RU32  u32UpdateIntervalNS=%RU32  u64NanoTSLastUpdateHz=%RX64  u32Mode=%d (%s) u32Version=%#x\n"
-                     "tstGIP-2:     it: u64NanoTS        u64TSC           UpIntTSC H TransId            CpuHz TSC Interval History...\n",
+            RTPrintf("tstGIP-2: u32UpdateHz=%RU32  u32UpdateIntervalNS=%RU32  u64NanoTSLastUpdateHz=%RX64  u32Mode=%d (%s) u32Version=%#x\n",
                      g_pSUPGlobalInfoPage->u32UpdateHz,
                      g_pSUPGlobalInfoPage->u32UpdateIntervalNS,
@@ -102 +119 @@
                      :                                                            "???",
                      g_pSUPGlobalInfoPage->u32Version);
+            RTPrintf(fHex
+                     ? "tstGIP-2:     it: u64NanoTS        delta     u64TSC           UpIntTSC H  TransId           CpuHz TSC Interval History...\n"
+                     : "tstGIP-2:     it: u64NanoTS        delta     u64TSC             UpIntTSC H    TransId           CpuHz TSC Interval History...\n");
+            static SUPGIPCPU s_aaCPUs[2][RT_ELEMENTS(g_pSUPGlobalInfoPage->aCPUs)];
             for (uint32_t i = 0; i < cIterations; i++)
             {
+                /* copy the data */
+                memcpy(&s_aaCPUs[i & 1][0], &g_pSUPGlobalInfoPage->aCPUs[0], sizeof(g_pSUPGlobalInfoPage->aCPUs));
+
+                /* display it & find something to spin on. */
+                uint32_t u32TransactionId = 0;
+                uint32_t volatile *pu32TransactionId = NULL;
                 for (unsigned iCpu = 0; iCpu < RT_ELEMENTS(g_pSUPGlobalInfoPage->aCPUs); iCpu++)
                     if (    g_pSUPGlobalInfoPage->aCPUs[iCpu].u64CpuHz > 0
                         &&  g_pSUPGlobalInfoPage->aCPUs[iCpu].u64CpuHz != _4G + 1)
-                        RTPrintf("tstGIP-2: %4d/%d: %016llx %016llx %08x %d %08x %15llu %08x %08x %08x %08x %08x %08x %08x %08x (%d)\n",
+                    {   
+                        PSUPGIPCPU pPrevCpu = &s_aaCPUs[!(i & 1)][iCpu];
+                        PSUPGIPCPU pCpu = &s_aaCPUs[i & 1][iCpu];
+                        RTPrintf(fHex
+                                 ? "tstGIP-2: %4d/%d: %016llx %09llx %016llx %08x %d %08x %15llu %08x %08x %08x %08x %08x %08x %08x %08x (%d)\n"
+                                 : "tstGIP-2: %4d/%d: %016llu %09llu %016llu %010u %d %010u %15llu %08x %08x %08x %08x %08x %08x %08x %08x (%d)\n",
                                  i, iCpu,
-                                 g_pSUPGlobalInfoPage->aCPUs[iCpu].u64NanoTS,
-                                 g_pSUPGlobalInfoPage->aCPUs[iCpu].u64TSC,
-                                 g_pSUPGlobalInfoPage->aCPUs[iCpu].u32UpdateIntervalTSC,
-                                 g_pSUPGlobalInfoPage->aCPUs[iCpu].iTSCHistoryHead,
-                                 g_pSUPGlobalInfoPage->aCPUs[iCpu].u32TransactionId,
-                                 g_pSUPGlobalInfoPage->aCPUs[iCpu].u64CpuHz,
-                                 g_pSUPGlobalInfoPage->aCPUs[iCpu].au32TSCHistory[0],
-                                 g_pSUPGlobalInfoPage->aCPUs[iCpu].au32TSCHistory[1],
-                                 g_pSUPGlobalInfoPage->aCPUs[iCpu].au32TSCHistory[2],
-                                 g_pSUPGlobalInfoPage->aCPUs[iCpu].au32TSCHistory[3],
-                                 g_pSUPGlobalInfoPage->aCPUs[iCpu].au32TSCHistory[4],
-                                 g_pSUPGlobalInfoPage->aCPUs[iCpu].au32TSCHistory[5],
-                                 g_pSUPGlobalInfoPage->aCPUs[iCpu].au32TSCHistory[6],
-                                 g_pSUPGlobalInfoPage->aCPUs[iCpu].au32TSCHistory[7],
-                                 g_pSUPGlobalInfoPage->aCPUs[iCpu].cErrors);
-                RTThreadSleep(9);
+                                 pCpu->u64NanoTS,
+                                 i ? pCpu->u64NanoTS - pPrevCpu->u64NanoTS : 0,
+                                 pCpu->u64TSC,
+                                 pCpu->u32UpdateIntervalTSC,
+                                 pCpu->iTSCHistoryHead,
+                                 pCpu->u32TransactionId,
+                                 pCpu->u64CpuHz,
+                                 pCpu->au32TSCHistory[0],
+                                 pCpu->au32TSCHistory[1],
+                                 pCpu->au32TSCHistory[2],
+                                 pCpu->au32TSCHistory[3],
+                                 pCpu->au32TSCHistory[4],
+                                 pCpu->au32TSCHistory[5],
+                                 pCpu->au32TSCHistory[6],
+                                 pCpu->au32TSCHistory[7],
+                                 pCpu->cErrors);
+                        if (!pu32TransactionId)
+                        {
+                            pu32TransactionId = &g_pSUPGlobalInfoPage->aCPUs[iCpu].u32TransactionId;
+                            u32TransactionId = pCpu->u32TransactionId;
+                        }
+                    }
+
+                /* wait a bit / spin */
+                if (!fSpin)
+                    RTThreadSleep(9);
+                else
+                    while (u32TransactionId == *pu32TransactionId)
+                        /* nop */;
             }
         }