Changeset 99814 in vbox for trunk

Timestamp:

May 16, 2023 4:32:30 PM (20 months ago)

Author:

vboxsync

Message:

IEM: Added a separate CPU flag to enable VEX decoding to allow BMI1/2 to be enabled without AVX (see bugref:5653).

Location:

trunk

Files:

• include/VBox/vmm/cpum-x86-amd64.h (modified) (2 diffs)
• src/VBox/VMM/VMMAll/CPUMAllCpuId.cpp (modified) (1 diff)
• src/VBox/VMM/VMMAll/IEMAllInstructionsOneByte.cpp.h (modified) (4 diffs)

trunk/include/VBox/vmm/cpum-x86-amd64.h

@@ -916 +916 @@
     uint32_t        fLeakyFxSR : 1;
 
+    /** Supports VEX instruction encoding (AVX, BMI, etc.). */
+    uint32_t        fVex : 1;
+
     /** AMD64: Supports AMD SVM. */
     uint32_t        fSvm : 1;
@@ -945 +948 @@
     /** Alignment padding / reserved for future use (96 bits total, plus 12 bytes
      *  prior to the bit fields -> total of 24 bytes) */
-    uint32_t        fPadding0 : 24;
+    uint32_t        fPadding0 : 23;
 
 

trunk/src/VBox/VMM/VMMAll/CPUMAllCpuId.cpp

@@ -1599 +1599 @@
                                           pFeatures->fXSaveRstor = 0);
         }
+
+        /*
+         * Enable or disable VEX support depending on whether it's needed. Note that AVX,
+         * BMI1, and BMI2 all use VEX encoding but are theoretically independent of each other.
+         */
+        pFeatures->fVex = pFeatures->fAvx | pFeatures->fBmi1 | pFeatures->fBmi2;
     }
     else

trunk/src/VBox/VMM/VMMAll/IEMAllInstructionsOneByte.cpp.h

@@ -7167 +7167 @@
     {
         IEMOP_MNEMONIC(vex3_prefix, "vex3");
-        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAvx)
+        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVex)
         {
             /* Note! The real mode, v8086 mode and invalid prefix checks are done once
@@ -7214 +7214 @@
             }
         }
-        Log(("VEX3: AVX support disabled!\n"));
+        Log(("VEX3: VEX support disabled!\n"));
         return IEMOP_RAISE_INVALID_OPCODE();
     }
@@ -7239 +7239 @@
     {
         IEMOP_MNEMONIC(vex2_prefix, "vex2");
-        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fAvx)
+        if (IEM_GET_GUEST_CPU_FEATURES(pVCpu)->fVex)
         {
             /* Note! The real mode, v8086 mode and invalid prefix checks are done once
@@ -7259 +7259 @@
 
         /** @todo does intel completely decode the sequence with SIB/disp before \#UD? */
-        Log(("VEX2: AVX support disabled!\n"));
+        Log(("VEX2: VEX support disabled!\n"));
         return IEMOP_RAISE_INVALID_OPCODE();
     }