VirtualBox

Changeset 99820 in vbox for trunk


Ignore:
Timestamp:
May 17, 2023 7:31:36 AM (21 months ago)
Author:
vboxsync
Message:

Devices/Bus: Implement interrupt forwarding for the PCIe bus, bugref:10445

Location:
trunk/src/VBox/Devices/Bus
Files:
3 edited

Legend:

Unmodified
Added
Removed

  • trunk/src/VBox/Devices/Bus/DevPCI.cpp

    r99775 r99820  
    290290DECLINLINE(int) get_pci_irq_level(PDEVPCIROOT pGlobals, int irq_num)
    291291{
    292     return (pGlobals->Piix3.auPciLegacyIrqLevels[irq_num] != 0);
     292    return (pGlobals->u.Piix3.auPciLegacyIrqLevels[irq_num] != 0);
    293293}
    294294
    … …  
    347347            /* As per above treat ACPI in a special way */
    348348            pic_irq = pPciDev->abConfig[PCI_INTERRUPT_LINE];
    349             pGlobals->Piix3.iAcpiIrq = pic_irq;
    350             pGlobals->Piix3.iAcpiIrqLevel = iLevel & PDM_IRQ_LEVEL_HIGH;
     349            pGlobals->u.Piix3.iAcpiIrq = pic_irq;
     350            pGlobals->u.Piix3.iAcpiIrqLevel = iLevel & PDM_IRQ_LEVEL_HIGH;
    351351        }
    352352        else
    … …  
    356356
    357357            if (pPciDev->Int.s.uIrqPinState == PDM_IRQ_LEVEL_HIGH)
    358                 ASMAtomicIncU32(&pGlobals->Piix3.auPciLegacyIrqLevels[irq_num]);
     358                ASMAtomicIncU32(&pGlobals->u.Piix3.auPciLegacyIrqLevels[irq_num]);
    359359            else if (pPciDev->Int.s.uIrqPinState == PDM_IRQ_LEVEL_LOW)
    360                 ASMAtomicDecU32(&pGlobals->Piix3.auPciLegacyIrqLevels[irq_num]);
     360                ASMAtomicDecU32(&pGlobals->u.Piix3.auPciLegacyIrqLevels[irq_num]);
    361361
    362362            /* now we change the pic irq level according to the piix irq mappings */
    … …  
    366366                if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP)
    367367                {
    368                     ASMAtomicDecU32(&pGlobals->Piix3.auPciLegacyIrqLevels[irq_num]);
     368                    ASMAtomicDecU32(&pGlobals->u.Piix3.auPciLegacyIrqLevels[irq_num]);
    369369                    pPciDev->Int.s.uIrqPinState = PDM_IRQ_LEVEL_LOW;
    370370                }
    … …  
    384384        if (pic_irq == pbCfg[0x63])
    385385            pic_level |= get_pci_irq_level(pGlobals, 3);    /* PIRQD */
    386         if (pic_irq == pGlobals->Piix3.iAcpiIrq)
    387             pic_level |= pGlobals->Piix3.iAcpiIrqLevel;
     386        if (pic_irq == pGlobals->u.Piix3.iAcpiIrq)
     387            pic_level |= pGlobals->u.Piix3.iAcpiIrqLevel;
    388388
    389389        Log3Func(("%s: iLevel=%d iIrq=%d pic_irq=%d pic_level=%d uTagSrc=%#x\n",
    … …  
    988988     * Save IRQ states.
    989989     */
    990     for (unsigned i = 0; i < RT_ELEMENTS(pThis->Piix3.auPciLegacyIrqLevels); i++)
    991         pHlp->pfnSSMPutU32(pSSM, pThis->Piix3.auPciLegacyIrqLevels[i]);
     990    for (unsigned i = 0; i < RT_ELEMENTS(pThis->u.Piix3.auPciLegacyIrqLevels); i++)
     991        pHlp->pfnSSMPutU32(pSSM, pThis->u.Piix3.auPciLegacyIrqLevels[i]);
    992992    for (unsigned i = 0; i < RT_ELEMENTS(pThis->auPciApicIrqLevels); i++)
    993993        pHlp->pfnSSMPutU32(pSSM, pThis->auPciApicIrqLevels[i]);
    994994
    995     pHlp->pfnSSMPutU32(pSSM, pThis->Piix3.iAcpiIrqLevel);
    996     pHlp->pfnSSMPutS32(pSSM, pThis->Piix3.iAcpiIrq);
     995    pHlp->pfnSSMPutU32(pSSM, pThis->u.Piix3.iAcpiIrqLevel);
     996    pHlp->pfnSSMPutS32(pSSM, pThis->u.Piix3.iAcpiIrq);
    997997
    998998    pHlp->pfnSSMPutU32(pSSM, UINT32_MAX);      /* separator */
    … …  
    11701170    if (uVersion >= VBOX_PCI_SAVED_STATE_VERSION_IRQ_STATES)
    11711171    {
    1172         for (uint8_t i = 0; i < RT_ELEMENTS(pThis->Piix3.auPciLegacyIrqLevels); i++)
    1173             pHlp->pfnSSMGetU32V(pSSM, &pThis->Piix3.auPciLegacyIrqLevels[i]);
     1172        for (uint8_t i = 0; i < RT_ELEMENTS(pThis->u.Piix3.auPciLegacyIrqLevels); i++)
     1173            pHlp->pfnSSMGetU32V(pSSM, &pThis->u.Piix3.auPciLegacyIrqLevels[i]);
    11741174        for (uint8_t i = 0; i < RT_ELEMENTS(pThis->auPciApicIrqLevels); i++)
    11751175            pHlp->pfnSSMGetU32V(pSSM, &pThis->auPciApicIrqLevels[i]);
    11761176
    1177         pHlp->pfnSSMGetU32(pSSM, &pThis->Piix3.iAcpiIrqLevel);
    1178         pHlp->pfnSSMGetS32(pSSM, &pThis->Piix3.iAcpiIrq);
     1177        pHlp->pfnSSMGetU32(pSSM, &pThis->u.Piix3.iAcpiIrqLevel);
     1178        pHlp->pfnSSMGetS32(pSSM, &pThis->u.Piix3.iAcpiIrq);
    11791179    }
    11801180
    … …  
    12301230    pHlp->pfnPrintf(pHlp, "PCI IRQ levels:\n");
    12311231    for (int i = 0; i < DEVPCI_LEGACY_IRQ_PINS; ++i)
    1232         pHlp->pfnPrintf(pHlp, "  IRQ%c: %u\n", 'A' + i, pGlobals->Piix3.auPciLegacyIrqLevels[i]);
     1232        pHlp->pfnPrintf(pHlp, "  IRQ%c: %u\n", 'A' + i, pGlobals->u.Piix3.auPciLegacyIrqLevels[i]);
    12331233}
    12341234
    … …  
    13011301    pGlobals->uPciBiosIo   = 0xc000;
    13021302    pGlobals->uPciBiosMmio = 0xf0000000;
    1303     memset((void *)&pGlobals->Piix3.auPciLegacyIrqLevels, 0, sizeof(pGlobals->Piix3.auPciLegacyIrqLevels));
     1303    memset((void *)&pGlobals->u.Piix3.auPciLegacyIrqLevels, 0, sizeof(pGlobals->u.Piix3.auPciLegacyIrqLevels));
    13041304    pGlobals->fUseIoApic   = fUseIoApic;
    13051305    memset((void *)&pGlobals->auPciApicIrqLevels, 0, sizeof(pGlobals->auPciApicIrqLevels));

  • trunk/src/VBox/Devices/Bus/DevPciGenericEcam.cpp

    r99752 r99820  
    6868*********************************************************************************************************************************/
    6969
     70/**
     71 * Returns the interrupt pin for a given device slot on the root port
     72 * due to swizzeling.
     73 *
     74 * @returns Interrupt pin on the root port.
     75 * @param   uDevFn      The device.
     76 * @param   uPin        The interrupt pin on the device.
     77 */
     78DECLINLINE(uint8_t) pciGenEcamGetPirq(uint8_t uDevFn, uint8_t uPin)
     79{
     80    uint8_t uSlot = (uDevFn >> 3) - 1;
     81    return (uPin + uSlot) & 3;
     82}
     83
     84
     85/**
     86 * Returns whether the interrupt line is asserted on the PCI root for the given pin.
     87 *
     88 * @returns Flag whther the interrupt line is asserted (true) or not (false).
     89 * @param   pPciRoot    The PCI root bus.
     90 * @param   u8IrqPin    The IRQ pin being checked.
     91 */
     92DECLINLINE(bool) pciGenEcamGetIrqLvl(PDEVPCIROOT pPciRoot, uint8_t u8IrqPin)
     93{
     94    return (pPciRoot->u.GenericEcam.auPciIrqLevels[u8IrqPin] != 0);
     95}
     96
     97
     98/**
     99 * @interface_method_impl{PDMPCIBUSREGCC,pfnSetIrqR3}
     100 */
    70101static DECLCALLBACK(void) pciGenEcamSetIrq(PPDMDEVINS pDevIns, PPDMPCIDEV pPciDev, int iIrq, int iLevel, uint32_t uTagSrc)
    71102{
    72103    PDEVPCIROOT pPciRoot = PDMINS_2_DATA(pDevIns, PDEVPCIROOT);
     104    PDEVPCIBUS  pBus = &pPciRoot->PciBus;
    73105    PDEVPCIBUSCC pBusCC = PDMINS_2_DATA_CC(pDevIns, PDEVPCIBUSCC);
    74106    uint8_t uDevFn = pPciDev->uDevFn;
     107    uint16_t const uBusDevFn = PCIBDF_MAKE(pBus->iBus, uDevFn);
    75108
    76109    LogFlowFunc(("invoked by %p/%d: iIrq=%d iLevel=%d uTagSrc=%#x\n", pDevIns, pDevIns->iInstance, iIrq, iLevel, uTagSrc));
    … …  
    96129    }
    97130
    98     PDEVPCIBUS pBus = &pPciRoot->PciBus;
    99131    LogFlowFunc(("PCI Dev %p : IRQ\n", pPciDev));
    100132
    … …  
    104136        pPciDev->Int.s.uIrqPinState = (iLevel & PDM_IRQ_LEVEL_HIGH);
    105137
    106         /** @todo */
     138        /* Get the pin. */
     139        uint8_t uIrqPin = devpciR3GetByte(pPciDev, VBOX_PCI_INTERRUPT_PIN);
     140        uint8_t uIrq = pciGenEcamGetPirq(pPciDev->uDevFn, uIrqPin);
     141
     142        if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_HIGH)
     143            ASMAtomicIncU32(&pPciRoot->u.GenericEcam.auPciIrqLevels[uIrq]);
     144        else if ((iLevel & PDM_IRQ_LEVEL_HIGH) == PDM_IRQ_LEVEL_LOW)
     145            ASMAtomicDecU32(&pPciRoot->u.GenericEcam.auPciIrqLevels[uIrq]);
     146
     147        bool fIrqLvl = pciGenEcamGetIrqLvl(pPciRoot, uIrq);
     148        uint32_t u32IrqNr = pPciRoot->u.GenericEcam.auPciIrqNr[uIrq];
     149
     150        Log3Func(("%s: uIrqPin=%u uIrqRoot=%u fIrqLvl=%RTbool uIrqNr=%u\n",
     151              R3STRING(pPciDev->pszNameR3), uIrqPin, uIrq, fIrqLvl, u32IrqNr));
     152        pBusCC->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pDevIns, uBusDevFn, u32IrqNr, fIrqLvl, uTagSrc);
     153
     154        if ((iLevel & PDM_IRQ_LEVEL_FLIP_FLOP) == PDM_IRQ_LEVEL_FLIP_FLOP) {
     155            ASMAtomicDecU32(&pPciRoot->u.GenericEcam.auPciIrqLevels[uIrq]);
     156            pPciDev->Int.s.uIrqPinState = PDM_IRQ_LEVEL_LOW;
     157            fIrqLvl = pciGenEcamGetIrqLvl(pPciRoot, uIrq);
     158            Log3Func(("%s: uIrqPin=%u uIrqRoot=%u fIrqLvl=%RTbool uIrqNr=%u\n",
     159                  R3STRING(pPciDev->pszNameR3), uIrqPin, uIrq, fIrqLvl, u32IrqNr));
     160            pBusCC->CTX_SUFF(pPciHlp)->pfnIoApicSetIrq(pDevIns, uBusDevFn, u32IrqNr, fIrqLvl, uTagSrc);
     161        }
    107162    }
    108163}
    … …  
    111166/**
    112167 * @callback_method_impl{FNIOMMMIONEWWRITE,
    113  * Emulates writes to configuration space.}
     168 * Emulates writes to PIO space.}
    114169 */
    115170static DECLCALLBACK(VBOXSTRICTRC) pciHostR3MmioPioWrite(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void const *pv, unsigned cb)
    … …  
    146201/**
    147202 * @callback_method_impl{FNIOMMMIONEWWRITE,
    148  * Emulates reads from configuration space.}
     203 * Emulates reads from PIO space.}
    149204 */
    150205static DECLCALLBACK(VBOXSTRICTRC) pciHostR3MmioPioRead(PPDMDEVINS pDevIns, void *pvUser, RTGCPHYS off, void *pv, unsigned cb)
    … …  
    156211    AssertReturn(cb <= 4, VERR_INVALID_PARAMETER);
    157212
    158     /* Perform configuration space read */
     213    /* Perform PIO space read */
    159214    uint32_t     u32Value = 0;
    160215    VBOXSTRICTRC rcStrict = PDMDevHlpIoPortRead(pDevIns, (RTIOPORT)off, &u32Value, cb);
    … …  
    205260     * Validate and read configuration.
    206261     */
    207     PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "MmioEcamBase|MmioEcamLength|MmioPioBase|MmioPioSize", "");
     262    PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "MmioEcamBase"
     263                                           "|MmioEcamLength"
     264                                           "|MmioPioBase"
     265                                           "|MmioPioSize"
     266                                           "|IntPinA"
     267                                           "|IntPinB"
     268                                           "|IntPinC"
     269                                           "|IntPinD", "");
    208270
    209271    int rc = pHlp->pfnCFGMQueryU64Def(pCfg, "MmioEcamBase", &pPciRoot->u64PciConfigMMioAddress, 0);
    … …  
    219281    AssertRCReturn(rc, PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"MmioPioSize\"")));
    220282
     283    rc = pHlp->pfnCFGMQueryU32(pCfg, "IntPinA", &pPciRoot->u.GenericEcam.auPciIrqNr[0]);
     284    AssertRCReturn(rc, PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"IntPinA\"")));
     285
     286    rc = pHlp->pfnCFGMQueryU32(pCfg, "IntPinB", &pPciRoot->u.GenericEcam.auPciIrqNr[1]);
     287    AssertRCReturn(rc, PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"IntPinB\"")));
     288
     289    rc = pHlp->pfnCFGMQueryU32(pCfg, "IntPinB", &pPciRoot->u.GenericEcam.auPciIrqNr[2]);
     290    AssertRCReturn(rc, PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"IntPinC\"")));
     291
     292    rc = pHlp->pfnCFGMQueryU32(pCfg, "IntPinB", &pPciRoot->u.GenericEcam.auPciIrqNr[3]);
     293    AssertRCReturn(rc, PDMDEV_SET_ERROR(pDevIns, rc, N_("Configuration error: Failed to read \"IntPinD\"")));
     294
    221295    Log(("PCI: fUseIoApic=%RTbool McfgBase=%#RX64 McfgLength=%#RX64 fR0Enabled=%RTbool fRCEnabled=%RTbool\n", pPciRoot->fUseIoApic,
    222296         pPciRoot->u64PciConfigMMioAddress, pPciRoot->u64PciConfigMMioLength, pDevIns->fR0Enabled, pDevIns->fRCEnabled));
     297    Log(("PCI: IntPinA=%u IntPinB=%u IntPinC=%u IntPinD=%u\n", pPciRoot->u.GenericEcam.auPciIrqNr[0],
     298         pPciRoot->u.GenericEcam.auPciIrqNr[1], pPciRoot->u.GenericEcam.auPciIrqNr[2], pPciRoot->u.GenericEcam.auPciIrqNr[3]));
    223299
    224300    /*

  • trunk/src/VBox/Devices/Bus/DevPciInternal.h

    r99750 r99820  
    177177    /** Alignment padding.   */
    178178    uint32_t            u32Alignment1;
    179     /** Members only used by the PIIX3 code variant.
    180      * (The PCI device for the PCI-to-ISA bridge is PDMDEVINSR3::apPciDevs[1].) */
    181     struct
     179    /** PCI bus dependent data. */
     180    union
    182181    {
    183         /** ACPI IRQ level */
    184         uint32_t            iAcpiIrqLevel;
    185         /** ACPI PIC IRQ */
    186         int32_t             iAcpiIrq;
    187         /** Irq levels for the four PCI Irqs.
    188          * These count how many devices asserted the IRQ line.  If greater 0 an IRQ
    189          * is sent to the guest.  If it drops to 0 the IRQ is deasserted.
    190          * @remarks Labling this "legacy" might be a bit off...
    191          */
    192         volatile uint32_t   auPciLegacyIrqLevels[DEVPCI_LEGACY_IRQ_PINS];
    193     } Piix3;
     182        /** Members only used by the PIIX3 code variant.
     183         * (The PCI device for the PCI-to-ISA bridge is PDMDEVINSR3::apPciDevs[1].) */
     184        struct
     185        {
     186            /** ACPI IRQ level */
     187            uint32_t            iAcpiIrqLevel;
     188            /** ACPI PIC IRQ */
     189            int32_t             iAcpiIrq;
     190            /** Irq levels for the four PCI Irqs.
     191             * These count how many devices asserted the IRQ line.  If greater 0 an IRQ
     192             * is sent to the guest.  If it drops to 0 the IRQ is deasserted.
     193             * @remarks Labling this "legacy" might be a bit off...
     194             */
     195            volatile uint32_t   auPciLegacyIrqLevels[DEVPCI_LEGACY_IRQ_PINS];
     196        } Piix3;
     197        /** Members only used by the generic ECAM variant. */
     198        struct
     199        {
     200            /** The interrupt config for INT#A ... INT#D. */
     201            uint32_t            auPciIrqNr[DEVPCI_LEGACY_IRQ_PINS];
     202            /** Irq levels for the four PCI Irqs.
     203             * These count how many devices asserted the IRQ line.  If greater 0 an IRQ
     204             * is sent to the guest.  If it drops to 0 the IRQ is deasserted.
     205             */
     206            volatile uint32_t   auPciIrqLevels[DEVPCI_LEGACY_IRQ_PINS];
     207        } GenericEcam;
     208    } u;
    194209
    195210    /** The address I/O port handle. */
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